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| | * | x86: fsp: Add more debugging for silicon initSimon Glass2020-09-251-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If locating the FSP header hangs for whatever reason it is useful to see where it got stuck. Add a debug print. Also show the address of the FSP-S entry point as a sanity check. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| | * | x86: apl: Check low-level init in FSP-S pre-initSimon Glass2020-09-251-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | If U-Boot is not running FSP-S it should not do the pre-init either. Add a condition to handle this. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * | x86: acpi: Set the log category for x86 table generationSimon Glass2020-09-251-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This file doesn't currently have a log category. Add one so that items are logged correctly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| | * | acpi: tpm: Add a TPM1 tableSimon Glass2020-09-251-1/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This provides information about a v1 TPM in the system. Generate this table if the TPM is present. Add a required new bloblist type and correct the header order of one header file. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * | acpi: tpm: Add a TPM2 tableSimon Glass2020-09-251-0/+74
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This provides information about a v2 TPM in the system. Generate this table if the TPM is present. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * | x86: Correct handling of MADT table CPUsSimon Glass2020-09-251-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | At present if hyperthreading is disabled the CPU numbering is not sequential. Fix this. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * | x86: Add a header guard to asm/acpi_table.hSimon Glass2020-09-251-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This file cannot currently be included in ASL files. Add a header guard to permit this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| | * | x86: Correct the assembly guard in e820.hSimon Glass2020-09-251-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is currently in the wrong place, so including the file in the device tree fails. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| | * | x86: Notify the FSP of the 'end firmware' eventSimon Glass2020-09-252-0/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Send this notification when U-Boot is about to boot into Linux, as requested by the FSP. Currently this causes a crash with the APL FSP, so leave it disabled for now. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * | x86: Sort the MTRR tableSimon Glass2020-09-251-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present the MTRR registers are programmed with the list the U-Boot builds up in the same order. In some cases this list may be out of order. It looks better in Linux to have the registers in order, so sort them, Signed-off-by: Simon Glass <sjg@chromium.org>
| | * | x86: cpu: Report address width from cpu_get_info()Simon Glass2020-09-254-0/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for this new field in the common code used by most x86 CPU drivers. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * | x86: fsp: Update the FSP API with the end-firmware methodSimon Glass2020-09-251-3/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This new method is intended to be called when UEFI shuts down the 'boot services', i.e. any lingering code in the boot loader that might be used by the OS. Add a definition for this new method and update the comments a little. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| | * | x86: apl: Drop unnecessary code in PMC driverSimon Glass2020-09-251-6/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | We don't have CONFIG_PCI in TPL but it is present in SPL, etc. So this code is not needed. Drop it, and fix a code-style nit just above. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * | x86: apl: Generate ACPI table for LPCSimon Glass2020-09-251-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | Add an ACPI table for the LPC on Apollo Lake. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * | x86: apl: Generate CPU tablesSimon Glass2020-09-252-1/+79
| | | | | | | | | | | | | | | | | | | | | | | | Add ACPI generation to the APL CPU driver. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * | x86: apl: Add support for hostbridge ACPI generationSimon Glass2020-09-251-9/+211
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Support generating a DMAR table and add a few helper routines as well. Also set up NHLT so that audio works. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * | x86: apl: Generate required ACPI tablesSimon Glass2020-09-253-0/+230
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for generating various ACPI tables for Apollo Lake. Add a few S3 definitions that are needed. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * | x86: apl: Allow reading hostbridge base addressesSimon Glass2020-09-252-0/+58
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a few functions to permit reading of various useful base addresses provided by the hostbridge. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * | x86: acpi: Add support for additional Intel tablesSimon Glass2020-09-252-0/+226
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Apollo Lake needs to generate a few more table types used on Intel SoCs. Add support for these into the x86 ACPI code. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * | x86: Support Atom SoCs using SWSMISCI rather than the SWSCISimon Glass2020-09-252-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Some Atom SoCs use SWSMISCI for SMI control. Add a Kconfig to select this. It is used on Apollo Lake. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * | x86: acpi: Add common Intel ACPI tablesSimon Glass2020-09-256-0/+474
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add various tables that are common to Intel CPUs. These functions can be used by arch-specific CPU code. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * | x86: acpi: Add PCT and PTC tablesSimon Glass2020-09-253-1/+132
| | | | | | | | | | | | | | | | | | | | | | | | | | | | These are needed for the CPU tables. Add them into an x86-specific file since we do not support them on sandbox, or include tests. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * | x86: acpi: Support generation of the DBG2 tableSimon Glass2020-09-252-0/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add an implementation of the DBG2 (Debug Port Table 2) ACPI table. Adjust one of the header includes to be in the correct order, before adding more. Note that the DBG2 table is generic but the PCI UART is x86-specific at present since it assumes an ns16550 UART. It can be generalised later if necessary. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * | x86: acpi: Support generation of the HPET tableSimon Glass2020-09-252-0/+69
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add an implementation of the HPET (High Precision Event Timer) ACPI table. Since this is x86-specific, put it in an x86-specific file Signed-off-by: Simon Glass <sjg@chromium.org>
| | * | x86: Add a few common Intel CPU functionsSimon Glass2020-09-252-0/+113
| | | | | | | | | | | | | | | | | | | | | | | | Add functions to query CPU information, needed for ACPI. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * | x86: apl: Update iomap for ACPISimon Glass2020-09-251-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add some more definitions to the iomap. These will be used by ACPI-generation code as well as the device tree. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * | x86: apl: Add power-management definitionsSimon Glass2020-09-251-1/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add SCI and power-state definitions required by ACPI tables. Fix the license to match the original source file. Als update the guard on acpi_pmc.h to avoid an error when buiding ASL. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * | x86: Add some definitions for SMMSimon Glass2020-09-251-0/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | U-Boot does not support SMM (System Management Mode) at present, but needs a few definitions to correctly set up the ACPI table. Add these. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * | x86: acpi: Add a common routine to write WiFi infoSimon Glass2020-09-253-0/+129
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Intel WiFi chips can use a common routine to write the information needed by linux. Add an implementation of this. Enable it for coral. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * | x86: apl: Support writing the IntelGraphicsMem tableSimon Glass2020-09-256-0/+460
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This table is needed by the Linux graphics driver to handle graphics correctly. Write it to ACPI. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * | x86: Add wake sources for the acpi_gpe driverSimon Glass2020-09-252-0/+138
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some devices can wake the system from sleep, e.g opening the lid on a clamshell or moving a USB mouse. Add a wake to specify this for USB devices and add the settings for Apollo Lake. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * | x86: acpi: Expand the GNVSSimon Glass2020-09-252-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Expand this to 4KB so that it is possible to add custom information to it. On Chromebooks this is used to pass verified-boot information. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * | x86: acpi: Support external GNVS tablesSimon Glass2020-09-254-12/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present U-Boot puts a magic number in the ASL for the GNVS table and searches for it later. Add a Kconfig option to use a different approach, where the ASL files declare the table as an external symbol. U-Boot can then put it wherever it likes, without any magic numbers or searching. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * | x86: Add a common global NVS structureSimon Glass2020-09-252-22/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the definition of this structure common to Intel devices. It includes some optional Chrome OS pieces which are used when vboot is integrated. Drop the APL version as it is basically the same. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * | x86: Add a config for the systemagent PCIEX regions sizeSimon Glass2020-09-252-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a way to specify the required size for this region. This is used when generating ACPI tables. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * | x86: acpi: Add DPTF asl filesSimon Glass2020-09-255-0/+950
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add common DPTF (Intel Dynamic Performance and Thermal Framework) files, taken from coreboot. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * | x86: acpi: apl: Add asl files for Apollo LakeSimon Glass2020-09-2518-0/+1261
| | | | | | | | | | | | | | | | | | | | | | | | Add Apollo Lake ASL files, taken from coreboot. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * | x86: acpi: Add base asl files for common x86 devicesSimon Glass2020-09-258-5/+443
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add common x86 ASL files, taken from coreboot. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
| | * | x86: acpi: Add cros_ec tablesSimon Glass2020-09-2510-0/+1405
| | | | | | | | | | | | | | | | | | | | | | | | Add ASL files for the Chrome OS EC, taken from coreboot. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * | x86: zboot: Allow overriding the command lineSimon Glass2020-09-253-9/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When booting Chrome OS images the command line is stored separately from the kernel. Add a way to specify this address so that images boot correctly. Also add comments to the zimage.h header. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: adjust maxargs to 8 for 'zboot start'] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
| | * | x86: zboot: Add an option to dump the setup informationSimon Glass2020-09-252-1/+199
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is a lot of information in the setup block and it is quite hard to decode manually. Add a 'zboot dump' command to decode it into a human-readable format. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| | * | x86: zboot: Allow setting a separate setup base addressSimon Glass2020-09-251-8/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present the setup block is always obtained from the image automatically. In some cases it can be useful to use a setup block obtained elsewhere, e.g. if the image has already been unpacked. Add an argument to support this and update the logic to use it if provided. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: adjust maxargs to 7 for 'zboot start'] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
| | * | x86: zboot: Set environment variables for image locationsSimon Glass2020-09-251-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present it is not possible to tell from a script where the setup block is, or where the image was loaded to. Add environment variables for this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| | * | x86: zboot: Add an 'setup' subcommandSimon Glass2020-09-251-7/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a subcommand that sets up the kernel ready for execution. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| | * | x86: zboot: Add an 'load' subcommandSimon Glass2020-09-251-7/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a subcommand that loads the kernel into the right places in memory. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: adjust ZBOOT_STATE_INFO value to match the command order] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
| | * | x86: zboot: Add an 'info' subcommandSimon Glass2020-09-251-3/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a little subcommand that prints out where the kernel was loaded and its setup pointer. Run it by default in the normal boot. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| | * | x86: zboot: Add a 'go' subcommandSimon Glass2020-09-251-4/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Split out the code that actually boots linux into a separate sub-command. Add base_ptr to the state to support this. Show an error if the boot fails, since this should not happen. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| | * | x86: zboot: Set up a sub-command structureSimon Glass2020-09-251-5/+61
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add subcommands to zboot. At present there is only one called 'start' which does the whole boot. It is the default command so is optional. Change the 's' string variable to const while we are here. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: reduce maxargs to 6 of 'zboot start' subcommand] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
| | * | x86: zimage: Disable interrupts just before bootingSimon Glass2020-09-251-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present if an error occurs while setting up the boot, interrupts are left disabled. Move this call later in the sequence to avoid this problem. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| | * | x86: zboot: Correct image typeSimon Glass2020-09-251-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present U-Boot sets a loader type of 8 which means LILO version 8, according to the spec. Update it to 0x80, which means U-Boot with no particular version. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
generated by cgit (git 2.34.1) at 2025-10-03 09:32:33 +0000