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| * | arm: socfpga: mailbox: Update mailbox response codesLey Foon Tan2020-10-091-2/+36
| | | | | | | | | | | | | | | | | | | | | Sync latest mailbox response codes from SDM firmware. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
| * | arm: socfpga: mailbox: Support sending large mailbox commandChee Hong Ang2020-10-091-35/+78
| | | | | | | | | | | | | | | | | | | | | | | | Mailbox command which is too large to fit into the mailbox FIFO command buffer can be sent to SDM in multiple parts. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
| * | arm: socfpga: mailbox: Always read mailbox responses before returning statusChee Hong Ang2020-10-091-4/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Mailbox driver should always check for the length of the response and read the response data before returning the response status to caller. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
| * | arm: socfpga: mailbox: Refactor mailbox timeout event handlingChee Hong Ang2020-10-091-4/+9
| | | | | | | | | | | | | | | | | | | | | | | | Add miliseconds delay when waiting for mailbox event to happen before timeout. This will ensure the timeout duration is predictive. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
| * | arm: socfpga: soc64: Document down boot_scratch_cold register usageChin Liang See2020-10-091-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Document down the usage of boot_scratch_cold register to avoid overlapping of usage in the code for S10 & Agilex. The boot_scratch_cold register is generally used for passing critical system info between SPL, U-Boot and Linux. Signed-off-by: Chin Liang See <chin.liang.see@intel.com> Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
| * | arm: socfpga: soc64: Add timeout waiting for NOC idle ACKChee Hong Ang2020-10-091-9/+16
| | | | | | | | | | | | | | | | | | | | | Add timeout waiting for NOC idle ACK during FPGA bridge disable/enable. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
| * | arm: socfpga: agilex: Enable FPGA Full Reconfiguration supportChee Hong Ang2020-10-091-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
| * | fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM MailboxChee Hong Ang2020-10-092-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
| * | arm: socfpga: Use DM watchdog timerChee Hong Ang2020-10-096-3/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | All SoCFPGA platforms (except Cyclone V) are now switching to CONFIG_WDT (driver model for watchdog timer drivers) from CONFIG_HW_WATCHDOG. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
| * | arm: socfpga: soc64: Show reset state in SPLChee Hong Ang2020-10-094-0/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | Print reset state (warm/cold) together with the source (watchdog/MPU) which has triggered the warm reset on S10 & Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
| * | arm: socfpga: soc64: Add SDM triggered warm reset bit maskChee Hong Ang2020-10-091-2/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | Include SDM triggered warm reset bit (BIT1) in Reset Manager's stat register when checking for HPS warm reset status. Refactor the warm reset mask macro for clarity purpose. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
| * | sysreset: socfpga: agilex: Enable sysreset supportChee Hong Ang2020-10-091-1/+1
| | | | | | | | | | | | | | | | | | | | | Enable sysreset support for Agilex platform. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
| * | sysreset: socfpga: soc64: Rename SYSRESET SoCFPGA driver for S10 to SoC64Chee Hong Ang2020-10-091-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Rename the driver from S10 to SoC64 because Intel Agilex platform also using the this SYSRESET SoCFPGA driver for S10. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
| * | arm: socfpga: soc64: Initialize timer in SPL onlyChee Hong Ang2020-10-091-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Timer only need to be initialized once in SPL. This patch remove the redundancy of initializing the timer again in U-Boot proper Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
| * | arm: socfpga: soc64: Remove PHY interface setup from misc arch initChee Hong Ang2020-10-091-83/+2
| |/ | | | | | | | | | | | | | | 'dwmac_socfpga' driver will setup the PHY interface during probe. PHY interface setup in arch_misc_init() is no longer needed. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
* | qemu-arm64: Enable POSITION_INDEPENDENTAndre Przywara2020-10-081-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | Now that PIE works when U-Boot is started from ROM, let's enable CONFIG_POSITION_INDEPENDENT, which allows to load U-Boot also via ARM Trusted-Firmware's fip.bin to DRAM, without tweaking the configuration. To get a writable initial stack, we need to keep the fixed initial stack pointer, which points to DRAM in our case. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
* | qemu-arm: Drop ARCH_SUPPORT_TFABOOTAndre Przywara2020-10-081-1/+0
| | | | | | | | | | | | | | | | | | | | CONFIG_ARCH_SUPPORT_TFABOOT was used on the qemu-arm64 platform to guard a tweak to the flash bank configuration. U-Boot now reads the current flash setup from the devicetree, so there is no need for this option anymore. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | arm64: PIE: Allow fixed stack pointerAndre Przywara2020-10-081-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently selecting CONFIG_POSITION_INDEPENDENT also forces us to use an initial stack pointer relative to the beginning of the BSS section. This makes some sense, because this should be writable memory anyway. However the BSS section is not cleared or used until later in the setup process (after relocation), so memory nearby might not be available early enough to host the initial stack. This is an issue if U-Boot is loaded from (Flash-)ROM, for instance. Allow CONFIG_INIT_SP_RELATIVE to be turned off by a board's config, to be able to select a fixed stack pointer, for instance in known good DRAM. This will help QEMU utilising PIE, when it's loaded to (Flash-)ROM. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
* | arm64: PIE: Skip fixups if distance is zeroAndre Przywara2020-10-081-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | When the actual offset between link and runtime address is zero, there is no need for patching up U-Boot early when running with CONFIG_POSITION_INDEPENDENT. Skip the whole routine when the distance is 0. This helps when U-Boot is loaded into ROM, or in otherwise sensitive memory locations. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
* | arm64: PIE: Do not skip static relocationAndre Przywara2020-10-081-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When we build an arm64 target and enable POSITION_INDEPENDENT, we were skipping our build-time dynamic relocation fixup routine (STATIC_RELA). This was probably done because we didn't need it in this case, as the PIE fixup routine in start.S would take care of that at runtime. However when we now skip this routine (upon detecting that the fixup offset is 0), this might lead to uninitialised pointers. Remove the exception, so that we always do the build-time relocation. NOTE: GNU binutils starting with v2.27.1 do this build-time relocation automatically, to be in-line with other architecures. So on newer toolchains our manual fixup is actually not needed. It doesn't hurt to have it, though, so that we keep compatibility with the popular Linaro toolchains, which lack this feature. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
* | arm: Kconfig: Explain TFABOOTAndre Przywara2020-10-081-2/+7
| | | | | | | | | | | | | | | | | | | | The CONFIG_TFABOOT option is more about what U-Boot DOES NOT need to do than to support some features. Explain a bit more in the Kconfig help text to avoid misunderstandings. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | riscv: add DT binding for BOOT button on Maix boardHeinrich Schuchardt2020-10-081-0/+11
| | | | | | | | | | | | | | | | | | Add a device tree binding for the BOOT button on the Maix board. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Sean Anderson <seanga2@gmail.com> Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
* | riscv: Add pinmux and gpio bindings for Kendryte K210Sean Anderson2020-10-082-0/+116
| | | | | | | | | | | | | | | | This patch adds the necessary device tree bindings. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Rick Chen <rick@andestech.com>
* | test: dm: Test for default led namingSean Anderson2020-10-081-1/+1
| | | | | | | | | | | | | | | | This modifies the existing led test to check for default led naming as added in the previous patch. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | test: pinmux: Add test for pin muxingSean Anderson2020-10-081-7/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This extends the pinctrl-sandbox driver to support pin muxing, and adds a test for that behaviour. The test is done in C and not python (like the existing tests for the pinctrl uclass) because it needs to call pinctrl_select_state. Another option could be to add a command that invokes pinctrl_select_state and then test everything in test/py/tests/test_pinmux.py. The pinctrl-sandbox driver now mimics the way that many pinmux devices work. There are two groups of pins which are muxed together, as well as four pins which are muxed individually. I have tried to test all normal paths. However, very few error cases are explicitly checked for. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | ram: move aspeed ram driver into drivers/ directoryDylan Hung2020-10-082-440/+1
|/ | | | | | | | to improve the maintainability. It is more easier to modify and add configurations of the driver in the centralized ram driver directory. Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
* Merge tag 'mips-pull-2020-10-07' of ↵Tom Rini2020-10-0721-14/+11033
|\ | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-mips - mips: octeon: add support for DDR4 memory controller - mips: octeon: add support for DWC3 USB - mips: octeon: add support for booting Linux
| * mips: octeon: Add bootoctlinux commandAaron Williams2020-10-073-0/+716
| | | | | | | | | | | | | | | | | | | | | | | | Octeon needs a platform specific cmd to boot the Linux kernel, as specific parameters need to be passed and special handling for the multiple cores (SMP) is needed. Co-developed-by: Stefan Roese <sr@denx.de> Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de> [use gd->ram_base instead of gd->bd->bi_memstart] Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * mips: octeon: Add bootmem supportAaron Williams2020-10-073-0/+1994
| | | | | | | | | | | | | | | | This is needed for Linux booting, as the memory infos need to be passed in this bootmem format to the Linux kernel. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * mips: octeon: Add coremask supportAaron Williams2020-10-073-0/+1119
| | | | | | | | | | | | | | This patch adds the coremask handling functions. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * mips: octeon: Add header cvmx-bootinfo.hAaron Williams2020-10-071-0/+350
| | | | | | | | | | | | | | | | Add header to handle bootinfo support, needed for Octeon Linux kernel booting. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * mips: octeon: Add header cvmx-fuse.hAaron Williams2020-10-071-0/+71
| | | | | | | | | | | | | | Add header to handle Octeon fuse access. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * mips: octeon: Add header octeon-feature.hAaron Williams2020-10-071-0/+442
| | | | | | | | | | | | | | | | This header includes the Octeon feature detection used in many Octeon drivers. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * mips: octeon: Add header cvmx-regs.hAaron Williams2020-10-071-0/+144
| | | | | | | | | | | | | | This header includes common register defines and accessor functions. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * mips: octeon: lowlevel_init.S: Add NMI handling code for SMP Linux bootingStefan Roese2020-10-071-0/+76
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the necessary lowlevel init code, to enable SMP Linux booting. This code will be used with the platform specific Octeon Linux boot command "bootoctlinux", which starts a configurable number of cores into Linux. Additionally some erratas and lowlevel register initializations are copied from the original Cavium / Marvell U-Boot source code, enabling booting into the Linux kernel. Signed-off-by: Stefan Roese <sr@denx.de>
| * mips: octeon: octeon-model.h: Enable inclusion from assembler filesStefan Roese2020-10-071-0/+4
| | | | | | | | | | | | | | Add the #ifdef __ASSEMBLY__ checks to enable inclusion of this header from assembler files. Signed-off-by: Stefan Roese <sr@denx.de>
| * mips: octeon: Add USB DT nodesStefan Roese2020-10-072-0/+84
| | | | | | | | | | | | | | Add the USB device tree nodes to the Octeon dts/dtsi files. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * mips: octeon: cache.c: Flush all pending writes in flush_dcache_range()Stefan Roese2020-10-071-6/+6
| | | | | | | | | | | | | | | | As noticed while working on the USB xHCI support, Octeon needs to flush all pending writes so that the values are present in the memory. Add this "syncw" instruction (twice) to flush_dcache_range(). Signed-off-by: Stefan Roese <sr@denx.de>
| * mips: octeon: Add mangle-port.hStefan Roese2020-10-071-0/+56
| | | | | | | | | | | | | | | | | | Import platform specific mangle-port.h header, allowing a area specific swapping, which is needed on Octeon for USB & PCI areas. Imported from Linux v5.7. Signed-off-by: Stefan Roese <sr@denx.de>
| * mips: octeon: cpu.c: Add table for selective swappingStefan Roese2020-10-071-0/+21
| | | | | | | | | | | | | | | | | | | | Import octeon_should_swizzle_table[] which is needed for the area specific swapping. It will be used by the platform specific mangle-port.h header. Imported from Linux v5.7. Signed-off-by: Stefan Roese <sr@denx.de>
| * mips: octeon: dram.c: Add RAM driver supportStefan Roese2020-10-071-8/+64
| | | | | | | | | | | | | | | | | | This patch adds the initialization call for the Octeon RAM driver to the Octeon platforms code. So if enabled via Kconfig, the DDR driver will be called and the RAM will be configured and used. If the RAM driver is not enabled, the L2 cache is still used as RAM. Signed-off-by: Stefan Roese <sr@denx.de>
| * mips: octeon: Add octeon_ddr.h headerAaron Williams2020-10-071-0/+982
| | | | | | | | | | | | | | | | This header will be used by the DDR driver (lmc). Its ported from the 2013 Cavium / Marvell U-Boot repository. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * mips: octeon Add cvmx/cvmx-lmcx-defs.h headerAaron Williams2020-10-071-0/+4574
| | | | | | | | | | | | | | | | This header will be used by the DDR driver (lmc). Its ported from the 2013 Cavium / Marvell U-Boot repository. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * mips: octeon: Add octeon-model.h headerAaron Williams2020-10-071-0/+313
| | | | | | | | | | | | | | | | This header is used by the upcoming DDR driver and potentially by other drivers ported from the 2013 Cavium / Marvell U-Boot repository. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * mips: octeon: dts: mrvl, cn73xx.dtsi: Add memory controller DT nodeStefan Roese2020-10-071-0/+17
| | | | | | | | | | | | | | | | This patch adds the memory controller (LMC) DT node to the Octeon 3 dtsi file. It also adds the L2C DT node, as this is referenced by the DDR driver. Signed-off-by: Stefan Roese <sr@denx.de>
* | Merge tag 'dm-pull-6oct20' of git://git.denx.de/u-boot-dmTom Rini2020-10-065-74/+107
|\ \ | |/ |/| | | | | | | bloblist enhancement for alignment Update ofnode/dev_read phandle function sandbox keyboard enhancements and fixes
| * sandbox: avoid duplicate backslash inputHeinrich Schuchardt2020-10-061-5/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | When using SDL for input the SDL key codes are first converted to Linux key codes and then to matrix entries of the cross wired keyboard. We must not map any key code to two different places on the keyboard. So comment out one backslash position. Update the rest of the file from Linux 5.7. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
| * sandbox: add missing SDL key scan codesHeinrich Schuchardt2020-10-061-67/+89
| | | | | | | | | | | | | | | | | | | | Add missing SDL key scan codes, e.g. * shift, ctrl, meta, alt * brace/bracket Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
| * test: dm: add test for phandle access functionsPatrick Delaunay2020-10-061-0/+1
| | | | | | | | | | | | | | | | | | | | | | Add unitary test for phandle access functions - ofnode_count_phandle_with_args - ofnode_parse_phandle_with_args - dev_count_phandle_with_args - dev_read_phandle_with_args Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * bloblist: Allow custom alignment for blobsSimon Glass2020-10-062-2/+2
| | | | | | | | | | | | | | | | | | Some blobs need a larger alignment than the default. For example, ACPI tables often start at a 4KB boundary. Add support for this. Update the size of the test blob to allow these larger records. Signed-off-by: Simon Glass <sjg@chromium.org>
generated by cgit (git 2.34.1) at 2025-10-02 23:07:47 +0000