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| * | sunxi: binman: Update FIT component descriptionsSamuel Holland2020-10-221-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since commit d879616e9e64 ("spl: fit: simplify logic for FDT loading for non-OS boots"), the SPL looks at the "os" properties of FIT images to determine where to append the FDT. The "os" property of the "firmware" image also determines how to execute the next stage of the boot process, as in 1d3790905d9c ("spl: atf: introduce spl_invoke_atf and make bl31_entry private"). For this reason, the next stage must be specified in "firmware", not in "loadables". To support this additional functionality, and to properly model the boot process, where ATF runs before U-Boot, add the "os" properties and swap the firmware/loadable images in the FIT image. Since this description was copied as an example in commit 70248d6a2916 ("binman: Support generating FITs with multiple dtbs"), update those examples as well for correctness and consistency. Acked-by: Patrick Wildt <patrick@blueri.se> Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * | sunxi: binman: Use a macro for the BL31 load addressSamuel Holland2020-10-221-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | This consolidates the SoC-specific part at the top of the file to avoid cluttering it up with preprocessor conditions. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * | sunxi: binman: Provide a default BL31 filenameSamuel Holland2020-10-221-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Prior to commit 7f7f8aca8257 ("sunxi: Convert 64-bit boards to use binman"), if the BL31 environment variable was not defined, the firmware would be loaded from a file "bl31.bin" in the current directory. Restore that behavior by providing that as the default filename in case no entry arg is provided, which will be the case if the environment variable is unset. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * | sunxi: binman: Fix spacing between nodesSamuel Holland2020-10-221-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | Nodes should have a blank line separating them from sibling nodes and properties. Add the necessary lines. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * | sunxi: make V3s DRAM initialization more properIcenowy Zheng2020-10-222-5/+87
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously, because we have no source code about the DRAM initialization of V3s and missing some configurations (delays and MBUS QoS info), our V3s DRAM initialization sequence is hacked from the H3 one. As the SDK shipped with PineCube contains source code for V3s libdram, we can retrieve these information from it and tweak some other magic bits. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
* | | arch: arm/xen: add putc() for debuggingAKASHI Takahiro2020-10-221-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This new function, xen_debug_putc(), is intended to be used to enable CONFIG_DEBUG_UART on xen guest. Please note that the underlying functionality in Xen is available only when Xen is configured with !NDEBUG but is much simpler than a generic HYPERVISOR_console_io(). Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org> Reviewed-by: Peng Fan <peng.fan@nxp.com>
* | | reset: ast2500: Use SCU for reset controlChia-Wei, Wang2020-10-221-4/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The System Control Unit (SCU) controller of Aspeed SoCs provides the reset control for each peripheral. This patch refactors the reset method to leverage the SCU reset control. Thus the driver dependency on watchdog including dedicated WDT API and reset flag encoding can be eliminated. The Kconfig description is also updated accordingly. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
* | | IPQ40xx: Add PRNG supportRobert Marko2020-10-222-0/+11
| | | | | | | | | | | | | | | | | | | | | Since we now have the driver for Qualcomm PRNG HW, lets use it and add the necessary clocks and nodes. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr>
* | | IPQ40xx: Add support for MDIORobert Marko2020-10-222-0/+32
| | | | | | | | | | | | | | | | | | | | | Lets add the necessary DTS node and pinctrl properties for newly added MDIO driver. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr>
* | | IPQ40xx: Add SPI supportRobert Marko2020-10-223-2/+30
| | | | | | | | | | | | | | | | | | | | | Since we have SPI driver for IPQ40xx QUP SPI controller, lets add the necessary nodes, pinctrl and clocks. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr>
* | | km: fix license string and compatible stringsHolger Brunck2020-10-2217-27/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As the ownership is now Hitachi Power Grids, change the license string and adapt the compatible string in DTS files. For kmeter1.dts we change it to "keymile,KMETER1" for now, as this is then compliant with what is submitted to the linux kernel. All other boards don't have a upstreamed version in linux mainline. Signed-off-by: Holger Brunck <holger.brunck@hitachi-powergrids.com> CC: Valentin Longchamp <valentin.longchamp@hitachi-powergrids.com> CC: Heiko Schocher <hs@denx.de> CC: Marek Vasut <marex@denx.de> CC: Tom Rini <trini@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | timer: Return count from timer_ops.get_countSean Anderson2020-10-222-8/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | No timer drivers return an error from get_count. Instead of possibly returning an error, just return the count directly. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | Merge tag 'u-boot-stm32-20201021' of ↵Tom Rini2020-10-226-74/+22
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-stm - Activate CMD_EXPORTENV/CMD_IMPORTENV/CMD_ELF for STM32MP15 defconfig - Fix stm32prog command: parsing of FlashLayout without partition - Update MAINTAINERS for ARM STM STM32MP - Manage eth1addr on dh board with KS8851 - Limit size of cacheable DDR in pre-reloc stage in stm32mp1 - Use mmc_of_parse() to read host capabilities in mmc:sdmmc2 driver
| * | | stm32mp: stm32prog: accept device without partitionPatrick Delaunay2020-10-211-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When partitions are not available on a device the command stm32prog raises an error but a device can have no partition to check in init_device() and the command need to continue to the next part_id. This patch correct an issue for ram0 target, when block_dev and mtd are NULL. For example with the simple flashlayout file: Opt Part Name Type Device Offset Binary - 0x01 fsbl Binary none 0x0 tf-a-serialboot.stm32 - 0x03 ssbl Binary none 0x0 u-boot.stm32 P 0x10 kernel System ram0 0xC2000000 uImage.bin P 0x11 dtb FileSytem ram0 0xC4000000 stm32mp157f-ev1.dtb Fixes: ffc405e63b94 ("stm32mp: stm32prog: add upport of partial update") Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
| * | | arm: stm32: cleanup arch gpio.hPatrick Delaunay2020-10-212-70/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Cosmetic update of gpio.h: - remove enumerate: stm32_gpio_port, stm32_gpio_pin because STM32_GPIO_XXX values are unused - move STM32_GPIOS_PER_BANK in stm32_gpio.c as its value is IP dependent and not arch dependent No functional change as number of banks and number of gpio by banks is managed by device tree since since DM migration and commit 8f651ca60ba1 ("pinctrl: stm32: Add get_pins_count() ops"). Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
| * | | stm32mp: limit size of cacheable DDR in pre-reloc stagePatrick Delaunay2020-10-213-2/+17
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In pre-reloc stage, U-Boot marks cacheable the DDR limited by the new config CONFIG_DDR_CACHEABLE_SIZE. This patch allows to avoid any speculative access to DDR protected by firewall and used by OP-TEE; the "no-map" reserved memory node in DT are assumed after this limit: STM32_DDR_BASE + DDR_CACHEABLE_SIZE. Without security, in basic boot, the value is equal to STM32_DDR_SIZE. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
* | | Merge branch '2021.01-rc' of https://github.com/lftan/u-bootTom Rini2020-10-221-2/+2
|\ \ \ | | | | | | | | | | | | - fix Gen5 enable of EMAC via FPGA
| * | | arm: socfpga: fix Gen5 enable of EMAC via FPGARalph Siemsen2020-10-211-2/+2
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | An earlier conversion from struct to defines introduced two errors, both related to setup of EMAC routed via the FPGA. One of the offsets was incorrect, and the EMAC0/EMAC1 were swapped. The effect of this was rather odd: both ports could operate at gigabit, but one of them would fail to transmit when operating at 100Mbit. Fixes: db5741f7a85ec3ee79b64496172afaa7dc2cb225 ("arm: socfpga: Convert system manager from struct to defines") Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
* | | Merge https://gitlab.denx.de/u-boot/custodians/u-boot-shTom Rini2020-10-202-1/+1973
|\ \ \ | | | | | | | | | | | | - Assorted R-Car Gen3 updates
| * | | clk: renesas: Import R8A774C0 clock tables from Linux 5.9Lad Prabhakar2020-10-201-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Import RZ/G2E (R8A774C0) clock tables from Linux 5.9 commit bbf5c979011a ("Linux 5.9"). Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
| * | | clk: renesas: Add R8A774E1 clock tablesBiju Das2020-10-201-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This sync's the RZ/G2H clock tables with mainline linux 5.9 commit bbf5c979011a ("Linux 5.9"). Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
| * | | clk: renesas: Add R8A774B1 clock tablesBiju Das2020-10-201-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This sync's the RZ/G2N clock tables with mainline linux 5.9 commit bbf5c979011a ("Linux 5.9"). Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
| * | | arm: dts: r8a774c0: Import DTS from Linux 5.9Lad Prabhakar2020-10-201-0/+1960
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Import R8A774C0 (RZ/G2E) SoC DTSI and headers from Linux 5.9 commit bbf5c979011a ("Linux 5.9"). Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
| * | | arm: renesas: Add config option for R8A774C0 SoCLad Prabhakar2020-10-201-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add config support for RZ/G2E (a.k.a R8A774C0) SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
| * | | arm: renesas: Add config option for R8A774E1 SoCBiju Das2020-10-201-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add config support for RZ/G2H(a.k.a R8A774E1) SoC. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
| * | | arm: renesas: Add config option for R8A774B1 SoCBiju Das2020-10-201-1/+4
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | Add config support for RZ/G2N(a.k.a R8A774B1) SoC. Also fixed the alignment issue on R8A774A1 config. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
* / / arm: dts: mt8512: add usb related nodesChunfeng Yun2020-10-202-1/+82
|/ / | | | | | | | | | | | | Add usb, usb phy, and fixed regulators nodes Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Acked-by: Bin Meng <bmeng.cn@gmail.com>
* | ARM: at91: Add chip ID for SAM9X60 SiPNicolas Ferre2020-10-192-0/+9
| | | | | | | | | | | | SAM9X60 SiP (System in Package) are added for SoC identification. Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
* | ARM: dts: sam9x60: use alphabetical orderClaudiu Beznea2020-10-191-14/+13
| | | | | | | | | | | | Use alphabetical order for entries in sam9x60ek-u-boot.dtsi Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
* | ARM: dts: sam9x60: use CCF compatibles for PMCClaudiu Beznea2020-10-193-164/+33
| | | | | | | | | | | | | | Use CCF compatible for PMC. With this, the board/SoC will be able to boot. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
* | ARM: dts: sam9x60: use slow clock CCF compatible bindingsClaudiu Beznea2020-10-192-47/+20
| | | | | | | | | | | | | | | | Use slow clock CCF compatible DT bindings. This will not break the above functionality as the SoC is not booting with current PMC bindings. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
* | ARM: dts: sam9x60: use u-boot,dm-pre-relocClaudiu Beznea2020-10-191-0/+8
| | | | | | | | | | | | Use u-boot,dm-pre-reloc for slow xtal and main xtal. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
* | ARM: dts: sam9x60ek: add clock frequencies to board fileClaudiu Beznea2020-10-192-2/+10
| | | | | | | | | | | | | | Slow Xtal and Main Xtal are board specific. Add their proper frequency to board file. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
* | Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvellTom Rini2020-10-161-0/+2
|\ \ | | | | | | | | | | | | | | | - Fix Octeon SPI driver for Octeon TX2 - Fix and enhance Octeon watchdog driver - Misc minor enhancements to Octeon TX/TX2
| * | arm: octeontx: Select CLKStefan Roese2020-10-161-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Clock support is needed for all Octeon TX/TX2 boards. This patch selects CONFIG_CLK so that it is available. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Aaron Williams <awilliams@marvell.com> Cc: Suneel Garapati <sgarapati@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com>
* | | arm: fsl-layerscape: Include device_compat.h in soc.cTom Rini2020-10-161-0/+1
|/ / | | | | | | | | | | Necessary for dev_xxx. Signed-off-by: Tom Rini <trini@konsulko.com>
* | Merge tag 'mmc-2020-10-14' of ↵Tom Rini2020-10-151-0/+2
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-mmc - fsl_esdhc_imx cleanup - not send cm13 if send_status is 0. - Add reinit API - Add mmc HS400 for fsl_esdhc - Several cleanup for fsl_esdhc - Add ADMA2 for sdhci
| * | arm: dts: lx2160ardb: support eMMC HS400 modeYangbo Lu2020-10-121-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add properties related to eMMC HS400 mode. mmc-hs400-1_8v; bus-width = <8>; They had been already in kernel dts file since the first lx2160ardb dts patch. b068890 arm64: dts: add LX2160ARDB board support Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
* | | Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvellTom Rini2020-10-145-159/+611
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Octeon TX: Add NAND driver (Suneel) - Octeon TX: Add NIC driver driver (Suneel) - Octeon TX2: Add NIC driver driver (Suneel) - Armada 8040: Add iEi Puzzle-M80 board support (Luka) - Armada A37xx SPI: Add support for CS-GPIO (George) - Espressobin: Use Linux model/compatible strings (Andre) - Espressobin: Add armada-3720-espressobin-emmc.dts from Linux (Andre) - Armada A37xx: Small cleanup of config header (Pali)
| * | | arm64: dts: a3720: add support for espressobin with populated emmcAndre Heider2020-10-142-0/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Import armada-3720-espressobin-emmc.dts from Linux, but use sdhc1 for emmc, since our dtsi is still based on downstream and sdhc0 is used for the sd card. Signed-off-by: Andre Heider <a.heider@gmail.com>
| * | | arm64: dts: armada-3720-espressobin: split common parts to .dtsiAndre Heider2020-10-142-157/+174
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move most of the dts to the new common armada-3720-espressobin.dtsi file, just like Linux, but keep the current, downstream based, version. The dts itself is imported from Linux. Signed-off-by: Andre Heider <a.heider@gmail.com>
| * | | arm64: dts: armada-3720-espressobin: use Linux model/compatible stringsAndre Heider2020-10-141-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the actual board vendor and ease synching dts files from Linux. Signed-off-by: Andre Heider <a.heider@gmail.com> Reviewed-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
| * | | arm: mvebu: Initial iEi Puzzle-M801 supportLuka Kovacic2020-10-142-0/+390
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add initial U-Boot support for the iEi Puzzle-M801 board based on the Marvell Armada 88F8040 SoC. Currently supported hardware: 1x USB 3.0 4x Gigabit Ethernet 2x SFP+ (with NXP PCA9555 and NXP PCA9544) 1x SATA 3.0 1x M.2 type B 1x RJ45 UART 1x SPI flash 1x EPSON RX8010 RTC Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr> Reviewed-by: Stefan Roese <sr@denx.de>
* | | | arm: enable DM_RNG on QEMU by defaultHeinrich Schuchardt2020-10-141-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The EFI_RNG_PROTOCOL is needed for address randomization in Linux. We should provide it by default on QEMU. Reported-by: François Ozog <francois.ozog@linaro.org> Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
* | | | test: sharpen button label unit testHeinrich Schuchardt2020-10-142-8/+8
|/ / / | | | | | | | | | | | | | | | | | | | | | Using different strings for the device tree node labels and the label property of buttons sharpens the button label unit test. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Philippe Reynes <philippe.reynes@softathome.com>
* | | Merge branch 'for-next' of https://github.com/lftan/u-bootTom Rini2020-10-1220-485/+971
|\ \ \ | |/ / |/| |
| * | arm: dts: socfpga: arria10: Move to use generic handoff dtsiLey Foon Tan2020-10-093-330/+292
| | | | | | | | | | | | | | | | | | | | | Move to use generic handoff dtsi (socfpga_arria10-handoff.dtsi) and include the specify generated _handoff.h header file from qts-filter-a10.sh script. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
| * | arm: socfpga: arria10: Add handoff header for A10 SoCDK SDMMCDalon Westergreen2020-10-091-0/+305
| | | | | | | | | | | | | | | | | | | | | | | | Add the qts-filter-a10.sh generated handoff header file for the Arria10 SoCDK SDMMC u-boot device tree. Signed-off-by: Dalon Westergreen <dalon.westergreen@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
| * | arm: socfpga: arria10: Add qts-filter for Arria10 socfpgaDalon Westergreen2020-10-091-0/+141
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add a script to process HPS handoff data and generate a header for inclusion in u-boot specific devicetree addons. The header should be included in the top level of u-boot.dtsi. Signed-off-by: Dalon Westergreen <dalon.westergreen@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
| * | arm: socfpga: mailbox: Add mailbox retry supportLey Foon Tan2020-10-091-9/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Resend mailbox command for 3 times with 2ms interval in between if it receives MBOX_RESP_TIMEOUT and MBOX_RESP_DEVICE_BUSY response code. Add a wrapper function mbox_send_cmd_common_retry() for retry, change all the callers to use this wrapper function. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
generated by cgit (git 2.34.1) at 2025-10-02 21:40:23 +0000