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| * | board: Rename uclass to sysinfoSimon Glass2020-11-062-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This uclass is intended to provide a way to obtain information about a U-Boot board. But the concept of a U-Boot 'board' is the whole system, not just one circuit board, meaning that 'board' is something of a misnomer for this uclass. In addition, the name 'board' is a bit overused in U-Boot and we want to use the same uclass to provide SMBIOS information. The obvious name is 'system' but that is so vague as to be meaningless. Use 'sysinfo' instead, since this uclass is aimed at providing information on the system. Rename everything accordingly. Note: Due to the patch delta caused by the symbol renames, this patch shows some renamed files as being deleted in one place and created in another. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: zimage: Quieten down the zimage boot processSimon Glass2020-11-061-5/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | Much of the output is not very useful. The bootm command is quite a bit quieter. Convert some output to use log_debug(). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>
| * | x86: zimage: Sanity-check the kernel version before printing itSimon Glass2020-11-061-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With Chrome OS the kernel setup block is stored in a separate place from the kernel, so it is not possible to access the kernel version string. At present, garbage is printed. Add a sanity check to avoid this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: zimage: Add a little more loggingSimon Glass2020-11-061-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | Add logging for each part of the boot process, using a new Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>
| * | x86: fsp: Adjust calculations for MTRR range and DRAM topSimon Glass2020-11-061-13/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present the top of available DRAM is the same as the top of the range of the low-memory MTRR. In fact, U-Boot is allowed to use memory up until the start of the FSP reserved memory. Use that value for low_end, since it makes more memory available. Keep the same calculation as before for mtrr_top, i.e. the top of reserved memory. A side-effect of this change is that the E820 tables have a single entry that extends from the bottom of the memory used by U-Boot to the bottom of the FSP reserved memory. This includes the bloblist, if ACPI tables are placed there. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: acpi: Don't show the UART address by defaultSimon Glass2020-11-061-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is useful when using Linux's earlycon since the MMIO address must be provided on some platforms, e.g.: earlycon=uart8250,mmio32,0xddffc000,115200n8 However this is only for debugging, so don't show it by default. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: acpi: Include the TPMv1 table only if neededSimon Glass2020-11-061-8/+11
| | | | | | | | | | | | | | | | | | | | | | | | This table is not needed if a v2 TPM is in use. Add a condition to avoid adding it when not needed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: Silence some logging statementsSimon Glass2020-11-065-11/+11
| | | | | | | | | | | | | | | | | | | | | | | | Quite a few log_info() calls are included in the x86 code which should use log_debug() instead. Convert them to reduce unwanted output. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: fsp: Convert fsp_dram to use log_debug()Simon Glass2020-11-061-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | Use log_debug() instead of debug() in this file, to enable the extra features. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: Set up Chrome OS to boot into developer modeSimon Glass2020-11-061-6/+20
| | | | | | | | | | | | | | | | | | | | | | | | Set up a few fields necessarily to make Chrome OS boot without showing a firmware error. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: Use CONFIG_CHROMEOS_VBOOT for verified bootSimon Glass2020-11-065-7/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present CONFIG_CHROMEOS is used to determine whether verified boot is in use. The code to implement that is not in U-Boot mainline. However, it is useful to be able to boot a Chromebook in developer mode in U-Boot mainline without needing the verified boot code. To allow this, use CONFIG_CHROMEOS_VBOOT to indicate that verified boot should be used, and CONFIG_CHROMEOS to indicate that the board supports Chrome OS. That allows us to define CONFIG_CHROMEOS on coral. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: Define the Chrome OS GNVS regionSimon Glass2020-11-061-1/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | It is not possible to boot Chrome OS properly without passing some basic information from U-Boot. This applies even if verified boot is not being used. Add a structure definition for this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | acpi: Don't reset the tables with every new generationSimon Glass2020-11-061-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | At present if SSDT and DSDT code is created, only the latter is retained for examination by the 'acpi items' command. Fix this by only resetting the list when explicitly requested. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: acpi: Put the generated code first in DSDTSimon Glass2020-11-061-9/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current implementation for DSDT tables is not correct for the case where there is generated code, as the length ends up being incorrect. Also, we want the generated code to go first in the table. Rewrite this piece to correct these problems. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: acpi: Allow the SSDT to be emptySimon Glass2020-11-061-7/+15
| | | | | | | | | | | | | | | | | | | | | | | | If there is nothing in the SSDT we should not include it in the tables. Update the implementation to check this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: Show the interrupt pointer with 'irqinfo'Simon Glass2020-11-063-7/+27
| | | | | | | | | | | | | | | | | | | | | | | | It is useful for this command to show the address of the interrupt table. Add support for this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: nhlt: Fix a few bugs in the table generationSimon Glass2020-11-061-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | At present these tables do not have the correct header, and there is an occasional incorrect value due to uninited data. Fix these bugs. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: nhlt: Correct output of bytes and 16-bit dataSimon Glass2020-11-061-3/+10
| | | | | | | | | | | | | | | | | | | | | | | | At present these functions are incorrect. Fix them and add some logging and checking to avoid future problems. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: Allow putting some tables in the bloblistSimon Glass2020-11-061-3/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present all tables are placed starting at address f0000 in memory, and can be up to 64KB in size. If the tables are very large, this may not provide enough space. Also if the tables point to other tables (such as console log or a ramoops area) then we must allocate other memory anyway. The bloblist is a nice place to put these tables since it is contiguous, which makes it easy to reserve this memory for linux using the 820 tables. Add an option to put some of the tables in the bloblist. For SMBIOS and ACPI, create suitable pointers from the f0000 region to the new location of the tables. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/project/uboot/patch/ 20201105062407.1.I8091ad931cbbb5e3b6f6ababdf3f8d5db0d17bb9@changeid/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: Use if instead of #ifdef in write_tables()Simon Glass2020-11-051-19/+19
| | | | | | | | | | | | | | | | | | | | | Use if() to remove the extra build path in this code. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: Add SMBIOS info for CoralSimon Glass2020-11-051-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | This is required by Chrome OS so that the audio and other unibuild features work correctly. Add it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: coral: Drop the duplicate PCIe settingsSimon Glass2020-11-051-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | These settings are included twice. The second lot are correct, so drop the others. Signed-off-by: Simon Glass <sjg@chromium.org> Reported-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: Don't bother clearing global NVSSimon Glass2020-11-051-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | The bloblist guarantees that blobs are zeroed so there is no need to do an additional memset(). Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: acpi: Store the ACPI context in global_dataSimon Glass2020-11-051-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present we create the ACPI context but then drop it after generation of tables is complete. This is annoying because we have to then search for tables later. To fix this, allocate the context and store it in global_data. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: Allow writing tables to failSimon Glass2020-11-053-3/+15
| | | | | | | | | | | | | | | | | | | | | | | | At present write_tables() can fail but does not report this problem to its caller. Fix this by changing the return type. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: Add support for private filesSimon Glass2020-11-051-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some boards need to include binary data into the image for use during the boot process. Add a node for these. An example is the audio-codec configuration used by some audio drivers on Intel platforms. If no private files are provided, they will be omitted. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: Add a layout for Chrome OS verified bootSimon Glass2020-11-051-0/+38
| | | | | | | | | | | | | | | | | | | | | Add definitions for part of the vboot context used with verified boot. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: apl: Add core init for the SoCSimon Glass2020-11-057-21/+170
| | | | | | | | | | | | | | | | | | | | | | | | Set up MSRs required for Apollo Lake. This enables Linux to use the timers correctly. Also write the fixed MSRs for this platform. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: Fix up driver names to avoid dtoc warningsSimon Glass2020-11-059-12/+12
| |/ | | | | | | | | | | | | | | | | | | | | | | At present there are a lot of dtoc warnings reported when building chromebook_coral, of the form: WARNING: the driver intel_apl_lpc was not found in the driver list Correct these by using driver names that matches their compatible string. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | Merge tag 'u-boot-imx-20201105' of ↵Tom Rini2020-11-0512-8/+1063
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-imx u-boot-imx for 2021.1 --------------------- - new boards : GE (new B1x5v2), phytec phyCORE-i.MX8MM - converted doc to reST - fixes for verdin-imx8mm (Toradex) - fixes for i.MX thermal driver - mx7ulp: Align the PLL_USB frequency - mx53: primary/secondary bmode Travis: https://travis-ci.org/github/sbabic/u-boot-imx/builds/741465284
| * board: ge: b1x5v2: Add GE B1x5v2 and B1x5Pv2Sebastian Reichel2020-11-013-0/+664
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | GE B1x5v2 patient monitor series is similar to the CARESCAPE Monitor series (GE Bx50). It consists of a carrier PCB used in combination with a Congatec QMX6 SoM. This adds U-Boot support using device model everywhere and SPL for memory initialization. Proper configuration is provided as 'ge_b1x5v2_defconfig' and the combined image u-boot-with-spi.imx can be flashed directly to 1024 byte offset to /dev/mtdblock0. Alternatively SPL and u-boot.imx can be loaded separately via USB-OTG using e.g. imx_usb. Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * imx6: allow usage of disable_ldb_di_clock_sources for CONFIG_MX6QDLSebastian Reichel2020-11-011-1/+1
| | | | | | | | | | | | | | Allow using disable_ldb_di_clock_sources with just the combined CONFIG_MX6QDL being enabled. Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
| * board: phytec: imx8mm: Add PHYTEC phyCORE-i.MX8MM supportTeresa Remmet2020-11-014-0/+366
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support PHYTEC phyCORE-i.MX8MM SOM. Supported features: - 2GB LPDDR4 RAM - 1x 1Gbit Ethernet - eMMC - external SD - debug UART3 - watchdog - i2c eeprom Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
| * ARM: imx: Add support for the primary/secondary bmode to MX53Marek Vasut2020-11-011-1/+20
| | | | | | | | | | | | | | | | | | | | | | Implement the 'getprisec' subcommand of 'bmode' command for i.MX53 and also the primary/secondary bootmode switching. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: NXP i.MX U-Boot Team <uboot-imx@nxp.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
| * dts: Provide LED DTS description for HSC and DDC imx53 devicesLukasz Majewski2020-11-011-0/+4
| | | | | | | | | | | | Those two LEDs are used to indicate U-Boot's boot stage. Signed-off-by: Lukasz Majewski <lukma@denx.de>
| * mx7ulp: clock: Align the PLL_USB frequencyFabio Estevam2020-11-011-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The command 'clocks' shows the following output: => clocks PLL_A7_SPLL 528 MHz PLL_A7_APLL 529 MHz PLL_USB 0 MHz Add some extra spaces so that the PLL_USB information gets aligned with the previous reported frequencies. Signed-off-by: Fabio Estevam <festevam@gmail.com>
| * mx7ulp: clock: Remove unuseful informationFabio Estevam2020-11-011-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The command 'clocks' shows the following output: => clocks PLL_A7_SPLL 528 MHz PLL_A7_APLL 529 MHz PLL_USB 0 MHz .... [do_mx7_showclocks] addr = 0x9FFB61F1 The last line is not useful at all, so just remove it. Signed-off-by: Fabio Estevam <festevam@gmail.com>
| * imx: cpu: terminate line with CR if invalid temp sensorTim Harvey2020-11-011-1/+2
| | | | | | | | | | | | | | | | Ensure we terminate the line with a CR if we get an invalid sensor device or reading. Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Fabio Estevam <festevam@gmail.com>
| * mx6: peripheral clock from oscillatorJorge Ramirez-Ortiz2020-11-011-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to be able to run the I2C bus at 400Khz, the chip errata[1] recommends that the peripheral clock runs out of the 24MHz oscillator. Systems running I2C from OP-TEE before Linux executes - for example to access a Secure Element [2] providing the cryptographic support - expect this clock to be configured by the bootloader [3]. [1] IMX6SLCE Rev. 5, 02/2019, ERR007805. [2] OP-TEE: support for NXP SE05X Plug and Trust (patch on the list). [3] OP-TEE: check the imx_i2c.c driver (imx6 patch on the list). Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io> Reviewed-by: Fabio Estevam <festevam@gmail.com>
* | arch: Move NEEDS_MANUAL_RELOC symbol to KconfigMichal Simek2020-11-043-6/+5
| | | | | | | | | | | | | | | | | | CONFIG_NEEDS_MANUAL_RELOC macro was out of Kconfig. Move it there to be able to use compile-time checks to reduce the number of build paths. Fixes: f9a882438966 ("dm: core: Convert #ifdef to if() in root.c") for Microblaze Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | Merge tag 'u-boot-atmel-fixes-2021.01-a' of ↵Tom Rini2020-11-029-9/+9
|\ \ | |/ |/| | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-atmel First set of u-boot-atmel fixes for 2021.01 cycle: This specific feature set includes the patches for DT required to fix the warnings for newer DTC version (1.6.0+), i2c and spi bus unit address.
| * ARM: dts: at91: sama5d3xmb_cmp: fix SPI bus unit addressEugen Hristev2020-11-021-1/+1
| | | | | | | | | | | | w+arch/arm/dts/.at91sam9260ek.dtb.pre.tmp:119.21-123.7: Warning (spi_bus_reg): /ahb/apb/spi@fffc8000/mtd_dataflash@0: SPI bus unit address format error, expected "1" Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
| * ARM: dts: at91: sam9260ek: fix SPI bus unit addressEugen Hristev2020-11-021-1/+1
| | | | | | | | | | | | w+arch/arm/dts/.at91sam9260ek.dtb.pre.tmp:119.21-123.7: Warning (spi_bus_reg): /ahb/apb/spi@fffc8000/mtd_dataflash@0: SPI bus unit address format error, expected "1" Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
| * ARM: dts: at91: sama5d3xmb: fix I2C bus unit addressEugen Hristev2020-11-021-1/+1
| | | | | | | | | | | | w+arch/arm/dts/sama5d3xmb.dtsi:64.25-83.7: Warning (i2c_bus_reg): /ahb/apb/i2c@f0018000/camera@0x30: I2C bus unit address format error, expected "30" Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
| * ARM: dts: at91: gurnard: fix SPI bus unit addressEugen Hristev2020-11-021-1/+1
| | | | | | | | | | | | w+arch/arm/dts/.at91sam9g45-gurnard.dtb.pre.tmp:118.21-122.7: Warning (spi_bus_reg): /ahb/apb/spi@fffa4000/mtd_dataflash@0: SPI bus unit address format error, expected "1" Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
| * ARM: dts: at91: at91sam9g25ek: fix I2C bus unit addressEugen Hristev2020-11-021-1/+1
| | | | | | | | | | | | w+arch/arm/dts/.at91sam9g25ek.dtb.pre.tmp:28.25-47.7: Warning (i2c_bus_reg): /ahb/apb/i2c@f8010000/camera@0x30: I2C bus unit address format error, expected "30" Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
| * ARM: dts: at91: at91sam9g20ek_common: fix SPI bus unit addressEugen Hristev2020-11-021-1/+1
| | | | | | | | | | | | w+arch/arm/dts/at91sam9g20ek_common.dtsi:100.21-104.7: Warning (spi_bus_reg): /ahb/apb/spi@fffc8000/mtd_dataflash@0: SPI bus unit address format error, expected "1" Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
| * ARM: dts: at91: at91sam9g20-taurus: fix SPI bus unit addressEugen Hristev2020-11-021-1/+1
| | | | | | | | | | | | w+arch/arm/dts/.at91sam9g20-taurus.dtb.pre.tmp:79.18-83.4: Warning (spi_bus_reg): /ahb/apb/spi@fffc8000/mtd_dataflash@0: SPI bus unit address format error, expected "1" Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
| * ARM: dts: at91: at91sam9261ek: fix SPI unit address warningEugen Hristev2020-11-021-1/+1
| | | | | | | | | | | | w+arch/arm/dts/.at91sam9261ek.dtb.pre.tmp:124.15-144.7: Warning (spi_bus_reg): /ahb/apb/spi@fffc8000/tsc2046@0: SPI bus unit address format error, expected "2" Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
| * ARM: dts: at91: vinco: fix I2C warning bus unit addressEugen Hristev2020-11-021-1/+1
| | | | | | | | | | | | w+arch/arm/dts/.at91-vinco.dtb.pre.tmp:131.18-134.7: Warning (i2c_bus_reg): /ahb/apb/i2c@f8024000/rtc@64: I2C bus unit address format error, expected "32" Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
generated by cgit (git 2.34.1) at 2025-10-02 16:51:21 +0000