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| * | | | Revert "arm64: dts: armada-3720-espressobin: split common parts to .dtsi"Pali Rohár2020-12-072-174/+157
| | | | | | | | | | | | | | | | | | | | This reverts commit 03bb6a9b1ed7085794c5f167307273d15c99d3f0.
| * | | | arm: mvebu: a38x: Configurable USB2 high-speed impedance thresholdJoshua Scott2020-12-072-3/+9
| |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Hardware testing of a board using the Armada 385 has shown that an impedance threshold setting of 0x7 performs better in an eye-diagram test than with Marvell's recommended value 0x6. As other boards may still perform better with Marvell's reccomended value, a configuration option is added with a default value of 0x6. Signed-off-by: Joshua Scott <joshua.scott@alliedtelesis.co.nz> Reviewed-by: Stefan Roese <sr@denx.de>
* / / / configs: cei-tk1-som: remove CONFIG_ARMV7_PSCI in include filePatrick Delaunay2020-12-041-0/+1
|/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Activate ARCH_SUPPORT_PSCI as other TEGRA124 target and remove CONFIG_ARMV7_PSCI and CONFIG_ARMV7_PSCI_NR_CPUS in configs file as they are migrated in Kconfig. Select CONFIG_ARMV7_PSCI_0_1 (the first PSCI version), because CONFIG_ARMV7_PSCI_0_2 and CONFIG_ARMV7_PSCI_1_0 are not activated in this product. Hi, This patch depend on the previous serie [1]. I don't test this patch on real hardware but after this patch the size of the binary don't change. In .config we have: CONFIG_ARCH_SUPPORT_PSCI=y CONFIG_ARMV7_PSCI=y # CONFIG_ARMV7_PSCI_1_0 is not set # CONFIG_ARMV7_PSCI_0_2 is not set CONFIG_ARMV7_PSCI_0_1=y CONFIG_ARMV7_PSCI_NR_CPUS=4 In u-boot.cfg, this patch only add the 2 lines #define CONFIG_ARCH_SUPPORT_PSCI 1 #define CONFIG_ARMV7_PSCI_0_1 1 [1] "Convert CONFIG_ARMV7_PSCI_1_0 and CONFIG_ARMV7_PSCI_0_2 to Kconfig" http://patchwork.ozlabs.org/project/uboot/list/?series=184029 Regards Patrick END Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Peter Chubb <peter.chubb@data61.csiro.au> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | | mips: octeon: tools: Add update_octeon_header toolStefan Roese2020-11-302-222/+172
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a tool to update or insert an Octeon specific header into the U-Boot image. This is needed e.g. for booting via SPI NOR, eMMC and NAND. While working on this, move enum cvmx_board_types_enum and cvmx_board_type_to_string() to cvmx-bootloader.h and remove the unreferenced (unsupported) board definition. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Aaron Williams <awilliams@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* | | mips: octeon: bootoctlinux: Use gd->ram_size instead of ram_get_info()Stefan Roese2020-11-301-18/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Using ram_get_info() is complicated and does not work after relocation. Now that gd->ram_size holds the full RAM size, let's use it instead and remove the ram_get_size logic completely. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Aaron Williams <awilliams@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* | | mips: octeon: Report full DDR size in dram_init() to gd->ram_sizeStefan Roese2020-11-301-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With this patch, gd->ram_size now holds to full RAM size detected by the DDR init code. It introduces the get_effective_memsize() function to report the maximum usable RAM size in U-Boot to the system instead. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Aaron Williams <awilliams@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* | | mips: start.S: Add Octeon boot header compatibilityStefan Roese2020-11-301-2/+8
| |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Octeon has a specific boot header, when booted via SPI NOR, NAND or MMC. Here the only 2 instructions are allowed in the first few bytes of the image. And these instructions need to be one branch and a nop. This patch adds the necessary nop after the nop, to that the common MIPS image is compatible with this Octeon header. The tool to patch the Octeon boot header into the image will be send in a follow-up patch. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Aaron Williams <awilliams@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* | riscv: sifive/fu540: kconfig: Enable support for Opencores I2C controllerPragnesh Patel2020-11-281-0/+2
| | | | | | | | | | | | | | Enable support for SiFive FU540 Opencores I2C master controller. Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
* | remoteproc: stm32: use reset for hold bootPatrick Delaunay2020-11-251-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the reset function to handle the hold boot bit in RCC with device tree handle with MCU_HOLD_BOOT identifier. This generic reset allows to remove the two specific properties: - st,syscfg-holdboot - st,syscfg-tz This patch prepares alignment with kernel device tree. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Cc: Fabien DESSENNE <fabien.dessenne@st.com> Cc: Arnaud POULIQUEN <arnaud.pouliquen@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
* | SPL: stm32mp1: fix spl_mmc_boot_partition not definedRichard Genoud2020-11-251-0/+2
| | | | | | | | | | | | | | | | spl_mmc_boot_partition is only defined when CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION is defined. Signed-off-by: Richard Genoud <richard.genoud@posteo.net> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
* | ARM: dts: stm32: Drop QSPI CS2 on DHCOMMarek Vasut2020-11-251-11/+2
| | | | | | | | | | | | | | | | | | | | The QSPI CS2 is not used on DHCOM, remove the pinmux and flash@1. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
* | ARM: dts: stm32: Fix uSD card-detect GPIO on DHCOMMarek Vasut2020-11-251-1/+1
| | | | | | | | | | | | | | | | | | | | The uSD slot card-detect GPIO is connected to PG1, fix it. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
* | ARM: dts: stm32: Add DHCOM based PicoITX boardMarek Vasut2020-11-253-0/+108
| | | | | | | | | | | | | | | | | | | | | | | | Add DT for DH PicoITX unit, which is a bare-bones carrier board for the DHCOM. The board has ethernet port, USB, CAN, LEDs and a custom board-to-board expansion connector. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
* | arm: stm32mp: correct the ALIGN macro usagePatrick Delaunay2020-11-251-2/+2
| | | | | | | | | | | | | | | | | | | | | | Correct the ALIGN macro usage in mmu_set_region_dcache_behaviour call: the address must use ALIGN_DOWN and size can use ALIGN macro. With STM32_SYSRAM_BASE=0x2FFC0000 and MMU_SECTION_SIZE=0x100000 for STM32MP15x the computed address was 30000000 instead of 2ff00000. Fixes: 43fe9d2fda24 ("stm32mp1: mmu_set_region_dcache_behaviour") Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
* | ARM: dts: stm32: Fix typo in stm32h7-u-boot.dtsiPatrice Chotard2020-11-251-1/+1
| | | | | | | | | | | | | | Fix typo "firsct" Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
* | ARM: dts: stm32: Fix timer initialization for stm32 MCU's boardPatrice Chotard2020-11-255-12/+24
| | | | | | | | | | | | | | | | | | Commit 4b2be78ab66c ("time: Fix get_ticks being non-monotonic") puts in evidence that get_ticks is called before timer initialization. Fix it by initializing timer before relocation. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
* | ARM: dts: stm32: DT sync with kernel v5.10-rc1 for MCU's boardsPatrice Chotard2020-11-2522-100/+308
| | | | | | | | | | | | | | Device tree alignment with kernel v5.10-rc1. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
* | ARM: dts: sync armv7-m.dtsi with kernel v5.10-rc1Patrice Chotard2020-11-251-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since kernel v4.8-rc1, commit 05b23ebc2bd9 ("ARM: dts: armv7-m: remove skeleton.dtsi include"), skeleton.dtsi file is no more included. This synchronization is needed to avoid to get 2 memory node in DTB file if, in DTS file, memory node is declared with the correct syntax as following: memory@90000000 { device_type = "memory"; reg = <0x90000000 0x800000>; }; Then in DTB, we will have the 2 memory nodes, which is incorrect and cause misbehavior during DT parsing by U-boot: memory { device_type = "memory"; reg = <0x00 0x00>; }; memory@90000000 { device_type = "memory"; reg = <0x90000000 0x800000>; }; Issue found when synchronizing MCU's STM32 DT from kernel v5.10-rc1. When using fdtdec_setup_mem_size_base() or fdtdec_setup_memory_banksize() API, first above memory node is found (with reg = <0x00 0x00>), so gd->ram_size, gd->ram_base, gd->bd->bi_dram[bank].start and gd->bd->bi_dram[bank].size are all set to 0 which avoid boards to boot. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
* | pinctrl: renesas: r8a77951: Add R8A774E1 PFC supportBiju Das2020-11-221-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | Renesas RZ/G2H (r8a774e1) is pin compatible with R-Car H3 (r8a77951), however it doesn't have several automotive specific peripherals. Add a r8a77951 specific pin groups/functions along with common pin groups/functions for supporting both r8a77951 and r8a774e1 SoC. PFC changes are synced from mainline linux-5.9 commit bbf5c979011a ("Linux 5.9"). Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
* | pinctrl: renesas: r8a77965: Add R8A774B1 PFC supportBiju Das2020-11-221-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | Renesas RZ/G2N (r8a774b1) is pin compatible with R-Car M3-N (r8a77965), however it doesn't have several automotive specific peripherals. Add a r8a77965 specific pin groups/functions along with common pin groups/functions for supporting both r8a77965 and r8a774b1 SoC. PFC changes are synced from mainline linux-5.9 commit bbf5c979011a ("Linux 5.9"). Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
* | arm64: zynqmp: Get rid of unused macrosMichal Simek2020-11-201-4/+2
| | | | | | | | | | | | | | There is no reason to have these macros. But record offsets of missing register in the structure for future use. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | microblaze: Enable GCC garbage collector for full U-BootMichal Simek2020-11-202-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | GCC's garbage collector works for Microblaze for quite a long time but none has enabled it. The same change has be done for example by commit fac4790491f6 ("arc: Eliminate unused code and data with GCC's garbage collector"). Before: text data bss dec hex filename 588760 33592 39192 661544 a1828 u-boot After: text data bss dec hex filename 504504 32164 38608 575276 8c72c u-boot Which saves almost 15% of memory footprint. Also group symbols/functions to proper section. Reported-by: Tom Rini <trini@konsulko.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | sunxi: dts: sync Allwinner V3s-related DTs from Linux 5.10-rc1Icenowy Zheng2020-11-176-30/+725
| | | | | | | | | | | | | | | | This commit imports device tree files that are related to Allwinner V3 series from Linux commit 3650b228f83a ("Linux 5.10-rc1"). Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
* | sunxi: allow to use AXP20[39] attached to I2C0 on V3 seriesIcenowy Zheng2020-11-171-0/+1
| | | | | | | | | | | | | | | | | | | | | | The reference design of Allwinner V3 series uses an AXP203 or AXP209 PMIC attached to the I2C0 bus of the SoC, although the first community-available V3s board, Lichee Pi Zero, omitted it. Allow to introduce support for the PMIC on boards with it. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
* | sunxi: add V3/S3 supportIcenowy Zheng2020-11-171-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | Allwinner V3/Sochip S3 uses the same die with Allwinner V3s/S3L, but V3 comes with no co-packaged DDR (DDR3 is usually used externally), and S3L comes with co-packaged DDR3. Add support for Allwinner V3/S3 chips by add SoC names to original V3s choice, and allow to select DDR3. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
* | sunxi: DT: A64: update device tree filesSamuel Holland2020-11-1725-631/+2383
| | | | | | | | | | | | | | | | | | | | | | | | | | Import updated device trees from Linux tag v5.9. This picks up new hardware (PinePhone, PineTab); and it drops the U-Boot specific DTSI files for the Pinebook and the Teres-I, since the ANX6345 bridge is now supported upstream. A couple of headers needed updates for recently-added hardware support. Acked-by: Maxime Ripard <mripard@kernel.org> Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
* | sunxi: board: Add PinePhone DT selection logicSamuel Holland2020-11-171-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | There are two different publicly-released revisions of the PinePhone hardware, versions 1.1 and 1.2; and they need different device trees. Since some GPIO pins were rerouted, we can use that to distinguish between them. Acked-by: Maxime Ripard <mripard@kernel.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
* | Merge tag 'ti-v2021.01-rc3' of ↵Tom Rini2020-11-164-1/+259
|\ \ | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-ti - Fix Nokia RX-51 boot issues - Fix CONFIG_LOGLEVEL on K3 devices - Add phyBOARD REGOR support
| * | ARM: am335x: Add phyBOARD REGOR supportParthiban Nallathambi2020-11-154-1/+259
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | phyBOARD-REGOR is based on phyCORE AM335x R2 SoM (PCL060). CPU : AM335X-GP rev 2.1 Model: Phytec AM335x phyBOARD-REGOR DRAM: 512 MiB NAND: 512 MiB MMC: OMAP SD/MMC: 0 eth0: ethernet@4a100000 Working: - Eth0 - i2C - MMC/SD - NAND - UART - USB (host) Device trees were taken from Linux mainline: commit c4d6fe731176 ("Linux 5.9.0") Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | Merge tag 'u-boot-amlogic-20201116' of ↵Tom Rini2020-11-168-97/+30
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic - Clock fix MMC driver for SM1 based platforms - sync SOC Ids from Linux 5.10-rc1 - fix potential build warning on meson_dw_hdmi and meson-g12a-usb2 phy
| * | | ARM: dts: meson-sm1: add u-boot specific MMC controller compatibleNeil Armstrong2020-11-126-4/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to enable the Amlogic SM1 MMC controller fix, we need to add a u-boot specific MMC controller compatible. This adds a new meson-sm1-u-boot.dtsi and reworks the other -u-boot.dtsi to use this for SM1 based boards. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
| * | | mmc: meson-gx: move arch header to local headerNeil Armstrong2020-11-121-92/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the asm/arch-meson/sd_emmc.h to a local meson_gx_mmc.h, remove the useless if/then and fix the meson_gx_mmc.c include. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
| * | | ARM: mach-meson: update SoC IDsNeil Armstrong2020-11-121-1/+6
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | Update From Linux commits - 240051cb833b ("soc: amlogic: meson-gx-socinfo: Add A1 and A113L IDs") - 1d7c541b8a5b ("soc: amlogic: meson-gx-socinfo: Add S905X3 ID for VIM3L") - fdfc6997bd08 ("soc: amlogic: meson-gx-socinfo: Fix S905D3 ID for VIM3L") - d16d0481e6ba ("soc: amlogic: meson-gx-socinfo: Fix S905X3 and S905D3 ID's") Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* | | rockchip: Enable BINMAN for boards enable SPL_OPTEEKever Yang2020-11-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rockchip has many 32bit SoCs and some of them are support SPL_OPTEE now, only boards with SPL_OPTEE support can fit BINMAN well, other boards will fail at initr_binman() in U-Boot proper after below patch, eg. rv1108 board. 83187546ae binman: Support multiple images in the library Fixes: 79030a4861 ("rockchip: Add Single boot image (with binman, pad_cat)") Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* | | rockchip: rockpro64: fix boot from SPI flash on spi1Hugh Cole-Baker2020-11-131-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit c4cea2bbf995 ("rockchip: Enable building a SPI ROM image on bob") added an alias spi1 referring to spi@ff1d0000, however there was already an alias spi0 referring to the same node in rockpro64's u-boot.dtsi, and having both aliases present broke booting from SPI flash for this board. Remove the spi0 alias, set the default bus for SPI flash to 1, and enable support for numbered aliases in SPL so that it uses the same bus numbering as U-Boot proper. This fixes booting from U-Boot in SPI flash on the rockpro64 board. Signed-off-by: Hugh Cole-Baker <sigmaris@gmail.com> Suggested-by: Simon Glass <sjg@chromium.org> Fixes: c4cea2bbf995 ("rockchip: Enable building a SPI ROM image on bob") Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
* | | video: rockchip: Restrict EDP, VOP, MIPI files to GPL-2.0Alper Nebi Yasak2020-11-132-2/+2
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These files have a lot of code in common with their counterparts in coreboot, especially in their earlier revisions: U-Boot | coreboot --------------------------------------|-------------------------------------------- drivers/video/rockchip/: | src/soc/rockchip/: - rk_edp.c (GPL-2.0+) | - common/edp.c (GPL-2.0-only) " | - rk3288/display.c (GPL-2.0-only) " | - rk3399/display.c (GPL-2.0-only) - rk_hdmi.h (GPL-2.0+) | (none) - rk_hdmi.c (GPL-2.0+) | - rk3288/hdmi.c (GPL-2.0-or-later) - rk3288_hdmi.c (GPL-2.0+) | - rk3288/hdmi.c (GPL-2.0-or-later) - rk3399_hdmi.c (GPL-2.0+) | (none) - rk_mipi.h (GPL-2.0+) | (none) - rk_mipi.c (GPL-2.0+) | - rk3399/mipi.c (GPL-2.0-only) - rk3288_mipi.c (GPL-2.0+) | - rk3399/mipi.c (GPL-2.0-only) - rk3399_mipi.c (GPL-2.0+) | - rk3399/mipi.c (GPL-2.0-only) - rk_lvds.c (GPL-2.0+) | (none) - rk_vop.h (GPL-2.0+) | (none) - rk_vop.c (GPL-2.0+) | - common/vop.c (GPL-2.0-only) - rk3288_vop.c (GPL-2.0+) | - common/vop.c (GPL-2.0-only) - rk3399_vop.c (GPL-2.0+) | (none) | arch/arm/include/asm/arch-rockchip/: | src/soc/rockchip/*/include/soc/*: - edp_rk3288.h (GPL-2.0+) | - common/.../edp.h (GPL-2.0-only) " | - rk3288/.../display.h (GPL-2.0-only) " | - rk3399/.../display.h (GPL-2.0-only) - vop_rk3288.h (GPL-2.0+) | - common/.../vop.h (GPL-2.0-only) Restrict the licenses to match coreboot's so that changes from coreboot can be imported to U-Boot as necessary. HDMI files are already 2.0+ there and rk_lvds.c has no counterpart, so keep them as is. Cc: Simon Glass <sjg@chromium.org> Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Cc: Eric Gao <eric.gao@rock-chips.com> Cc: Jacob Chen <jacob-chen@iotwrt.com> Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
* | x86: coral: Update smbios tables to latest definitionSimon Glass2020-11-101-6/+21
| | | | | | | | | | | | | | | | The accepted binding uses multiple nodes, one for each table type. Update coral accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: Avoid using hardcoded number of variable range MTRRs in mtrr_commit()Bin Meng2020-11-101-1/+1
|/ | | | | | | | | | | | | | | Since commit 29d2d64ed55f ("x86: Add support for more than 8 MTRRs"), the maximum number of variable range MTRRs was increased from 8 to 10. On the BayTrail platform there are only 8 variable range MTRRs. In mtrr_commit() it still uses MTRR_MAX_COUNT which caused a #GP during VESA video driver probe. It should have been updated to use dynamically probed number. This fixes the boot failure seen on Intel Minnow Max board. Fixes: 29d2d64ed55f ("x86: Add support for more than 8 MTRRs") Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* Merge tag 'dm-pull5nov20' of git://git.denx.de/u-boot-dmTom Rini2020-11-066-6/+58
|\ | | | | | | | | | | | | patman status subcommand to collect tags from Patchwork patman showing email replies from Patchwork sandbox poweroff command minor fixes in binman, tests
| * sandbox: implement resetHeinrich Schuchardt2020-11-054-0/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Up to now the sandbox would shutdown upon a cold reset request. Instead it should be reset. In our coding we use static variables like LIST_HEAD(efi_obj_list). A reset can occur at any time, e.g. via an UEFI binary calling the reset service. The only safe way to return to an initial state is to relaunch the U-Boot binary. The reset implementation uses execv() to relaunch U-Boot. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
| * sandbox: use O_CLOEXEC in os_open()Heinrich Schuchardt2020-11-051-0/+5
| | | | | | | | | | | | | | | | During a cold reset execv() is used to relaunch the U-Boot binary. We must ensure that all files are closed in this case. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
| * sandbox: enable poweroff commandHeinrich Schuchardt2020-11-051-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | The command to shut down a device is 'poweroff'. It is a deficit of the sandbox that it does not support resetting yet but shuts down upong seeing the 'reset' command. Once the sandbox properly supports reset we need the 'poweroff' command to leave the sandbox. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
| * sandbox: eth-raw: do not close the console inputHeinrich Schuchardt2020-11-052-5/+8
| | | | | | | | | | | | | | | | | | | | When the sandbox eth-raw device host_lo is removed this leads to closing the console input. Do not call close(0). Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* | Merge https://gitlab.denx.de/u-boot/custodians/u-boot-x86Tom Rini2020-11-0662-144/+783
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | - Add a new SMBIOS parser and enable it when booting from coreboot - Fix up various driver names to avoid dtoc warnings - Fully enable ACPI support on Google Chromebook Coral - Add a way to set SMBIOS properties using the devicetree - Update existing boards to use devicetree for SMBIOS using a new default sysinfo driver
| * | x86: Provide default SMBIOS manufacturer/productSimon Glass2020-11-0616-0/+62
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a file containing defaults for these, using the existing CONFIG options. This file must be included with #include since it needs to be passed through the C preprocessor. Enable the driver for all x86 boards that generate SMBIOS tables. Disable it for coral since it has its own driver. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: reword the commit message a little bit] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: galileo: Use devicetree for SMBIOS settingsSimon Glass2020-11-061-0/+28
| | | | | | | | | | | | | | | | | | | | | | | | Add settings and enable the default sysinfo driver so that these can come from the device tree. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | arm64: mvebu: Use devicetree for SMBIOS settings on uDPUSimon Glass2020-11-061-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | Add settings and enable the default sysinfo driver so that these can come from the device tree. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | odroid-c2: Use devicetree for SMBIOS settingsSimon Glass2020-11-061-0/+23
| | | | | | | | | | | | | | | | | | | | | | | | Add settings and enable the default sysinfo driver so that these can come from the device tree. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | imx: Use devicetree for SMBIOS settings on MYiR MYS-6ULXSimon Glass2020-11-061-0/+25
| | | | | | | | | | | | | | | | | | | | | | | | Add settings and enable the default sysinfo driver so that these can come from the device tree. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | rockchip: Use devicetree for SMBIOS settingsSimon Glass2020-11-064-0/+85
| | | | | | | | | | | | | | | | | | | | | | | | Add settings and enable the default sysinfo driver so that these can come from the device tree. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
generated by cgit (git 2.34.1) at 2025-10-02 11:57:08 +0000