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| * arm: dts: ti: Add Support for AM642 SoCDave Gerlach2021-05-124-0/+649
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The AM642 SoC belongs to the K3 Multicore SoC architecture platform, providing advanced system integration to enable applications such as Motor Drives, PLC, Remote IO and IoT Gateways. Some highlights of this SoC are: * Dual Cortex-A53s in a single cluster, two clusters of dual Cortex-R5F MCUs, and a single Cortex-M4F. * Two Gigabit Industrial Communication Subsystems (ICSSG). * Integrated Ethernet switch supporting up to a total of two external ports. * PCIe-GEN2x1L, USB3/USB2, 2xCAN-FD, eMMC and SD, UFS, OSPI memory controller, QSPI, I2C, eCAP/eQEP, ePWM, ADC, among other peripherals. * Centralized System Controller for Security, Power, and Resource Management (DMSC). See AM64X Technical Reference Manual (SPRUIM2, Nov 2020) for further details: https://www.ti.com/lit/pdf/spruim2 Introduce basic support for the AM642 SoC to enable SD/MMC boot. Introduce a limited set of MAIN domain peripherals under cbass_main and a set of MCU domain peripherals under cbass_mcu. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
| * board: ti: am64x: Add board support for am64x evmDave Gerlach2021-05-121-0/+1
| | | | | | | | | | | | Add board specific initialization for am64x based boards. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
| * armv8: mach-k3: am642: Add custom MMU supportKeerthy2021-05-121-0/+41
| | | | | | | | | | | | | | | | | | | | | | | | Change the memory attributes for the DDR regions used by the remote processors on AM65x so that the cores can see and execute the proper code. A separate table based on the previous K3 SoCs is introduced since the number of remote processors and their DDR usage is different between the SoC families. Signed-off-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
| * arm: mach-k3: am642: Shut down R5 core after ATF startup on A53Suman Anna2021-05-121-0/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The AM642 SoCs use the Main R5FSS0 as a boot processor, and runs the R5 SPL that performs the initialization of the System Controller processor and starting the Arm Trusted Firmware (ATF) on the Arm Cortex A53 cluster. The Core0 serves as this boot processor and is parked in WFE after all the initialization. Core1 does not directly participate in the boot flow, and is simply parked in a WFI. Power down these R5 cores (and the associated RTI timer resources that were indirectly powered up) after starting up ATF on A53 by using the appropriate SYSFW API in release_resources_for_core_shutdown(). This allows these Main R5F cores to be further controlled from the A53 to run regular applications. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
| * arm: mach-k3: am642: Use mmc start and stop callbacksDave Gerlach2021-05-121-1/+33
| | | | | | | | | | | | | | To avoid any glitches on MMC clock line, make use of pm per and post callbacks when loading sysfw. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
| * arm: mach-k3: am642: Load SYSFW binary and config from boot mediaDave Gerlach2021-05-121-0/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | Use the System Firmware (SYSFW) loader framework to load and start the SYSFW as part of the AM642 early initialization sequence. Also make use of existing logic to detect if ROM has already loaded sysfw and avoided attempting to reload and instead just prepare to use already running firmware. While at it also initialize the MAIN_UART1 pinmux as it is used by SYSFW to print diagnostic messages. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
| * arm: mach-k3: am642: Store boot info from ROMDave Gerlach2021-05-122-0/+23
| | | | | | | | | | | | | | | | | | | | For AM642, ROM supports loading system firmware directly from boot image. ROM passes information about the number of images that are loaded to bootloader at a specific address that is temporary. Add support for storing this information somewhere permanent before it gets corrupted. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
| * arm: mach-k3: am642: Unlock all applicable control MMR registersDave Gerlach2021-05-122-4/+22
| | | | | | | | | | | | | | To access various control MMR functionality the registers need to be unlocked. Do that for all control MMR regions in the MAIN domain. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
| * arm: mach-k3: am642: Add support for boot device detectionKeerthy2021-05-125-0/+198
| | | | | | | | | | | | | | | | | | | | | | | | | | AM642 allows for booting from primary or backup boot media. Both media can be chosen individually based on switch settings. ROM looks for a valid image in primary boot media, if not found then looks in backup boot media. In order to pass this boot media information to boot loader, ROM stores a value at a particular address. Add support for reading this information and determining the boot media correctly. Signed-off-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
| * arm: mach-k3: Add basic support for AM642 SoC definitionDave Gerlach2021-05-123-4/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The AM642 SoC belongs to the K3 Multicore SoC architecture platform, providing advanced system integration to enable applications such as Motor Drives, PLC, Remote IO and IoT Gateways. Some highlights of this SoC are: * Dual Cortex-A53s in a single cluster, two clusters of dual Cortex-R5F MCUs, and a single Cortex-M4F. * Two Gigabit Industrial Communication Subsystems (ICSSG). * Integrated Ethernet switch supporting up to a total of two external ports. * PCIe-GEN2x1L, USB3/USB2, 2xCAN-FD, eMMC and SD, UFS, OSPI memory controller, QSPI, I2C, eCAP/eQEP, ePWM, ADC, among other peripherals. * Centralized System Controller for Security, Power, and Resource Management (DMSC). See AM64X Technical Reference Manual (SPRUIM2, Nov 2020) for further details: https://www.ti.com/lit/pdf/spruim2 Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
| * Revert "fdt: translate address if #size-cells = <0>"Dario Binacchi2021-05-121-21/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit d64b9cdcd475eb7f07b49741ded87e24dae4a5fc. As pointed by [1] and [2], the reverted patch made every DT 'reg' property translatable. What the patch was trying to fix was fixed in a different way from previously submitted patches which instead of correcting the generic address translation function fixed the issue with appropriate platform code. [1] https://patchwork.ozlabs.org/project/uboot/patch/1614324949-61314-1-git-send-email-bmeng.cn@gmail.com/ [2] https://lore.kernel.org/linux-clk/20210402192054.7934-1-dariobin@libero.it/T/ Signed-off-by: Dario Binacchi <dariobin@libero.it> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | Merge tag 'u-boot-imx-20210502' of ↵Tom Rini2021-05-1125-218/+2539
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-imx u-boot-imx-20210502 ------------------- - mx6: fixes for Ventana - local fixes from maintainer - imx7d: Ronetix's iMX7-CM - imx8: Ronetix iMX8MQ-CM Engicam i.Core MX8M Compulab iot-gate-imx8 - Fixes i.MX8 documentation - Fixes phy usage with fec
| * | ARM:imx:imx8mq-cm: Add support for Ronetix iMX8MQ-CMIlko Iliev2021-05-024-5/+659
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Supported peripherals: Ethernet, eMMC, Serial. U-Boot SPL 2021.04-00911-g5fa1e2ffeb-dirty (Apr 23 2021 - 09:11:14 +0200) Normal Boot Trying to boot from MMC2 U-Boot 2021.04-00911-g5fa1e2ffeb-dirty (Apr 23 2021 - 09:11:14 +0200) CPU: Freescale i.MX8MQ rev2.1 at 1000 MHz Reset cause: POR Model: Ronetix iMX8M-CM SoM DRAM: 1 GiB WDT: Started with servicing (60s timeout) MMC: FSL_SDHC: 0, FSL_SDHC: 1 Loading Environment from MMC... OK In: serial Out: serial Err: serial Net: Warning: ethernet@30be0000 (eth0) using random MAC address - 42:0d:e7:78:da:53 eth0: ethernet@30be0000 Hit any key to stop autoboot: 0 u-boot=> Signed-off-by: Ilko Iliev <iliev@ronetix.at>
| * | imx: Add support for Ronetix's iMX7-CM boardIlko Iliev2021-05-024-0/+460
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Console boot log: U-Boot SPL 2021.04-00836-ga6232e065d-dirty (Apr 16 2021 - 15:16:35 +0200) Trying to boot from MMC1 U-Boot 2021.04-00836-ga6232e065d-dirty (Apr 16 2021 - 15:16:35 +0200) CPU: Freescale i.MX7D rev1.3 1000 MHz (running at 792 MHz) CPU: Commercial temperature grade (0C to 95C) at 44C Reset cause: POR Model: Ronetix iMX7-CM Board Board: iMX7-CM DRAM: 512 MiB PMIC: PFUZE3000 DEV_ID=0x30 REV_ID=0x11 MMC: FSL_SDHC: 0, FSL_SDHC: 2 Loading Environment from MMC... OK In: serial Out: serial Err: serial Net: Warning: ethernet@30be0000 (eth0) using random MAC address - fe:be:37:01:5a:3f eth0: ethernet@30be0000 Hit any key to stop autoboot: 0 Signed-off-by: Ilko Iliev <iliev@ronetix.at>
| * | imx: mkimage_fit_atf: fix file size reportingTim Harvey2021-05-021-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | instead using ls and awk to determine file size use stat instead. This fixes an invalid size reporting for user or group names that have spaces in them. This adds a dependency on the stat application which is part of the coreutils package which also includes ls. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
| * | arm: imx8m: add support for Compulab iot-gate-imx8 (imx8mm-cl-iot-gate)Ying-Chun Liu (PaulLiu)2021-05-021-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add initial support for Compulab iot-gate-imx8 board (imx8mm-cl-iot-gate). The initial support includes: - MMC - eMMC - I2C - FEC - Serial console Signed-off-by: Kirill Kapranov <kirill.kapranov@compulab.co.il> Signed-off-by: Uri Mashiach <uri.mashiach@compulab.co.il> Signed-off-by: Valentin Raevsky <valentin@compulab.co.il> Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org> Cc: Peter Robinson <pbrobinson@gmail.com>
| * | arm: dts: add imx8mm-cl-iot-gate dts fileYing-Chun Liu (PaulLiu)2021-05-023-0/+810
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add board dts for imx8mm-cl-iot-gate Signed-off-by: Kirill Kapranov <kirill.kapranov@compulab.co.il> Signed-off-by: Uri Mashiach <uri.mashiach@compulab.co.il> Signed-off-by: Valentin Raevsky <valentin@compulab.co.il> Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org> Cc: Peter Robinson <pbrobinson@gmail.com>
| * | arm: dts: imx6qdl-gw552x.dtsi: fix VBUS supplyTim Harvey2021-05-021-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove the invalid 'regulator-always-on' property to resolve: starting USB... Bus usb@2184000: Error enabling VBUS supply (ret=-13) probe failed, error -13 Bus usb@2184200: USB EHCI 1.00 Signed-off-by: Tim Harvey <tharvey@gateworks.com>
| * | board: imx8mm: Add Engicam i.Core MX8M Mini C.TOUCH 2.0Jagan Teki2021-05-024-0/+134
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Engicam C.TOUCH 2.0 is an EDIMM compliant general purpose Carrier board. Genaral features: - Ethernet 10/100 - Wifi/BT - USB Type A/OTG - Audio Out - CAN - LVDS panel connector i.Core MX8M Mini is an EDIMM SoM based on NXP i.MX8M Mini from Engicam. i.Core MX8M Mini needs to mount on top of this Carrier board for creating complete i.Core MX8M Mini C.TOUCH 2.0 board. Linux dts commit details: commit <a142252061ff> ("arm64: dts: imx8mm: Add Engicam i.Core MX8M Mini C.TOUCH 2.0") Add support for it. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * | board: imx8mm: Add Engicam i.Core MX8M Mini EDIMM2.2 Starter KitJagan Teki2021-05-025-0/+170
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Engicam EDIMM2.2 Starter Kit is an EDIMM 2.2 Form Factor Capacitive Evaluation Board. Genaral features: - LCD 7" C.Touch - microSD slot - Ethernet 1Gb - Wifi/BT - 2x LVDS Full HD interfaces - 3x USB 2.0 - 1x USB 3.0 - HDMI Out - Mini PCIe - MIPI CSI - 2x CAN - Audio Out i.Core MX8M Mini is an EDIMM SoM based on NXP i.MX8M Mini from Engicam. i.Core MX8M Mini needs to mount on top of this Evaluation board for creating complete i.Core MX8M Mini EDIMM2.2 Starter Kit. Linux dts commit details: commit <051c08eea682> ("arm64: dts: imx8mm: Add Engicam i.Core MX8M Mini EDIMM2.2 Starter Kit") Add support for it. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * | arm64: dts: imx8mm: Add Engicam i.Core MX8M Mini SoMJagan Teki2021-05-021-0/+232
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | i.Core MX8M Mini is an EDIMM SoM based on NXP i.MX8M Mini from Engicam. General features: - NXP i.MX8M Mini - Up to 2GB LDDR4 - 8/16GB eMMC - Gigabit Ethernet - USB 2.0 Host/OTG - PCIe Gen2 interface - I2S - MIPI DSI to LVDS - rest of i.MX8M Mini features i.Core MX8M Mini needs to mount on top of Engicam baseboards for creating complete platform solutions. Linux dts commit details: commit <470d6dad5ddd> ("arm64: dts: imx8mm: Add Engicam i.Core MX8M Mini SoM") Add support for it. Signed-off-by: Matteo Lisi <matteo.lisi@engicam.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * | arm64: dts: imx8mm: Add common -u-boot.dtsiJagan Teki2021-05-027-209/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | /soc@0 aips1 aips2 aips3 clk iomuxc osc_24m are common node enablements across imx8mm platform for dm-spi, dm-pre-reloc stages. Move them into common dtsi, imx8mm-u-boot.dtsi Cc: Tim Harvey <tharvey@gateworks.com> Cc: Adam Ford <aford173@gmail.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Teresa Remmet <t.remmet@phytec.de> Cc: Igor Opaniuk <igor.opaniuk@toradex.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * | board: ge: bx50v3: add phy reset GPIOSebastian Reichel2021-05-021-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add PHY's reset GPIO, so that U-Boot does a PHY hard reset. This is needed, since the PHY might become unresponsive if watchdog reboots the system while a transaction is ongoing. The reset GPIO is added to the U-Boot specific DT files, since the kernel does not setup the reserved registers correctly after resetting the PHY and thus must not reset it. Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
* | | boards: Disable CMD_SATA on platforms that no longer have a SATA driver enabledTom Rini2021-05-111-11/+0
| |/ |/| | | | | | | | | | | | | | | There are a number of platforms that depend on a SATA driver that has been converted to require AHCI but the platforms themselves are behind on other migrations that would make it trivial to enable AHCI. Disable SATA in these cases. Signed-off-by: Tom Rini <trini@konsulko.com>
* | Merge https://source.denx.de/u-boot/custodians/u-boot-riscvTom Rini2021-05-073-0/+30
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| * | riscv: cpu: fu740: clear feature disable CSRGreen Wan2021-05-051-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Clear feature disable CSR to turn on all features of hart. The detail is specified at section, 'SiFive Feature Disable CSR', in user manual https://sifive.cdn.prismic.io/sifive/aee0dd4c-d156-496e-a6c4-db0cf54bbe68_sifive_U74MC_rtl_full_20G1.03.00_manual.pdf Signed-off-by: Green Wan <green.wan@sifive.com> Reviewed-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
| * | riscv: cpu: Add callback to init each coreGreen Wan2021-05-052-0/+15
| |/ | | | | | | | | | | | | | | | | | | | | Add a callback harts_early_init() to start.S to allow different riscv hart perform setup code for each hart as early as possible. Since all the harts enter the callback, they must be able to run the same setup. Signed-off-by: Green Wan <green.wan@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | sandbox: add test of CONFIG_ENV_IMPORT_FDTRasmus Villemoes2021-05-041-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | Check that a variable defined in /config/environment is found in the run-time environment, and that clearing fdt_env_path from within that node works. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk> Acked-by: Joe Hershberger <joe.hershberger@ni.com> [trini: Conditionalize the test being linked in] Signed-off-by: Tom Rini <trini@konsulko.com>
* | test: Add gpio-sysinfo testSean Anderson2021-05-041-0/+7
|/ | | | | | | This adds a test for the gpio-sysinfo driver. Signed-off-by: Sean Anderson <sean.anderson@seco.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* Merge tag 'xilinx-for-v2021.07-rc2' of ↵Tom Rini2021-04-291-3/+0
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://source.denx.de/u-boot/custodians/u-boot-microblaze Xilinx changes for v2021.07-rc2 xilinx: - Enable saving variables based on bootmode - Cleanup usb dfu setup and wire it up with usb bootmode - Fix bootscript address logic - Remove GD references (spi, Versal) - Enable capsule update clk: - Small Kconfig fix net: - Fix gmii2rgmii bridge binding usb: - Propagate error (dfu gadget)
| * arm64: versal: Remove gd referenceMichal Simek2021-04-231-3/+0
| | | | | | | | | | | | gd is not used in this file that's why doesn't make sense to declare it. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | phy: marvell: add support for SFI1Igal Liberman2021-04-297-11/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In CP115, comphy4 can be configured into SFI port1 (in addition to SFI0). This patch adds the option described above. In addition, rename all existing SFI/XFI references: COMPHY_TYPE_SFI --> COMPHY_TYPE_SFI0 No functional change for exsiting configuration. Change-Id: If9176222e0080424ba67347fe4d320215b1ba0c0 Signed-off-by: Igal Liberman <igall@marvell.com> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
* | phy: marvell: fix pll initialization for second utmi portGrzegorz Jaszczyk2021-04-291-15/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to Design Reference Specification the PHY PLL and Calibration register from PHY0 are shared for multi-port PHY. PLL control registers inside other PHY channels are not used. This commit reworks utmi device tree nodes in a way that common PHY PLL registers are moved to main utmi node. Accordingly both child nodes utmi-unit range is reduced and register offsets in utmi_phy.h are updated to this change. This fixes issues in scenarios when only utmi port1 was in use, which resulted with lack of correct pll initialization. Change-Id: Icc520dfa719f43a09493ab31f671efbe88872097 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
* | phy: marvell: cp110: remove unused definitionsMarcin Wojtas2021-04-291-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Even if comphy types of SATA2/SATA3/SGMII3 and comphy speeds of 1.5G/3G/6.25G were referenced in the driver non configuration (dts) was using it. This patch removes unused definitions. Change-Id: I53ed6f9d3a82b9d18cb4e488bc14d3cf687f9488 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
* | phy: marvell: rename comphy related definitions to COMPHY_XXIgal Liberman2021-04-2912-122/+124
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, all comphy definitions are PHY_TYPE_XX and PHY_SPEEED_XX. Those definition might be confused with MDIO PHY definitions. This patch does the following changes: - PHY_TYPE_XX --> COMPHY_TYPE_XX - PHY_SPEED_XX --> COMPHY_SPEED_XX This improves readability, no functional change. Change-Id: I2bd1d9289ebbc5c16fa80f9870f797ea1bcaf5fa Signed-off-by: Igal Liberman <igall@marvell.com> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
* | arm: octeontx2: cn9130-crb.dtsi: Disable eth2 for nowStefan Roese2021-04-291-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | Because of the incorrectly supported SGMII_2500 mode, this patch disables eth2 for now until this issue will be fixed in mainline. Also fix an incorrect comment. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Konstantin Porotchkin <kostap@marvell.com> Cc: Stefan Chulski <stefanc@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Marek Behun <marek.behun@nic.cz>
* | arm: octeontx2: Add Octeon TX2 CN9130 CRB supportKonstantin Porotchkin2021-04-291-0/+10
| | | | | | | | | | | | | | | | This patch adds the base support for the Marvell Octeon TX2 CN9130 CRB. Not all interfaces are supported fully yet. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
* | arm: octeontx2: Add dtsi/dts files for Octeon TX2 CN9130 CRBKonstantin Porotchkin2021-04-295-1/+453
| | | | | | | | | | | | | | | | | | This patch adds the dtsi/dts files needed to support the Marvell Octeon TX2 CN9130 CRB. This is only the base port with not all interfaces supported fully. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
* | arm: armada: dts: Add support for ap807-based platformsKonstantin Porotchkin2021-04-298-379/+330
| | | | | | | | | | | | | | | | Add support for SoCs based on AP807 die. Remove unused include file for Armada-8020 SoC. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
* | arm: armada: dts: Use a single dtsi for cp110 die descriptionKonstantin Porotchkin2021-04-2913-944/+504
| | | | | | | | | | | | | | | | | | | | | | | | Use a single dtsi file for CP110 die instead of master/slave. Moving to single file will allow miltiple DTSI inclusions with re-defined CP index and name. This change will also allow support for SoCs containing more than two CP110 dies on board. Move pin control definitions from CP110 DTS to board DTS files Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
* | test: reset: Extend base reset test to catch errorNeil Armstrong2021-04-281-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With this extended test, we get the following failure : => ut dm reset_base Test: dm_test_reset_base: reset.c test/dm/reset.c:52, dm_test_reset_base(): reset_method3.id == reset_method3_1.id: Expected 0x14 (20), got 0x2 (2) Test: dm_test_reset_base: reset.c (flat tree) test/dm/reset.c:52, dm_test_reset_base(): reset_method3.id == reset_method3_1.id: Expected 0x14 (20), got 0x2 (2) Failures: 2 A fix is needed in reset_get_by_index_nodev() when introduced in [1]. [1] ea9dc35aab ("reset: Get the RESET by index without device") Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* | arm: zimage: Use correct symbol to hide messages in SPLSamuel Holland2021-04-281-7/+5
| | | | | | | | | | | | | | | | | | | | | | | | When zImage support was added to SPL, the messages were hidden to reduce code size. However, the wrong config symbol was used. Since this file is only built when CONFIG_SPL_FRAMEWORK=y, the messages were always hidden. Use the correct symbol so the messages are printed in U-Boot proper. Also use IS_ENABLED to drop the #ifdef. Fixes: 431889d6ad9a ("spl: zImage support in Falcon mode") Signed-off-by: Samuel Holland <samuel@sholland.org>
* | powerpc: introduce CONFIG_CACHE_FLUSH_WATCHDOG_THRESHOLDRasmus Villemoes2021-04-283-2/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When flush_cache() is called during boot on our ~7M kernel image, the hundreds of thousands of WATCHDOG_RESET calls end up adding significantly to boottime. Flushing a single cache line doesn't take many microseconds, so doing these calls for every cache line is complete overkill. The generic watchdog_reset() provided by wdt-uclass.c actually contains some rate-limiting logic that should in theory mitigate this, but alas, that rate-limiting must be disabled on powerpc because of its get_timer() implementation - get_timer() works just fine until interrupts are disabled, but it just so happens that the "big" flush_cache() call happens in the part of bootm where interrupts are indeed disabled. [1] [2] [3] I have checked with objdump that the generated code doesn't change when this option is left at its default value of 0: gcc is smart enough to see that the ">=" comparison is tautologically true, hence all assignments to "flushed" are eliminated as dead stores. On our board, setting the option to something like 65536 ends up reducing total boottime by about 0.8 seconds. [1] https://patchwork.ozlabs.org/project/uboot/patch/20200605111657.28773-1-rasmus.villemoes@prevas.dk/ [2] https://lists.denx.de/pipermail/u-boot/2021-April/446906.html [3] https://lists.denx.de/pipermail/u-boot/2021-April/447280.html Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
* | powerpc: lib: remove leftover CONFIG_5xxRasmus Villemoes2021-04-281-2/+0
| | | | | | | | | | | | | | | | CONFIG_5xx hasn't existed since commit 502589777416 (powerpc, 5xx: remove support for 5xx). Remove this last mention of it. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
* | allow opting out of WATCHDOG_RESET() from timer interruptRasmus Villemoes2021-04-282-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Having WATCHDOG_RESET() called automatically from the timer interrupt runs counter to the idea of a watchdog device - if the board runs into an infinite loops with interrupts still enabled, the watchdog will never fire. When using CONFIG_(SPL_)WDT, the watchdog_reset function is a lot more complicated than just poking a few SOC-specific registers - it involves accessing all kinds of global data, and if the interrupt happens at the wrong time (say, in the middle of an WATCHDOG_RESET() call from ordinary code), that can end up corrupting said global data. Allow the board to opt out of calling WATCHDOG_RESET() from the timer interrupt handler by setting CONFIG_SYS_WATCHDOG_FREQ to 0 - as that setting is currently nonsensical (it would be compile-time divide-by-zero), it cannot affect any existing boards. Add documentation for both the existing and extended meaning of CONFIG_SYS_WATCHDOG_FREQ. Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
* | sunxi: DT: A64: Update devicetree files from Linux 5.12Andre Przywara2021-04-2817-76/+215
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Import updated devicetree files from the Linux v5.12 release. Besides some node and audio port renames this changes the PHY modes to either rgmii-id or rgmii-txid. From the board files the Pinephone sees a lot of updates. This also adds the long missing USB PHY property for controller 0, which allows the U-Boot PHY driver to eventually use port 0 in host mode (pending another U-Boot patch). Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net>
* | sunxi: DT: R40: Update device tree files from Linux 5.12Ivan Uvarov2021-04-283-44/+366
| | | | | | | | | | | | | | | | | | | | | | Update R40 .dts{,i} and dt-binding headers to current version from kernel. Files taken from Linux 5.12-rc1 release (commit fe07bfda2fb9cdef8a4d4008a409bb02f35f1bd8) Signed-off-by: Ivan Uvarov <i.uvarov@cognitivepilot.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* | mips: octeon: ebb7304: Add support for some I2C devicesAaron Williams2021-04-281-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for the following I2C devices connected to I2C bus 0 on the Octeon EBB7304: - Dallas DS1337 RTC - TLV EEPROM Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de> Cc: Chandrakala Chavva <cchavva@marvell.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* | mips: octeon: dts/dtsi: Change UART DT node to use clocks propertyAaron Williams2021-04-282-4/+2
| | | | | | | | | | | | | | | | | | | | | | We already have a clock driver for MIPS Octeon. This patch changes the Octeon DT nodes to supply the clock property via the clock driver instead of using an hard-coded value, which is not correct in all cases. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de> Cc: Chandrakala Chavva <cchavva@marvell.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* | mips: octeon: Add Octeon III NIC23 board supportStefan Roese2021-04-283-0/+170
| | | | | | | | | | | | | | This patch adds the basic support for the PCIe target board equipped with the Octeon III CN2350 SoC. Signed-off-by: Stefan Roese <sr@denx.de>
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