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* | | | | am33xx: Re-enable SW levelling for DDR2Tom Rini2015-06-156-40/+91
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The recent changes for hw leveling on am33xx were not intended for DDR2 boards, only DDR3. Update emif_sdram_type to take a sdram_config value to check against. This lets us pass in the value we would use to configure, when we have not yet configured the board yet. In other cases update the call to be as functional as before and check an already programmed value in. Tested-by: Yan Liu <yan-liu@ti.com> Signed-off-by: Tom Rini <trini@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | | | | ARM: BeagleBoard-x15: Enable i2c5 clocksLokesh Vutla2015-06-153-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On AM57xx evm I2C5 is used to detect the LCD board by reading the EEPROM present on the bus. Enable i2c5 clocks to help that. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | | | ARM: DRA7: CPSW: Remove IO delay hackLokesh Vutla2015-06-121-25/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now all manual mode configurations are done as part of IO delay recalibration sequence, remove the hack done for CPSW. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | | | | ARM: DRA7: Add support for manual mode configurationLokesh Vutla2015-06-124-2/+140
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In addition to the regular mux configuration, certain pins of DRA7 require to have "manual mode" also programmed, when predefined delay characteristics cannot be used for the interface. struct iodelay_cfg_entry is introduced for populating manual mode IO timings. For configuring manual mode, along with the normal pad configuration do the following steps: - Select MODESELECT field of each assocaited PAD. CTRL_CORE_PAD_XXX[8]:MODESELECT = 1(Enable MANUAL_MODE macro along with mux) - Populate A_DELAY, G_DELAY values that are specified in DATA MANUAL. And pass the offset of the CFG_XXX register in iodelay_cfg_entry. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
* | | | | ARM: DRA7: Add support for IO delay configurationLokesh Vutla2015-06-126-0/+231
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On DRA7, in addition to the regular muxing of pins, an additional hardware module called IODelay which is also expected to be configured. This "IODelay" module has it's own register space that is independent of the control module. It is advocated strongly in TI's official documentation considering the existing design of the DRA7 family of processors during mux or IODelay recalibration, there is a potential for a significant glitch which may cause functional impairment to certain hardware. It is hence recommended to do muxing as part of IOdelay recalibration. IODELAY recalibration sequence: - Complete AVS voltage change on VDD_CORE_L - Unlock IODLAY config registers. - Perform IO delay calibration with predefined values. - Isolate all the IOs - Update the delay mechanism for each IO with new calibrated values. - Configure PAD configuration registers - De-isolate all the IOs. - Relock IODELAY config registers. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
* | | | | ARM: DRA7: Add support for virtual mode configurationLokesh Vutla2015-06-121-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In addition to the regular mux configuration, certain pins of DRA7 require to have "virtual mode" also programmed. This allows for predefined delay characteristics to be used by the SoC to meet timing characterstics needed for the interface. Provide easy to use macro to do the same. For configuring virtual mode, along with normal pad configuration add the following two steps: - Select MODESELECT field of each assocaited PAD. CTRL_CORE_PAD_XXX[8]:MODESELECT = 1 - DELAYMODE filed should be configured with value given in DATA Manual. CTRL_CORE_PAD_XXX[7:4]:DELAYMODE =[0-15] (as given in DATA manual). Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
* | | | | ARM: DRA7: Add pinctrl register definitionsLokesh Vutla2015-06-121-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adopting the pinctrl register definitions from Linux kernel to be consistent. Old definitions will be removed once all the pinctrl data is adapted to new definitions. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
* | | | | ARM: DRA7: Make do_set_mux32() genericLokesh Vutla2015-06-122-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | do_set_mux32() is redefined in dra7xx and beagle_x15 boards. IO delay recalibration sequence also needs this. Making it generic to avoid duplication. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
* | | | | ARM: DRA7xx: EMIF: Fix DLL_CALIB_CTRL registerLokesh Vutla2015-06-121-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When DLL_CALIB_INTERVAL is set, an extra delay is added which is not required and it consumes EMIF bandwidth. So making the DLL_CALIB_CTRL[8:0]DLL_CALIB_INTERVAL bits to 0. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | | | | ARM: DRA7: Update DDR IO registersLokesh Vutla2015-06-121-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update DDR IO register values. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | | | ARM: DRA7: Update DDR IO configurationLokesh Vutla2015-06-121-4/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DDRIO_2 and LPDDR2CH1_1 registers are not present for DRA7. So not configuring these registers for DRA7xx Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | | | ARM: DRA7: Add is_dra72x cpu check definitionLokesh Vutla2015-06-121-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A generic is_dra72x cpu check is useful for grouping all the revisions under that. This is used in the subsequent patches. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | | | ARM: DRA72-evm: Enable HW levelingLokesh Vutla2015-06-121-6/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Updating EMIF registers to enable HW leveling on DRA72-evm. Also updating the timing registers. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | | | ARM: DRA7-evm: Enable HW levelingLokesh Vutla2015-06-121-6/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Updating EMIF registers to enable HW leveling on DRA7-evm. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | | | ARM: DRA7: DDR3: Add support for HW levelingLokesh Vutla2015-06-123-24/+207
|/ / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | DRA7 EMIF supports Full leveling for DDR3. Adding support for the Full leveling sequence. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | | Merge git://git.denx.de/u-boot-dmTom Rini2015-06-118-20/+54
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| * | | | dm: usb: tegra: Drop legacy USB codeSimon Glass2015-06-101-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Drop the code that doesn't use driver model for USB. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | | dts: Disable device tree for SPL on all boardsSimon Glass2015-06-104-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We plan to enable device tree in SPL by default. Before doing this, explicitly disable it for all boards. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | | fdt: arm: Drop device tree paddingSimon Glass2015-06-101-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The 4KB padding doesn't seem necessary since we don't normally adjust the control device tree file within U-Boot. Also drop the memory table space. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | | sandbox: Add an implementation for cleanup_before_linux_select()Simon Glass2015-06-101-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Support this function so we can use Chrome OS verified boot with sandbox. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | | arm: Allow cleanup_before_linux() without disabling cachesSimon Glass2015-06-101-18/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This function is used before jumping to U-Boot, but in that case we don't always want to disable caches. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
| * | | | dm: tegra: usb: Move USB to driver modelSimon Glass2015-06-102-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Somehow this change was dropped in the various merges. I noticed when I came to turn off the non-driver-model support for Tegra. We need to make this change (and deal with any problems) before going further. Change-Id: Ib9389a0d41008014eb0df0df98c27be65bc79ce6 Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Marek Vasut <marex@denx.de>
* | | | | Merge branch 'master' of http://git.denx.de/u-boot-samsungTom Rini2015-06-101-78/+2
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| * | | | odroid: dts: cleanup of MAX77686 regulatorsPrzemyslaw Marczak2015-06-101-78/+2
| | |/ / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit cleanup MAX77686 regulator node by: - remove the sub-nodes of unconnected regulators - remove the "regulator-compatible" properties of all regulators This prevents printing init errors for the regulators, with duplicated name strings. Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | | | Merge branch 'master' of http://git.denx.de/u-boot-sunxiTom Rini2015-06-101-0/+1
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| * | | | sunxi: Request macpwr gpio before using itHans de Goede2015-06-101-0/+1
| |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes ethernet no longer working on boards which use a gpio to enable the phy. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | | | Merge branch 'master' of git://git.denx.de/u-boot-avr32Tom Rini2015-06-103-280/+0
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| * | | | avr32: delete ancient board.cAndreas Bießmann2015-06-102-259/+0
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * | | | avr32: delete non generic board's atstk100{3, 4, 6}Andreas Bießmann2015-06-101-9/+0
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * | | | avr32: delete non generic board mimc200Andreas Bießmann2015-06-101-4/+0
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * | | | avr32: delete non generic board hammerheadAndreas Bießmann2015-06-101-4/+0
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * | | | avr32: delete non generic board favr-32-ezkitAndreas Bießmann2015-06-101-4/+0
| |/ / / | | | | | | | | | | | | Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | | | tegra: Replace 'Norrin' with 'Nyan-big' and fix typoSimon Glass2015-06-091-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With the rename the MAINTAINER file was not updated. Fix it and the 'Chrombook' typo in Kconfig. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | | | tegra: Allow board-specific initSimon Glass2015-06-092-2/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a hook to allows boards to add their own init to board_init(). Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | | | tegra: Add missing tegra124 peripheralsSimon Glass2015-06-092-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | There are some missing entries in the tables. Add them. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | | | tegra: Introduce SRAM repair on tegra124Simon Glass2015-06-092-1/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is required in order to avoid instability when running from caches after the kernel starts. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | | | tegra: clock: Adjust PLL access to avoid a warningSimon Glass2015-06-091-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A harmless but confusing warning is displayed when looking up the DisplayPort PLL. Correct this. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | | | tegra: clock: Support enabling external clocksSimon Glass2015-06-092-0/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a simple function to enable external clocks. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | | | dm: tegra: cros_ec: Enable Chrome OS EC on Nyan-bigSimon Glass2015-06-091-0/+3
|/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable the EC and keyboard, using the SPI bus. The EC driver requires a particular format and a deactivation delay. Also U-Boot does not support interrupts. For now, adjust the device tree to comply. At some point we should tidy this up to support interrupts and make tegra and exynos use the same setup. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | | Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2015-06-0815-6/+304
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| * | imx: drop warning: unused variable 'max_freq'Stefano Babic2015-06-081-1/+2
| | | | | | | | | | | | | | | | | | | | | max_freq in print_cpuinfo is used only with imx6. Signed-off-by: Stefano Babic <sbabic@denx.de>
| * | colibri_vf: Enable board specific USB initialisation for USB pen gpioSanchayan Maity2015-06-081-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add IOMUX for the pad used as USB pen. This needs to be driven low for the Iris and Viola boards where it is pulled up high by default. This is required for the USB host functionality to work on these boards. Use the board specific weak initialisation function, to drive the pin low which would be called on "usb start". Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
| * | vf610: dts: Add device tree supportBhuvanchandra DV2015-06-085-0/+160
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add device tree files for Freescale Vybrid platform and Toradex Colibri VF50, VF61 modules. Device tree files are taken from upstream Kernel. Removed the stuff which are not used/supported yet in U-Boot. Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
| * | arm: vf610: Add iomux support for DSPIBhuvanchandra DV2015-06-081-0/+9
| | | | | | | | | | | | | | | | | | Add iomux definitions for DSPI second instance. Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
| * | arm: vf610: Add clock support for DSPIBhuvanchandra DV2015-06-083-0/+12
| | | | | | | | | | | | Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
| * | colibri_vf: Add pinmux entries for GPIOsBhuvanchandra DV2015-06-081-0/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | Inorder to use the pins as GPIO, apart from setting the alt-function, pinmuxing need to be done, this patch adds pinmux entries of few GPIOs. Acked-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
| * | dm: gpio: vf610: Add GPIO driver supportBhuvanchandra DV2015-06-084-0/+66
| | | | | | | | | | | | | | | | | | Add GPIO driver support to Freescale VF610 Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
| * | mxs: Do not disable bo detection when DC-DC is already enabledStefan Wahren2015-06-011-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | In case the DC-DC is already enabled mxs_enable_4p2_dcdc_input() returns without reenabling brown out detection. So fix this issue by moving the return before brown out deactivation. Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com> Reviewed-by: Marek Vasut <marex@denx.de>
| * | Revert "imx: drop warning: unused variable 'max_freq'"Stefano Babic2015-05-281-2/+1
| | | | | | | | | | | | | | | | | | This reverts commit a0117a5e416629932becf079589f5e1859eab90a. Signed-off-by: Stefano Babic <sbabic@denx.de>
| * | imx: drop warning: unused variable 'max_freq'Stefano Babic2015-05-271-1/+2
| | | | | | | | | | | | | | | | | | | | | max_freq in print_cpuinfo is used only with imx6. Signed-off-by: Stefano Babic <sbabic@denx.de>
generated by cgit (git 2.34.1) at 2024-10-02 02:42:18 +0000