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* sunxi: add DTSI file for V3sIcenowy Zheng2017-04-211-0/+284
| | | | | | | | | | | As we have now V3s support in board code, the V3s DTSI file should also be added. Add also some CCU include headers to satisfy the DTSI file. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* sunxi: add basic V3s supportIcenowy Zheng2017-04-213-0/+7
| | | | | | | | | | | | | | | Basic U-Boot support is now present for V3s. Some memory addresses are changed specially for V3s, as the original address map cannot fit into a so small DRAM. As the DRAM controller code needs a big refactor, the SPL support is disabled in this version. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* sunxi: Add clock support for DE2/HDMI/TCON on newer SoCsJernej Skrabec2017-04-202-1/+93
| | | | | | | | This is needed for HDMI, which will be added later. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* sunxi: video: Convert lcdc to use struct display_timingJernej Skrabec2017-04-201-3/+3
| | | | | | | | | | | | | | Video driver for older Allwinner SoCs uses cfb console framework which in turn uses struct ctfb_res_modes to hold timing informations. However, DM video framework uses different structure - struct display_timing. It makes more sense to convert lcdc to use new timing structure because all new drivers should use DM video framework and older drivers might be rewritten to use new framework too. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* sunxi: video: Split out TCON codeJernej Skrabec2017-04-202-103/+128
| | | | | | | | | TCON unit has similar layout and functionality also on newer SoCs. This commit splits out TCON code for easier reuse later. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* sunxi: Add support for Bananapi M2 UltraChen-Yu Tsai2017-04-203-0/+254
| | | | | | | | | | | The Bananapi M2 Ultra is the first publicly available development board featuring the R40 SoC. This patch add barebone dtsi/dts files for the R40 and Bananapi M2 Ultra, as well as a defconfig for it. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* sunxi: Add PSCI support for R40Chen-Yu Tsai2017-04-201-3/+32
| | | | | | | | | | | | | | | | The R40's CPU controls are a combination of sun6i and sun7i. All controls are in the CPUCFG block, and it seems the R40 does not have a PRCM block. The core reset, power gating and clamp controls are grouped like sun6i. Last, the R40 does not have a secure SRAM block. This patch adds a PSCI implementation for CPU bring-up and hotplug for the R40. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* sunxi: Fix CPUCFG address for R40Chen-Yu Tsai2017-04-201-2/+4
| | | | | | | | The R40 has the CPUCFG block at the same address as the A20. Fix it. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* sunxi: Use H3/A64 DRAM initialization code for R40Chen-Yu Tsai2017-04-206-18/+133
| | | | | | | | | | The R40 seems to have a variant of the memory controller found in the H3 and A64 SoCs. Adapt the code for use on the R40. The changes are based on released DRAM code and comparing register dumps from boot0. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* sunxi: Set PLL lock enable bits for R40Chen-Yu Tsai2017-04-202-0/+7
| | | | | | | | | | | | According to the BSP released by Banana Pi, the R40 (sun8iw11p1) has an extra "PLL lock control" register in the CCU, which controls whether the individual PLL lock status bits in each PLL's control register work or not. This patch enables it for all the PLLs. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* sunxi: Fix watchdog reset function for R40Chen-Yu Tsai2017-04-203-7/+8
| | | | | | | | The watchdog found on the R40 SoC is the older variant found on the A20. Add the proper "#if defines" to make it work. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* sunxi: Enable AXP221s in I2C mode with the R40 SoCChen-Yu Tsai2017-04-201-0/+7
| | | | | | | | | | The R40 SoC uses the AXP221s in I2C mode to supply power. Some regulator's common usages have changed, and also the recommended voltage for existing usages have changed. Update the defaults to match. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* sunxi: Add initial support for R40Chen-Yu Tsai2017-04-202-3/+9
| | | | | | | | | | | | | | The R40 is the successor to the A20. It is a hybrid of the A20, A33 and the H3. The R40's PIO controller is compatible with the A20, Reuse the A20 UART and I2C muxing code by adding the R40's macro. The display pipeline is the newer DE 2.0 variant. Block enabling video on R40 for now. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* Merge git://git.denx.de/u-boot-rockchipTom Rini2017-04-1610-11/+140
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| * rockchip: rk3399: spl: add UART0 support for SPLPhilipp Tomsich2017-04-153-8/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The RK3399-Q7 ("Puma") SoM exposes UART0 as the Qseven UART (i.e. the serial line available via standardised pins on the edge connector and available on a RS232 connector). To support boards (such as the RK3399-Q7) that require UART0 as a debug console, we match CONFIG_DEBUG_UART_BASE and add the appropriate iomux setup to the rk3399 SPL code. As we are already touching this code, we also move the board-specific UART setup (i.e. iomux setup) into board_debug_uart_init(). This will be called from the debug UART init when CONFIG_DEBUG_UART_BOARD_INIT is set. As the RK3399 needs to use its board_debug_uart_init() function, we have Kconfig enable it by default for RK3399 builds. With everything set up to define CONFIG_BAUDRATE via defconfig and with to have the SPL debug UART either on UART0 or UART2, the configs for the RK3399 EVB are then update (the change for the RK3399-Q7 is left for later to not cause issues on applying the change). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * rockchip: pmic: Enable RK808 for rk3399 evberic.gao@rock-chips.com2017-04-151-0/+39
| | | | | | | | | | | | | | | | For using mipi display, we need to enable lcd3v3 which supplied by rk808,so enable rk808 first. Signed-off-by: Eric Gao <eric.gao@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * rockchip: i2c: Enable i2c for rk3399eric.gao@rock-chips.com2017-04-151-0/+16
| | | | | | | | | | | | | | | | | | To enable mipi display, we need to enable pmic rk808 first for lcd3v3 power,which use i2c0 to communicate with soc. So enable i2c0. Signed-off-by: Eric Gao <eric.gao@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * rockchip: rk3399: Add missing sentinel in sysconeric.gao@rock-chips.com2017-04-151-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | when enable PMIC rk808,the system will halt at very early stage,log is shown as bellow. INFO: plat_rockchip_pmu_init(1211): pd status 3e INFO: BL31: Initializing runtime services INFO: BL31: Preparing for EL3 exit to normal world INFO: Entry point address = 0x200000 INFO: SPSR = 0x3c9 time 44561b, 0 (<<----Just stop here) It's caused by the absence of "{ }" in syscon_rk3399.c ,which will lead to memory overflow like below.According to Sysmap file ,we can find the function buck_get_value of rk808 is just follow the compatible struct,the pointer "of_match" point to "buck_get_value",but it is not a struct and don't have member of compatible, In this case, system crash. So,on the face, it looks like that rk808 is guilty.but he is really innocent. while (of_match->compatible) { <<---------- if (!strcmp(of_match->compatible, compat)) { *of_idp = of_match; return 0; } of_match++; } Signed-off-by: Eric Gao <eric.gao@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Tested-by: Kever Yang <kever.yang@rock-chips.com>
| * rockchip: ARM64: split RK3399-Q7 board off the RK3399-EVB boardKlaus Goger2017-04-151-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The RK3399-Q7 SoM is a Qseven-compatible (70mm x 70mm, MXM-230 connector) system-on-module from Theobroma Systems, featuring the Rockchip RK3399. It provides the following feature set: * up to 4GB DDR3 * on-module SPI-NOR flash * on-module eMMC (with 8-bit interace) * SD card (on a baseboad) via edge connector * Gigabit Ethernet w/ on-module Micrel KSZ9031 GbE PHY * HDMI/eDP/MIPI displays * 2x MIPI-CSI * USB - 1x USB 3.0 dual-role (direct connection) - 2x USB 3.0 host + 1x USB 2.0 (on-module USB 3.0 hub) * on-module STM32 Cortex-M0 companion controller, implementing: - low-power RTC functionality (ISL1208 emulation) - fan controller (AMC6821 emulation) - USB<->CAN bridge controller Note that we use a multi-payload FIT image for booting and have Cortex-M0 payload in a separate subimage: we thus rely on the FIT image loader to put it into the SRAM region that ATF expects it in. Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Fixed build warning on puma-rk3399: Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
| * rockchip: dts: rk3399-puma: make the DTS dual-licensedPhilipp Tomsich2017-04-151-1/+1
| | | | | | | | | | | | | | | | The RK3399-Q7 (Puma) DTS should (of course) be dual-licensed. This updates the licensing info in the rk3399-puma.dts. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * rockchip: rk3188: enable remap functionHeiko Stübner2017-04-152-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Most Rockchip socs have the ability to either map the bootrom or a sram area to the starting address of the cpu by flipping a bit in the GRF. Newer socs leave this untouched and mapped to the bootrom but the legacy loaders on rk3188 and before enabled the remap functionality and the current smp implementation in the Linux kernel also requires it to be enabled, to bring up secondary cpus. So to keep smp working in the kernel, mimic the behaviour of the legacy bootloaders and enable the remap functionality. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Simon Glass <sjg@chromium.org>
| * rockchip: cosmetic: Move rock board to its correct positionHeiko Stübner2017-04-151-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Somehow 43b5c78d8d91 ("rockchip: cosmetic: Sort RK3288 boards") moved the rock board in between some rk3288 board, probably as a result of rebasing. So move it back to its original position above all rk3288 boards. Fixes: 43b5c78d8d91 ("rockchip: cosmetic: Sort RK3288 boards") Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Simon Glass <sjg@chromium.org>
| * rockchip: dts: rk3399-puma: disable 'fifo-mode' in sdmmcPhilipp Tomsich2017-04-151-1/+0
| | | | | | | | | | Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Simon Glass <sjg@chromium.org>
| * rockchip: spl: rk3399: disable DDR security regions for SPLPhilipp Tomsich2017-04-151-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The RK3399 hangs during DMA of the Designware MMC controller, when performing DMA-based transactions in SPL due to the DDR security settings left behind by the BootROM (i.e. accesses to the first MB of DRAM are restricted... however, the DMA is likely to target this first MB, as it transfers from/to the stack). System security is not affected, as the final security configuration is performed by the ATF, which is executed after the SPL stage. With this fix in place, we can now drop 'fifo-mode' in the DTS for the RK3399-Q7 (Puma). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* | Merge git://git.denx.de/u-boot-dmTom Rini2017-04-164-23/+28
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| * | sandbox: Add some test LEDsSimon Glass2017-04-141-0/+14
| | | | | | | | | | | | | | | | | | | | | Add some LEDs to the standard sandbox device tree. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Ziping Chen <techping.chan@gmail.com>
| * | arm: omap: sata: compile out board-level sata code when CONFIG_DM_SCSI is ↵Jean-Jacques Hiblot2017-04-141-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | defined When CONFIG_DM_SCSI is defined, the SATA initialization will be implemented in the scsi-uclass driver. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * | arm: omap: sata: move enable sata clocks to enable_basic_clocks()Mugunthan V N2017-04-142-23/+12
| |/ | | | | | | | | | | | | | | | | | | All the clocks which has to be enabled has to be done in enable_basic_clocks(), so moving enable sata clock to common clocks enable function. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-videoTom Rini2017-04-145-1/+51
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| * board: toradex: colibri_vf: Add DCU support for Colibri VybridStefan Agner2017-04-144-0/+50
| | | | | | | | | | | | | | | | | | | | | | The Vybrid SoC family has the same display controller unit (DCU) like the LS1021A SoC. This patch adds platform data, pinmux defines and clock control to enable the driver for Toradex Colibri Vybrid module. Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com> Reviewed-by: Stefano Babic <sbabic@denx.de>
| * Convert CONFIG_FSL_DCU_FB to KconfigSanchayan Maity2017-04-141-1/+1
| | | | | | | | | | | | | | | | | | Rename CONFIG_FSL_DCU_FB to CONFIG_VIDEO_FSL_DCU_FB and convert it to Kconfig. Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com> Reviewed-by: Stefan Agner <stefan.agner@toradex.com> Reviewed-by: Alison Wang <alison.wang@nxp.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini2017-04-144-20/+26
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| * | arm: socfpga: Convert Altera DDR SDRAM driver to use KconfigLey Foon Tan2017-04-141-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Convert Altera DDR SDRAM driver to use Kconfig method. Enable ALTERA_SDRAM by default if it is on Gen5 target. Arria 10 will have different driver. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
| * | ARM: socfpga: Disable OC on MCVEVKMarek Vasut2017-04-141-0/+1
| | | | | | | | | | | | | | | | | | | | | Disable the OC test on MCVEVK as the old PHY version does not provide this information. This fixes the USB OTG operation. Signed-off-by: Marek Vasut <marex@denx.de>
| * | ARM: socfpga: Rename MCVEVKMarek Vasut2017-04-142-6/+6
| | | | | | | | | | | | | | | | | | The board is now manufactured by Aries Embedded GmbH , rename it. Signed-off-by: Marek Vasut <marex@denx.de>
| * | ARM: socfpga: boot0 hook: remove macro from boot0 header fileChee, Tien Fong2017-04-141-14/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit ce62e57fc571 ("ARM: boot0 hook: remove macro, include whole header file") miss out cleaning macro in this header file, and this has broken implementation of a boot header capability in socfpga SPL. Remove the macro in this file, and recovering it back to proper functioning. Fixes: ce62e57fc571 ("ARM: boot0 hook: remove macro, include whole header file") Signed-off-by: Chee, Tien Fong <tien.fong.chee@intel.com>
| * | ARM: socfpga: cyclone5-socdk: Enable ports A & CGeorges Savoundararadj2017-04-141-0/+8
| |/ | | | | | | | | | | | | | | | | | | | | With the port C enabled, we can read the GPI input state of: * the DIP switches (USER_DIPSW_HPS[3:0]/HPS_GPI[7:4]) * the push buttons (USER_PB_HPS[3:0]/HPS_GPI[11:8]) Signed-off-by: Georges Savoundararadj <savoundg@gmail.com> Signed-off by: Sid-Ali Teir <git.syedelec@gmail.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Marek Vasut <marex@denx.de>
* | Merge branch 'master' of git://git.denx.de/u-boot-mmcTom Rini2017-04-144-275/+1126
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| * | mmc: meson: add MMC driver for Meson GX (S905)Carlo Caione2017-04-141-0/+89
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This driver implements MMC support on Meson GX (S905) based systems. It's based on Carlo Caione's work, changes: - BLK support added - general refactoring Signed-off-by: Carlo Caione <carlo@caione.org> Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Tested-by: Vagrant Cascadian <vagrant@debian.org>
| * | arm: dts: update Meson GXBB / Odroid-C2 DT with recent Linux versionHeiner Kallweit2017-04-143-275/+1037
| |/ | | | | | | | | | | | | | | | | | | | | As a prerequisite for adding a Meson GX MMC driver update the Meson GXBB / Odroid-C2 device tree in Uboot with the latest version from Linux. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Carlo Caione <carlo@endlessm.com> Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
* | Merge git://git.denx.de/u-boot-dmTom Rini2017-04-1340-223/+6543
|\ \ | | | | | | | | | | | | Here with some DM changes as well as the long-standing AT91 DM/DT conversion patches which I have picked up via dm.
| * | ARM: at91: lds: use "_image_binary_end" for DT locationWenyou Yang2017-04-131-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | The MMC SPL locates the BSS section to a different memory region from text, then use "_image_binary_end" variable to point to the correct device tree location. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
| * | ARM: spl: atmel: move mem_init() advance in SPL init.Wenyou Yang2017-04-131-1/+2
| | | | | | | | | | | | | | | | | | | | | Because the MMC SPL puts the bbs section in the ddr memory, move calling mem_init() before calling spl_init(). Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
| * | ARM: spl: atmel: bring in serial device before initWenyou Yang2017-04-131-0/+8
| | | | | | | | | | | | | | | | | | | | | Before setting up the serial communications, bring in the serial device from the device tree file. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
| * | ARM: at91: spl: specify MMC and NAND boot deviceWenyou Yang2017-04-131-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When OF_CONTROL is enabled, MMC boot device should not be detected automatically, it should be MMC1 fixedly only the status "enabled" is available. Add NAND Flash boot device as well. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
| * | ARM: dts: at91: add dts file for sama5d4ekWenyou Yang2017-04-132-0/+344
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the device tree file for sama5d4ek board. The dts file is copied from Linux-4.4, do the following changes. - add the "u-boot,dm-pre-reloc" property to determine which nodes which are needed by SPL and by the board_init_f stage. - fix the compilation warning. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
| * | ARM: dts: at91: add dts files for sama5d4 XplainedWenyou Yang2017-04-133-0/+2224
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the device tree files for sama5d4 Xplained board. The dts files are copied from Linux-4.4, do the following changes. - add reg property for pinctrl node. - move the gpio nodes(pioA, pioB, pioC ...) from the pinctrl child's nodes to its slibling nodes. - add the "u-boot,dm-pre-reloc" property to determine which nodes which are needed by SPL and by the board_init_f stage. - fix the compilation warnings. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
| * | ARM: at91: dt: add dts file for sama5d3 XplainedWenyou Yang2017-04-132-0/+351
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the device tree file for sama5d3 Xplained board. The dts files are copied from the Linux-4.9, do changes as below. - add the "u-boot,dm-pre-reloc" property to determine which nodes which are needed by SPL and by the board_init_f stage. - fix the compile warning. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
| * | ARM: at91: dt: add dts files for sama5d3xek boardWenyou Yang2017-04-1325-0/+3382
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the device tree files for sama5d3xek board. The dts files are copied from Linux-4.9, do the changes as below. - add reg property for the pinctrl node. - move the gpio nodes (pioA, pioB, pioC ...) as the pinctrl's slibling nodes. - add the "u-boot,dm-pre-reloc" property to determine which nodes which are needed by SPL and by the board_init_f stage. - fix the compile warning. - add spi0 node aliases. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
| * | pinctrl: at91: add pinctrl driverWenyou Yang2017-04-131-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | AT91 PIO controller is a combined gpio-controller, pin-mux and pin-config module. The peripheral's pins are assigned through per-pin based muxing logic. Each SoC will have to describe the its limitation and pin configuration via device tree. This will allow to do not need to touch the C code when adding new SoC if the IP version is supported. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
generated by cgit (git 2.34.1) at 2024-11-19 08:38:00 +0000