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* sandbox: add missing compatible property in device treeHeinrich Schuchardt2019-12-102-0/+2
| | | | | | | | | In the device tree UEFI unit test the compatible property of the device is read. Provide the missing property. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
* Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-riscvTom Rini2019-12-0918-44/+594
|\ | | | | | | | | | | | | | | - Increase stack size to avoid a stack overflow during distro boot. - Add hifive-unleashed-a00.dts for SIFIVE FU540. - Add OF_SEPARATE support for SIFIVE FU540. - Add SPL support for Andes AX25 AE350. - Improve U-Boot SPL / OpenSBI smp boot flow for RISC-V.
| * riscv: add option to wait for ack from secondary harts in smp functionsLukas Auer2019-12-105-12/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a wait option to smp_call_function() to wait for the secondary harts to acknowledge the call-function request. The request is considered to be acknowledged once each secondary hart has cleared the corresponding IPI. As part of the call-function request, the secondary harts invalidate the instruction cache after clearing the IPI. This adds a delay between acknowledgment (clear IPI) and fulfillment (call function) of the request. We want to use the acknowledgment to be able to judge when the request has been completed. Remove the delay by clearing the IPI after cache invalidation and just before calling the function from the request. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com> Tested-by: Rick Chen <rick@andestech.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
| * riscv: add functions for reading the IPI statusLukas Auer2019-12-104-0/+43
| | | | | | | | | | | | | | | | | | | | Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
| * riscv: dts: Add #address-cells and #size-cells in nor nodeRick Chen2019-12-102-2/+6
| | | | | | | | | | | | | | | | | | Those are required for cfi-flash driver to get correct address information. Also modify size description correctly. Signed-off-by: Rick Chen <rick@andestech.com> Cc: KC Lin <kclin@andestech.com> Cc: Alan Kao <alankao@andestech.com>
| * riscv: dts: Support four cores SMPRick Chen2019-12-102-6/+108
| | | | | | | | | | | | | | | | | | Add CPU2 and CPU3 information in cpus node to support four cores SMP booting. Signed-off-by: Rick Chen <rick@andestech.com> Cc: KC Lin <kclin@andestech.com> Cc: Alan Kao <alankao@andestech.com>
| * riscv: Fix clear bss loop in the start-up codeRick Chen2019-12-103-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | For RV64, it will use sd instruction to clear t0 register, and the increament will be 8 bytes. So if the difference between__bss_strat and __bss_end was not 8 bytes aligned, the clear bss loop will overflow and acks like system hang. Signed-off-by: Rick Chen <rick@andestech.com> Cc: KC Lin <kclin@andestech.com> Cc: Alan Kao <alankao@andestech.com>
| * riscv: ax25: cache: Add SPL_RISCV_MMODE for SPLRick Chen2019-12-101-14/+46
| | | | | | | | | | | | | | | | | | | | The mcache_ctl csr only can be manipulated in M mode. Add SPL_RISCV_MMODE for U-Boot SPL to control cache operation. Signed-off-by: Rick Chen <rick@andestech.com> Cc: KC Lin <kclin@andestech.com> Cc: Alan Kao <alankao@andestech.com>
| * riscv: andes_plic: Fix some wrong configurationsRick Chen2019-12-101-4/+7
| | | | | | | | | | | | | | | | | | | | | | | | Fix two wrong settings of andes plic driver as below: 1. Fix wrong pending register base definition. 2. Declaring the en variable in enable_ipi() as unsigned int instead of int can help to fix wrong plic enabling setting in RV64. Signed-off-by: Rick Chen <rick@andestech.com> Cc: KC Lin <kclin@andestech.com> Cc: Alan Kao <alankao@andestech.com>
| * riscv: ax25: add SPL supportRick Chen2019-12-101-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The U-Boot SPL will boot in M mode and load the FIT image which include OpenSBI and U-Boot proper images. After loading progress, it will jump to OpenSBI first and then U-Boot proper which will run in S mode. Also remove V5L2_CACHE due to U-Boot SPL code size consideration. Without this concern, it can be enable manually for performance. Signed-off-by: Rick Chen <rick@andestech.com> Cc: KC Lin <kclin@andestech.com> Cc: Alan Kao <alankao@andestech.com>
| * riscv: dts: Add hifive-unleashed-a00 dts from LinuxJagan Teki2019-12-103-0/+348
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Sync the hifive-unleashed-a00 dts from Linux with below commit details: commit <2993c9b04e616df0848b655d7202a707a70fc876> ("riscv: dts: HiFive Unleashed: add default chosen/stdout-path") Idea is to periodically sync the dts from Linux instead of tweaking internal changes one after another, so better not add any intermediate changes in between. This would help to maintain the dts files easy and meaningful since we are reusing device tree files from Linux. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
| * riscv: increase stack size to avoid a stack overflow during distro bootLukas Auer2019-12-101-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes a problem, where booting Linux using distro boot will sometimes lead to an invalid instruction exception on the main hart. The secondary harts are not affected and boot Linux successfully. The root cause of this problem is a stack overflow on the main hart. With distro boot, the current default stack size of 8KiB on RISC-V is not sufficient and will cause a stack overflow. The stacks are allocated sequentially. In the case of a stack overflow the stack of the main hart can reach into that of another hart and be corrupted. The stack overflow previously did not cause any problems, because only stack frames, which are not used anymore since the hart enters Linux, were corrupted. Starting with GCC 9, the stack usage has decreased. Now, only the most recent stack frame overflows into the stack of a secondary hart and is corrupted. The illegal instruction exception is caused by the secondary hart overwriting the return address in the stack frame of the main hart with an address that does not include valid code. Increase the default stack size of each hart to 16KiB to avoid this problem. Reported-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Tested-by: David Abdurachmanov <david.abdurachmanov@sifive.com> Tested-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Rick Chen <rick@andestech.com>
* | ARM: DRA7: Fixup DSP OPP_HIGH clock rate on DRA76P/DRA77P SoCsSuman Anna2019-12-091-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The commit 1b42ab3eda8a ("ARM: DRA7: Fixup DSPEVE, IVA and GPU clock frequencies based on OPP") added the core logic to update the kernel device-tree blob to adjust the DSP, IVA and GPU DPLL clocks based on a one-time OPP choice selected in U-Boot for most of the DRA7xx/AM57xx family of SoCs. The DSPs on DRA76xP/DRA77xP SoCs (DRA76x ACD package SoCs) though provide a higher performance and can run at a higher clock frequency of 850 MHz at OPP_HIGH instead of 750 MHz. Fix up the logic to use the correct clock rates on these SoCs. Note that this higher clock rate is not applicable to other Jacinto 6 Plus SoCs (DRA75xP/DRA74xP SoCs or AM574x SoCs) that follow the ABZ package. Signed-off-by: Suman Anna <s-anna@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
* | Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-netTom Rini2019-12-095-3/+258
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| * arm: dts: k3-j721e-common-proc-board: Add DMA and CPSW related DT nodesVignesh Raghavendra2019-12-091-0/+238
| | | | | | | | | | | | | | | | | | Add DT nodes related to DMA and CPSW to -u-boot.dtsi to get networking up on J721e EVM. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
| * arm: dts: armada-cp110-*dtsi: add xmdio nodesNevo Hed2019-12-092-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Based on upstream-linux See https://github.com/torvalds/linux/commit/f66b2aff. However made the XSMI register window 0x16 (22) bytes per my reading of the functional spec. Similar commits in Marvels own repo bump it to 0x200 (512) bytes but I did not see the reasoning for that. https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/4d932b4. Also added device-name attributes to prevent ambiguity in the `mdio` command. Signed-off-by: Nevo Hed <nhed+github@starry.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * arm: dts: k3-am654-base-board-u-boot: change cpsw2g interface mode to rgmii-rxidGrygorii Strashko2019-12-091-2/+1
| | | | | | | | | | | | | | | | | | | | The AM654 SoC doesn't allow to disabling RGMII TX internal delay in CPSW2G MAC. Hence, change CPSW2G interface mode to "rgmii-rxid" - RGMII with internal RX delay provided by the PHY, the MAC will add an TX delay in this case. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * net: Always build the string_to_enetaddr() helperJoe Hershberger2019-12-091-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Part of the env cleanup moved this out of the environment code and into the net code. However, this helper is sometimes needed even when the net stack isn't included. Move the helper to lib/net_utils.c like it's similarly-purposed string_to_ip(). Also rename the moved function to similar naming. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Reported-by: Ondrej Jirman <megous@megous.com>
* | arm: -march=armv5t for ARM11Heinrich Schuchardt2019-12-091-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In GCC 9 support for the Armv5 and Armv5E architectures (which have no known implementations) has been removed, cf. https://gcc.gnu.org/gcc-9/changes.html Commit 16540d07fd62 ("arm: fix -march for ARM11") changed the value of the compiler flag from -march=armv5 and -march=armv5t into -march=armv6 for ARM11. The values prior to this patch were: arch-$(CONFIG_CPU_ARM1136) =-march=armv5 arch-$(CONFIG_CPU_ARM1176) =-march=armv5t The change lead to a regression with the Raspberry Pi Zero W not booting anymore. Use -march=armv5t both for ARM1136 and ARM1176. Fixes: 16540d07fd62 ("arm: fix -march for ARM11") Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Tested-by: Joris Offouga <offougajoris@gmail.com>
* | Merge tag 'u-boot-imx-20191209' of ↵Tom Rini2019-12-0913-1033/+1117
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-imx Fixes for 2020.01 ----------------- - imx8qxp_mek: increase buffer sizes and args number - Fixes for imx7ulp - imx8mm: Fix the first root clock in imx8mm_ahb_sels[] - colibri_imx7: reserve DDR memory for Cortex-M4 - vining2000: fixes and convert to ethernet DM - imx8m: fix rom version check to unbreak some B0 chips - tbs2910: Disable VxWorks image booting support
| * imx8m: fix rom version check to unbreak some B0 chipsPatrick Wildt2019-12-091-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Recently the version check was improved to be able to determine that we're running on SoC revision 2.1. A check for B0 was tightened so that it now must equal 0x20 instead of being bigger than 0x20. On some B0 chips the value returned is 0x1020 instead of 0x20. This means even though it's B0, the check will fail and code relying on the correct chip revision will make wrong decisions. There is no documentation of those bits, but it seems that NXP always uses a byte to encode the revision. Thus remove the upper bits to fix the regression. Signed-off-by: Patrick Wildt <patrick@blueri.se>
| * ARM: imx: vining2000: Repair PCIe supportMarek Vasut2019-12-061-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Ever since the conversion to DM PCI, the board was missing the PCIe DT nodes, hence the PCI did not really work. Fill in the DT nodes and add missing PCIe device reset. Moreover, bring the PCIe power domain up before booting Linux. This is mandatory to keep old broken vendor kernels working, as they do not do so and depend on the bootloader to bring the power domain up. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Silvio Fricke <silvio.fricke@softing.com> Cc: Stefano Babic <sbabic@denx.de>
| * ARM: imx: vining2000: Convert to SPL frameworkMarek Vasut2019-12-061-0/+1
| | | | | | | | | | | | | | | | | | | | | | In preparation for use of DDR DRAM fine-tuning upon boot, convert the board to SPL framework instead of using DCD tables to bring up DRAM and pinmux. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Silvio Fricke <silvio.fricke@softing.com> Cc: Stefano Babic <sbabic@denx.de>
| * ARM: mx6: pmu: Expose PMU LDO configuration interfaceMarek Vasut2019-12-062-7/+9
| | | | | | | | | | | | | | | | | | | | | | Make the PMU LDO configuration interface available to board code, so that board code can reconfigure the internal LDOs of the SoC. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Eric Nelson <eric@nelint.com> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Eric Nelson <eric@nelint.com>
| * board: colibri_imx7: reserve DDR memory for Cortex-M4Igor Opaniuk2019-12-061-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | i.MX 7's Cortex-M4 core can run from DDR and uses DDR memory for the rpmsg communication. Both use cases need a fixed location of memory reserved. For the rpmsg use case the reserved area needs to be in sync with the kernel's hardcoded vring descriptor location. Use the linux,usable-memory property to carve out 1MB of memory in case the M4 core is running. Also make sure that the i.MX 7 specific rpmsg driver does not get loaded in case we do not carve out memory. Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com> Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
| * mx6: Allow configuring the NoC registers on i.MX6QPFabio Estevam2019-12-061-0/+35
| | | | | | | | | | | | | | | | | | | | | | | | The NoC registers on i.MX6QP needs to be configured, otherwise some usecases in the kernel behave incorrectly, such as rotation and resize. Currently the NoC registers are not configured in the kernel, so configure them in U-Boot like it is done in the NXP U-Boot tree. Signed-off-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Stefano Babic <sbabic@denx.de>
| * mx7ulp: Sync the device tree related filesFabio Estevam2019-12-063-964/+969
| | | | | | | | | | | | | | | | | | | | | | | | Sync the mx7ulp device tree related files with the one from NXP U-Boot vendor tree (imx_v2019.04_4.19.35_1.0.0). The mainline support for i.MX7ULP is very premature at this stage. We should probably re-sync with mainline Linux dts when it gets in better shape, but for now sync with the U-Boot vendor code. Signed-off-by: Fabio Estevam <festevam@gmail.com>
| * mx7ulp: scg: Remove unnused scg_a7_apll_init()Fabio Estevam2019-12-062-62/+0
| | | | | | | | | | | | scg_a7_apll_init() is not called anywhere, so remove such dead code Signed-off-by: Fabio Estevam <festevam@gmail.com>
| * mx7ulp: Remove the _RUN notation from the PMC1 LDOVL definitionsFabio Estevam2019-12-061-10/+10
| | | | | | | | | | | | | | | | The LDOVL definitions is common to all the modes, not only RUN mode, so in order to avoid confusion, remove the _RUN notation from the PMC1 LDOVL definitions. Signed-off-by: Fabio Estevam <festevam@gmail.com>
| * mx7ulp: Introduce the CONFIG_LDO_ENABLED_MODE optionFabio Estevam2019-12-062-0/+63
| | | | | | | | | | | | | | | | Introduce the CONFIG_LDO_ENABLED_MODE option so that i.MX7ULP boards designed to operate with LDO enabled mode can work with 0.95V at LDO output in RUN mode as per the datasheet. Signed-off-by: Fabio Estevam <festevam@gmail.com>
| * mx7ulp: Print the LDO mode statusFabio Estevam2019-12-061-0/+20
| | | | | | | | | | | | | | | | | | As per the i.MX7ULP datasheet, it can boot in LDO enabled mode or LDO bypass mode. Print the LDO mode status in the U-Boot log for convenience. Signed-off-by: Fabio Estevam <festevam@gmail.com>
* | x86: simplify ljmp to 32-bit codeMasahiro Yamada2019-12-081-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | You can directly specify the label as the operand for ljmp. This commit saves 4-byte code. Signed-off-by: Masahiro Yamada <masahiroy@kernel.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: fixed the gas warning] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: use data32 directive instead of macro for operand-size prefixMasahiro Yamada2019-12-081-5/+3
| | | | | | | | | | | | | | | | | | | | | | This file defines 'a32' and 'o32' macros to avoid magic numbers of operand/address-size prefixing. GAS supports 'data32' and 'addr32' for that purpose. Signed-off-by: Masahiro Yamada <masahiroy@kernel.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* | Merge tag 'u-boot-rockchip-20191206' of ↵Tom Rini2019-12-0611-21/+203
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip - rockchip pwm driver update to support all the SoCs - RK3308 GMAC and pinctrl support - More UART interface support on PX30 and pmugrf reg fix - Fixup on misc for eth_addr/serial# - Other updates on variant SoCs
| * | arm: rockchip: rk3308: Initialize the iomux configurationDavid Wu2019-12-061-0/+37
| | | | | | | | | | | | | | | | | | | | | | | | When we want to use plus pinctrl feature, we need to enable them at spl. Signed-off-by: David Wu <david.wu@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * | pwm: rk_pwm: Make PWM driver to support all Rockchip SocsDavid Wu2019-12-061-6/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This PWM driver can be used to support pwm functions for on all Rockchip Socs. The previous chips than RK3288 did not support polarity, and register layout was different from the RK3288 PWM. The RK3288 keep the current functions. RK3328 and the chips after it, which can support hardware lock, configure duty, period and polarity at next same period, to prevent the intermediate temporary state. Signed-off-by: David Wu <david.wu@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * | dts: rk3308: Enable ethernet function supported for Firefly ROC_RK3308_CCDavid Wu2019-12-061-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | The Firefly ROC_RK3308_CC use ref_clock of input mode, and rmii pins of m1 group. Signed-off-by: David Wu <david.wu@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * | arm: dts: Add mac node for rk3308 at dtsi levelDavid Wu2019-12-061-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | The rk3308 only support RMII mode, and if it is output clock mode, better to use ref_clk pin with drive strength 12ma. Signed-off-by: David Wu <david.wu@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * | rockchip: misc: protect serial# from getting overwrittenHeiko Stuebner2019-12-051-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | serial# is one of the vendor properties and thus protected from being overwritten if already set. If env_set is called anyway this result in some nasty warnings, so check for presence before trying that. In the same direction check for the presence of cpuid# and compare it to the actual hardware and emit a warning if they don't match. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * | rockchip: misc: don't fail if eth_addr already setHeiko Stuebner2019-12-051-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | rockchip_setup_macaddr() runs from an initcall, so returning an error code will make that initcall fail thus breaking the boot process. And if an ethernet address is already set this is definitly not a cause for that, so just return success in that case. Fixes: 04825384999f ("rockchip: rk3399: derive ethaddr from cpuid"); Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * | rockchip: px30: Add support for using UART3 as debug UARTPaul Kocialkowski2019-12-052-0/+96
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some generic PX30 SoMs found in the wild use UART3 as their debug output instead of UART2 (used for MMC) and UART5. Make it possible to use UART3 as early debug output, with the associated clock and pinmux configuration. Two sets of output pins are supported (M0/M1). Future users should also note that the pinmux default in the dts is to use the M1 pins while the Kconfig option takes M0 as a default. Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
| * | rockchip: px30: Rename CONFIG_DEBUG_UART2_CHANNEL to CONFIG_DEBUG_UART_CHANNELPaul Kocialkowski2019-12-052-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | UART3 also has two sets of pins that can be selected. Rename the config option to a common name, to allow it to be used for both UART2 and UART3. Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * | rockchip: px30: Fixup PMUGRF registers layout orderPaul Kocialkowski2019-12-051-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | According to the PX30 TRM, the iomux registers come first, before the pull and strength control registers. Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
| * | rockchip: px5: enable spl-fifo-mode for emmc for px5-evbAndy Yan2019-12-051-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We need load some parts of ATF to sram, but rockchip dwmmc controllers can't do dma to non-ddr addresses space, so set the mmc controller into fifo mode in spl. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * | rockchip: rk3308: enable spl-fifo-mode for emmcAndy Yan2019-12-051-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We need load some parts of ATF to sram, but rockchip dwmmc controllers can't do dma to non-ddr addresses space, so set the mmc controller into fifo mode in spl. And show my best respect to Heiko's work for this solution. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* | | Fix typo in macros, "FIRMEWARE" -> "FIRMWARE"Thomas Hebb2019-12-052-5/+5
|/ / | | | | | | Signed-off-by: Thomas Hebb <tommyhebb@gmail.com>
* | cmd: nand/sf: isolate legacy codeMiquel Raynal2019-12-041-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The 'sf' command is not supposed to rely on the MTD stack, but both 'sf' and 'nand' commands use helpers located in mtd_uboot.c. Despite their location, these functions do not depend at all on the MTD stack. This file (drivers/mtd/mtd_uboot.c) is only compiled if CONFIG_MTD is selected, which is inconsistent with the current situation. Solve this by moving these three functions (which are only used by the above two commands) out of mtd_uboot.c and put them in a C file only compiled with cmd/sf.c and cmd/nand.c. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> [trini: Don't export get_part function now] Signed-off-by: Tom Rini <trini@konsulko.com>
* | mtd: rename CONFIG_NAND -> CONFIG_MTD_RAW_NANDMiquel Raynal2019-12-033-6/+6
| | | | | | | | | | | | | | | | | | Add more clarity by changing the Kconfig entry name. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> [trini: Re-run migration, update a few more cases] Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Boris Brezillon <boris.brezillon@bootlin.com>
* | ARM: MediaTek: add basic support for MT8518 boardsmingming lee2019-12-033-1/+107
| | | | | | | | | | | | | | | | | | | | | | | | | | This adds a general board file based on MT8518 SoCs from MediaTek. Apart from the generic parts (cpu) we add some low level init codes and initialize the early clocks. This commit is adding the basic boot support for the MT8518 eMMC board. Signed-off-by: mingming lee <mingming.lee@mediatek.com> [trini: Migrate env location to defconfig, set ENV_IS_IN_MMC] Signeed-off-by: Tom Rini <trini@konsulko.com>
* | pinctrl: add driver for MT8518mingming lee2019-12-031-1/+8
| | | | | | | | | | | | Add Pinctrl driver for MediaTek MT8518 SoC. Signed-off-by: mingming lee <mingming.lee@mediatek.com>
generated by cgit (git 2.34.1) at 2025-04-20 13:20:07 +0000