summaryrefslogtreecommitdiffstats
path: root/arch
Commit message (Collapse)AuthorAgeFilesLines
* mvebu: consolidate SPL boot device config symbolsBaruch Siach2018-08-062-8/+4
| | | | | | | | | | | Use MVEBU_SPL_BOOT_DEVICE_* to select between SPI and MMC, instead of board specific symbols. This commit enables the boot device selection menu to all mvebu platforms, but it is only effective on Turris Omnia and gdsys Controlcenter DC platforms. A following commit will enable boot selection for other platforms. Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
* mvebu: a38x: drop duplicate platform id symbolsBaruch Siach2018-08-061-0/+3
| | | | | | | Use generic mvebu Kconfig symbols like all other mvebu boards. Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
* Merge branch 'master' of git://git.denx.de/u-boot-sunxiTom Rini2018-08-0422-18/+2221
|\
| * board: sun50i: h6: Add OrangePi One Plus initial supportJagan Teki2018-07-312-0/+151
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | OrangePi One Plus is Allwinner H6 based open-source SBC, which support: - Allwinner H6 Quad-core 64-bit ARM Cortex-A53 - GPU Mali-T720 - 1GB LPDDR3 RAM - AXP805 PMIC - 1Gbps GMAC via RTL8211 - USB 2.0 Host, OTG - HDMI port - 5V/2A DC power supply Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
| * sunxi: add support for Pine H64 boardIcenowy Zheng2018-07-312-0/+187
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pine H64 is a SBC with Allwinner H6 SoC produced by Pine64. It features 1GiB/2GiB/4GiB(3GiB usable) DRAM, two USB 2.0 ports, one USB 3.0 port and a mPCIE slot. Add support for it. The device tree is from Linux next-20180720. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
| * sunxi: add support for Allwinner H6 SoCIcenowy Zheng2018-07-313-1/+306
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Allwinner H6 is a new SoC from Allwinner features USB3 and PCIe interfaces. This patch adds support for it. The corresponding DTSI file, from Linux next-20180720, is also introduced. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
| * sunxi: add DRAM support to H6Icenowy Zheng2018-07-315-0/+1061
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Allwinner H6 SoC comes with a set of new DRAM controller+PHY combo. Both the controller and the PHY seem to be originate from DesignWare, and are similar to the ones in ZynqMP SoCs. This commit introduces an initial DRAM driver for H6, which contains only LPDDR3 support. The currently known SBCs with H6 all come with LPDDR3 memory, including Pine H64 and several Orange Pi's. The BSP DRAM initialization code is closed source and violates GPL. Code in this commit is written by experimenting, referring the code/document of other users of the IPs (mainly the ZynqMP, as it's the only found PHY reference) and disassebling the BSP blob. Thanks for Jernej Skrabec for review and fix some issues in this driver (including the most critical one which made it to work), and rewrite some code from register dump! Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
| * sunxi: add MMC support for H6Icenowy Zheng2018-07-311-1/+1
| | | | | | | | | | | | | | | | | | | | | | The Allwinner H6 SoC has 3 MMC controllers like the ones in A64, with the MMC2 come with the capability to do crypto by EMCE. Add MMC support for H6. EMCE support is not added yet. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
| * sunxi: add UART0 setup for H6Icenowy Zheng2018-07-312-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | The UART0 on H6 is available at PH bank (and PF bank, but the PF one is muxed with SD card). Add pinmux configuration. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
| * sunxi: use sun6i-style watchdog for H6Icenowy Zheng2018-07-312-2/+2
| | | | | | | | | | | | | | | | | | | | | | The H6 SoC has a sun6i-style watchdog in its timer part. Enable the usage of it. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
| * sunxi: add clock code for H6Icenowy Zheng2018-07-314-0/+417
| | | | | | | | | | | | | | | | | | | | | | The new Allwinner H6 SoC has a brand new CCU layout. Add clock code for it. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
| * sunxi: change RMR64's RVBAR address for H6Icenowy Zheng2018-07-312-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | Allwinner H6 has a different RVBAR address with A64/H5. Add conditional RVBAR configuration into the code which does RMR switch. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
| * sunxi: add basic memory map definitions of H6 SoCIcenowy Zheng2018-07-312-0/+75
| | | | | | | | | | | | | | | | | | | | | | | | | | The Allwinner H6 SoC come with a totally new memory map. Add basical definition of the new memory map into a header file, and let the cpu.h header include it in the situation of H6. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
| * sunxi: change SUNXI_HIGH_SRAM option to SUNXI_SRAM_ADDRESSIcenowy Zheng2018-07-312-14/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The new Allwinner H6 SoC has its SRAM A1 at neither 0x0 nor 0x10000, but it's at 0x20000. Thus the SUNXI_HIGH_SRAM option needs to be refactored to support this new configuration. Change it to SUNXI_SRAM_ADDRESS, which holds the real address of SRAM A1 in the memory map. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
* | ARM: dts: stm32: remove cd-inverted for stm32429i-evalPatrice Chotard2018-08-031-2/+1
| | | | | | | | | | | | | | | | As cd-inverted property is no more used by arm_pl180_mmci driver, remove it. Update cd-gpios active level accordingly. Reported-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
* | armv8: make SPL exception vectors optionalAndre Przywara2018-08-033-4/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Even though the exception vector table is a fundamental part of the ARM architecture, U-Boot mostly does not make real use of it, except when crash dumping. But having it in takes up quite some space, partly due to the architectural alignment requirement of 2KB. Since we don't take special care of that, the compiler adds a more or less random amount of padding space, which increases the image size quite a bit, especially for the SPL. On a typical Allwinner build this is around 1.5KB of padding, plus 1KB for the vector table (mostly padding space again), then some extra code to do the actual handling. This amounts to almost 10% of the maximum image size, which is quite a lot for a pure debugging feature. Add a Kconfig symbol to allow the exception vector table to be left out of the build for the SPL. For now this is "default y" for everyone, but specific defconfigs, platforms or .config files can opt out here at will, to mitigate the code size pressure we see for some SPLs. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* | armv8: Reduce exception handling codeAndre Przywara2018-08-031-50/+82
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The arm64 exception handling code is quite big, mostly due to architectural alignment requirements. Each exception entry spans 32 instructions, which sounds generous, but is too small to fit all of the save/branch/restore code in there. So at the moment we use only four instructions, branching into shared save and restore routines. To not leave the space for those remaining 28 instructions wasted, let's split the save and restore routines and stuff them into the gaps. This saves about 250 bytes of code, which is helpful for those tight SPLs. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* | clk: add clk_valid()Fabrice Gasnier2018-08-031-0/+8
| | | | | | | | | | | | | | | | | | Add clk_valid() to check for optional clocks are valid. Call clk_valid() in test/dm/clk.c and add relevant test routine to sandbox clk tests. Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | Merge git://git.denx.de/u-boot-dmTom Rini2018-08-033-16/+16
|\ \
| * | binman: Rename 'position' to 'offset'Simon Glass2018-08-013-16/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | After some thought, I believe there is an unfortunate naming flaw in binman. Entries have a position and size, but now that we support hierarchical sections it is unclear whether a position should be an absolute position within the image, or a relative position within its parent section. At present 'position' actually means the relative position. This indicates a need for an 'image position' for code that wants to find the location of an entry without having to do calculations back through parents to discover this image position. A better name for the current 'position' or 'pos' is 'offset'. It is not always an absolute position, but it is always an offset from its parent offset. It is unfortunate to rename this concept now, 18 months after binman was introduced. However I believe it is the right thing to do. The impact is mostly limited to binman itself and a few changes to in-tree users to binman: tegra sunxi x86 The change makes old binman definitions (e.g. downstream or out-of-tree) incompatible if they use the 'pos = <...>' property. Later work will adjust binman to generate an error when it is used. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | ARM: tegra: align carveout sizeStephen Warren2018-08-011-1/+1
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | Align the size of the carveout region to 2M. This ensures that the size can be accurately represented by an LPAE page table that uses sections. This solves a bug (hang at boot time soon after printing the DRAM size) that only shows up when the following two commits are merged together: d32e86bde8a3 ARM: HYP/non-sec: enable ARMV7_LPAE if HYP mode is supported 6e584e633d10 ARM: tegra: avoid using secure carveout RAM Cc: Mark Kettenis <kettenis@openbsd.org> Cc: Alexander Graf <agraf@suse.de> Acked-by: Tom Warren <twarren@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | Merge tag 'arc-updates-for-2018.09-rc2' of git://git.denx.de/u-boot-arcTom Rini2018-08-014-1/+52
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | That's a set of prety minor changes and fixes for ARC. Among them: * Improvement in CREG GPIO driver used on ARC dev boards that allow us to re-use the driver for SPI's chip select * Enable SPI-flsh on AXS10x boards which allows to update U-Boot binary that gets loaded by boot-ROM * Fix accommodating always utilized unaligned access by GCC for ARC starting from 8.1.0
| * | ARC: Enable unaligned access in hardware if compiler uses itAlexey Brodkin2018-07-312-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Even if ARC core might handle unaligned access to data this hardware feature by default is disabled. But GCC starting from 8.1.0 unconditionally uses it for ARC HS cores. Which leads to quite strange and fatal run-time failures like the one below if HW is not configured properly: | hsdk# sf probe | Misaligned data access exception @ 0xbff794d4 | ECR: 0x000d0000 | RET: 0xbff794d4 | BLINK: 0xbff79644 | STAT32: 0x00000800 | GP: 0x1003e000 r25: 0xbfd58f08 | BTA: 0xbff794a4 SP: 0xbfd58cd4 FP: 0xbfd58ef0 | LPS: 0xbff90240 LPE: 0xbff90244 LPC: 0x00000000 | r00: 0x00000000 r01: 0x00000003 r02: 0x000026bf | r03: 0x00000000 r04: 0x00000100 r05: 0x00000000 | r06: 0x00000001 r07: 0x00000000 r08: 0x1dcd6500 | r09: 0x00000000 r10: 0x00200000 r11: 0x00000000 | r12: 0x1b3d4440 r13: 0xbff9eca4 r14: 0xbfd59d68 | r15: 0xbfd60cd0 r16: 0x00000000 r17: 0x00000000 | r18: 0xbff9ed14 r19: 0xbfd59c78 r20: 0xbfd58d40 | r21: 0xbfd58d44 r22: 0x00000000 r23: 0x00000000 | r24: 0xbfd59ba8 | Resetting CPU ... Now we're checking for __ARC_UNALIGNED__ define emitted by the compiler if it's going to use unaligned access and then we force-enable it in hardware too. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
| * | AXS10x: add spi flash supportEugeniy Paltsev2018-07-311-0/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | AXS10x boards have n25q512 spi flash IC, so add corresponding nodes to device tree and enaple corresponding options in defconfig. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
| * | GPIO: CREG: improve flexibility of hsdk-creg-gpio driverEugeniy Paltsev2018-07-311-1/+6
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CREG GPIO is a driver for weird soc-specific output ports, which are controlled by some fields in memory mapped register. Example: 31 9 7 5 0 < bit number | | | | | [ not used | gpio-1 | gpio-0 | <-shift-> ] < 32 bit register ^ ^ | | write 0x2 == set output to "1" (activate) write 0x3 == set output to "0" (deactivate) As of tooday we only support fixed (hardcoded) bit per gpio line, activate / deactivatei and shift values. Fix that by read them from device tree to be able to use this driver for other boards. Remove "hsdk" prefix from compatible string as this driver can be used with different boards like HSDK, AXS101, AXS103, etc. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
* / dm: Fix CMD_DM enablingMichal Simek2018-07-311-1/+1
|/ | | | | | | | | | The patch "dm: Change CMD_DM enabling" (sha1: 08a00cba06a7e608ae65e3d7ea225cf8c639429d) was incorrectly updated and PICO_IMX7D is missing imply CMD_DM and WARP7 has it twice. This patch is fixing it. Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* Merge tag 'signed-efi-next' of git://github.com/agraf/u-bootTom Rini2018-07-3017-121/+145
|\ | | | | | | | | | | | | | | | | | | | | Patch queue for efi - 2018-07-25 Highlights this time: - Many small fixes to improve spec compatibility (found by SCT) - Almost enough to run with sandbox target - GetTime() improvements - Enable EFI_LOADER and HYP entry on ARMv7 with NONSEC=y
| * x86: Add efi_loader bits to x86_64 linker scriptAlexander Graf2018-07-251-1/+33
| | | | | | | | | | | | The x86_64 linker script was missing efi runtime information. Add it. Signed-off-by: Alexander Graf <agraf@suse.de>
| * efi_loader: Rename sections to allow for implicit dataAlexander Graf2018-07-2512-72/+109
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some times gcc may generate data that is then used within code that may be part of an efi runtime section. That data could be jump tables, constants or strings. In order to make sure we catch these, we need to ensure that gcc emits them into a section that we can relocate together with all the other efi runtime bits. This only works if the -ffunction-sections and -fdata-sections flags are passed and the efi runtime functions are in a section that starts with ".text". Up to now we had all efi runtime bits in sections that did not interfere with the normal section naming scheme, but this forces us to do so. Hence we need to move the efi_loader text/data/rodata sections before the global *(.text*) catch-all section. With this patch in place, we should hopefully have an easier time to extend the efi runtime functionality in the future. Signed-off-by: Alexander Graf <agraf@suse.de> [agraf: Fix x86_64 breakage]
| * elf: Move x86 reloc defines to common elf.hAlexander Graf2018-07-253-47/+0
| | | | | | | | | | | | | | | | | | | | We need to know about x86 relocation definitions even in cases where we don't officially build against the x86 target, such as with sandbox. So let's move the x86 definitions into the common elf header, where all other architectures already have them. Signed-off-by: Alexander Graf <agraf@suse.de>
| * ARM: HYP/non-sec: enable ARMV7_LPAE if HYP mode is supportedMark Kettenis2018-07-251-1/+1
| | | | | | | | | | | | | | | | | | | | ARMV7_LPAE is required in order to enable the MMU in HYP mode. And we really want to enable the MMU in HYP mode such that we can enable the the caches. Otherwise U-Boot code (such as the EFI implementation) that runs in HYP mode will run at a snils pace. Signed-off-by: Mark Kettenis <kettenis@openbsd.org> Signed-off-by: Alexander Graf <agraf@suse.de>
| * ARM: HYP/non-sec: migrate stackMark Kettenis2018-07-251-0/+2
| | | | | | | | | | | | | | | | | | | | | | The current code that switches into HYP mode doesn't bother to set up a stack for HYP mode. This doesn't work for EFI applications as they expect a usable stack. Fix this by migrating the stack pointer from SP_svc to SP_hyp while in Monitor mode. This restores the stack pointer when we drop into HYP mode. Signed-off-by: Mark Kettenis <kettenis@openbsd.org> Signed-off-by: Alexander Graf <agraf@suse.de>
* | Kconfig: Sort bool, default, select and imply optionsMichal Simek2018-07-3019-97/+98
| | | | | | | | | | | | | | | | | | Another round of sorting Kconfig entries aplhabetically. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Alexey Brodkin <abrodkin@synopsys.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
* | dm: Change CMD_DM enablingMichal Simek2018-07-3014-0/+113
| | | | | | | | | | | | | | | | | | | | | | CMD_DM is used for debug purpose and it shouldn't be enabled by default via Kconfig. Unfortunately this is in the tree for quite a long time that's why solution is to use imply DM for all targets which are enabling DM. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
* | Kconfig: Sort bool, default, select and imply optionsMichal Simek2018-07-3013-327/+327
| | | | | | | | | | | | | | | | Fix Kconfig bool, default, select and imply options to be alphabetically sorted. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | Kconfig: Replace spaces with tabs and missing newlineMichal Simek2018-07-302-12/+12
| | | | | | | | | | | | | | | | | | Trivial Kconfig cleanup. Use tabs instead of spaces and every Kconfig entry should be separated by newline. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
* | Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini2018-07-278-86/+41
|\ \
| * | armv8: ls1046ardb: Add falcon mode for for QSPI bootYork Sun2018-07-262-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | A new defconfig is introduced to support SPL boot from QSPI NOR flash. This is to support falcon mode for faster booting into Linux. Signed-off-by: York Sun <york.sun@nxp.com>
| * | armv8: layerscape: spl: Initialize QSPI AHB for QSPI bootYork Sun2018-07-262-0/+7
| | | | | | | | | | | | | | | | | | To get full access of QSPI space, initialize AHB interface. Signed-off-by: York Sun <york.sun@nxp.com>
| * | armv8: dts: fsl-ls1012a: add sata node supportYuantian Tang2018-07-264-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | One ls1012a, there is one SATA 3.0 advanced host controller interface which is a high-performance SATA solution that delivers comprehensive and fully-compliant generation 3 (1.5 Gb/s - 6.0 Gb/s) serial ATA capabilities, in accordance with the serial ATA revision 3.0 of Serial ATA International Organization. Add sata node to support this feature. Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8: fsl: remove sata supportYuantian Tang2018-07-262-86/+0
| | | | | | | | | | | | | | | | | | | | | | | | Remove the old implementation in order to enable DM for sata. Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8: layerscape: Enabled I-cache for SPL bootYork Sun2018-07-261-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Enable I-cache for SPL boot to boost performance. Earlier MMU was enabled only for LS2080A and has since been dropped by commit f539c8a4a7a5 ("armv8: ls2080a: Drop early MMU for SPL build"). Signed-off-by: York Sun <york.sun@nxp.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-tegraTom Rini2018-07-268-33/+56
|\ \ \
| * | | tegra: beaver/apalis: Fix DTC warningTom Warren2018-07-262-6/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix warning when compiling tegra30-beaver/-apalis.dts with latest DTC: "Warning (avoid_unnecessary_addr_size): /pci/pch@1f,0: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property" Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | ARM: tegra: avoid using secure carveout RAMStephen Warren2018-07-261-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If a secure carveout exists, U-Boot cannot use that memory. Fix carveout_size() to reflect this, and hence transitively fix usable_ram_size_below_4g() and board_get_usable_ram_top(). This change ensures that when U-Boot copies the secure monitor code to install it, the copy target is not in-use for U-Boot code/data. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | ARM: PSCI: Enable the PSCI nodeStephen Warren2018-07-261-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When fixing up the DT to report PSCI support, explicitly enable the node. DTs may ship with the node disabled in case a PSCI implementation is not present, and expect any PSCI implementation to enable the node if they are actually present. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | ARM: PSCI: Support PSCI v0.2Stephen Warren2018-07-261-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enhance the PSCI DT editing code to allow setting a PSCI v0.2 compatible value in the DT. The CONFIG_ option is added to the whitelist to match the existing PSCI_1_0 option. While not adding new options to Kconfig isn't ideal, I figure it's better to keep related options together. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | ARM: define MON_MODEStephen Warren2018-07-261-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a MON_MODE define for ARM's monitor mode. This can be used later by a secure monitor to avoid hard-coding mode IDs. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | ARM: tegra: implement RAM repairBibek Basu2018-07-262-2/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | RAM repair has a few pre-requisites: 1) PMIC power supply (rail) enabled. 2) PMC CRAIL power partition powered. 3) Fuse clock active (it's the default). 4) PLLP reshift branch enabled (it's the default, when PLLP is active). RAM repair also only need run whenever specific partitions are powered (main SoC and CCPLEX respectively); RAM repair does not need to be triggered when any other partition changes state. start_cpu() needs to be re-ordered slightly to match these requirements. Note that C0NC and CE0 aren't required for RAM repair to operate, but they also do no harm, so the entire of powerup_cpus() is moved rather than splitting it up. The call to remove_cpu_resets() is moved last to ensure that all other actions complete before releasing reset; since the PMC power partitions are now enabled early, releasing reset is what causes the CPUs to start executing code, and RAM repair must complete before the CPU boots. Note that this commit is the result of squashing a numbmer of commits in NVIDIA's downstream L4T branch, hence the multiple signoffs below. Signed-off-by: Bibek Basu <bbasu@nvidia.com> Signed-off-by: Sandipan Patra <spatra@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | Revert "tegra: Introduce SRAM repair on tegra124"Stephen Warren2018-07-262-31/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 701b7b1d2cf657d435d2bd6caf43d0247d37220d. It will be immediately replaced by a different implementation that is more complete and runs are more targetted times. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
generated by cgit (git 2.34.1) at 2024-11-19 22:31:00 +0000