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| * | | stm32mp1: add bootstage supportPatrick Delaunay2019-05-231-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the needed configurations for bootstage and activate bootstage command. BOOTSTAGE_REPORT is not activated by default. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
| * | | armv7: timer: init timer with bootstagePatrick Delaunay2019-05-231-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In initf_bootstage() we call bootstage_mark_name() which ends up calling timer_get_us() before timer_init(); that cause crash for stm32mp1. This patch solve the issue without changing the initialization sequence. See also commit 97d20f69f53e ("Enable CONFIG_TIMER_EARLY with bootstage") for other solution when DM is activated for TIMER. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
| * | | stm32mp1: add bootcount supportPatrick Delaunay2019-05-232-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | Activate bootcount and use TAMP register to store the count value. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
| * | | stm32mp1: psci: add synchronization with ROM codePatrick Delaunay2019-05-231-4/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use SGI0 interruption and TAMP_BACKUP_MAGIC_NUMBER to synchronize the core1 boot sequence requested by core0 in psci_cpu_on(): - a initial interruption is needed in ROM code after RCC_MP_GRSTCSETR_MPUP1RST (psci_cpu_off) - the ROM code set to 0 the 2 registers + TAMP_BACKUP_BRANCH_ADDRESS + TAMP_BACKUP_MAGIC_NUMBER when magic is not egual to BOOT_API_A7_CORE0_MAGIC_NUMBER This patch solve issue for cpu1 restart in kernel. echo 0 > /sys/devices/system/cpu/cpu1/online echo 1 > /sys/devices/system/cpu/cpu1/online Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
| * | | stm32mp1: cosmetic: bsec: reorder include filesPatrick Delaunay2019-05-231-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Reorder the include files in alphabetic order. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
| * | | stm32mp1: migrate PREBOOT to KconfigPatrick Delaunay2019-05-231-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Use Kconfig to activate CONFIG_PREBOOT (empty by default). Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
| * | | stm32mp1: Move ENV_SIZE and ENV_OFFSET to KconfigPatrick Delaunay2019-05-231-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add arch stm32mp for ENV migration step and drop more items from include/configs/xxx.h. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
| * | | stm32mp1: Move config SYS_MALLOC_LEN to KconfigPatrick Delaunay2019-05-231-0/+3
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | This patch moves the the config SYS_MALLOC_LEN to Kconfig as it is already done for zynq arch in commit 01aa5b8f0503 ("Kconfig: Move config SYS_MALLOC_LEN to Kconfig for zynq") Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
* | | Merge git://git.denx.de/u-boot-mpc85xxTom Rini2019-05-242-3/+46
|\ \ \ | | | | | | | | | | | | - Enable DM for SATA, SDHC, USB in T2080QDS
| * | | powerpc: mpc85xx: delete FSL_SATA for T2080QDS board.Peng Ma2019-05-231-3/+1
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Peng Ma <peng.ma@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
| * | | arch: powerpc: add sata node for t2080 dtsPeng Ma2019-05-231-0/+16
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Peng Ma <peng.ma@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
| * | | arch: powerpc: add usb node in t2080 dtsYinbo Zhu2019-05-231-0/+19
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
| * | | arch: powerpc: add eSDHC node to t2080qds dtsYinbo Zhu2019-05-231-0/+10
| |/ / | | | | | | | | | | | | Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
* | | m68k: add dspi chip-select supportAngelo Dureghello2019-05-246-3/+139
| | | | | | | | | | | | | | | | | | | | | Signed-off-by: Angelo Dureghello <angelo@sysam.it> Changes for v5: - new patch
* | | m68k: move dspi bus control functions into cf_spi.c driverAngelo Dureghello2019-05-242-166/+41
| | | | | | | | | | | | | | | | | | | | | This patches move dspi bus-related operations into more proper location, to avoid the driver to declares them as externs. Signed-off-by: Angelo Dureghello <angelo@sysam.it>
* | | m68k: add OF control support to m68kAngelo Dureghello2019-05-241-0/+1
| | | | | | | | | | | | | | | | | | | | | Add SUPPORT_OF_CONTROL at this stage, to avoid to break build bisectability. Signed-off-by: Angelo Dureghello <angelo@sysam.it>
* | | m68k: enabling long jumps on mcf54x5 SoCsAngelo Dureghello2019-05-241-2/+4
| | | | | | | | | | | | | | | | | | | | | Growing of binary size asks for long assembly jumps. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Angelo Dureghello <angelo@sysam.it>
* | | m68k: add initial dts files for all m68k boardsAngelo Dureghello2019-05-2449-0/+1067
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds basic dts files for all the m68k boards. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Angelo Dureghello <angelo@sysam.it> [trini: Add CONFIG_TARGET_M5329EVB dtbs and update M5329EVB defconfigs] Signed-off-by: Tom Rini <trini@konsulko.com>
* | | m68k: architecture changes to support fdtAngelo Dureghello2019-05-232-2/+37
| | | | | | | | | | | | | | | | | | | | | This patch adds fdt support to the m68k architecture. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Angelo Dureghello <angelo@sysam.it>
* | | m68k: add basic set of devicetreesAngelo Dureghello2019-05-2316-0/+714
|/ / | | | | | | | | | | | | | | | | | | | | This patch adds a basic group of devicetrees, one for each cpu family, including actually just uart and dspi devices, since these are the drivers supporting devicetree (support added in this patch-set). Acked-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Angelo Dureghello <angelo@sysam.it> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
* | arm: dts: fsl-ls1028a: add sp805 watchdog nodeQiang Zhao2019-05-221-0/+5
| | | | | | | | | | Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
* | armv8: fsl-layerscape: Set env_loc to ENVL_NOWHERE with CONFIG_ENV_IS_NOWHERE.Udit Agarwal2019-05-221-9/+2
| | | | | | | | | | | | | | | | | | ENVL_NOWHERE is dependent on CONFIG_ENV_IS_NOWHERE and not on CONFIG_CHAIN_OF_TRUST so return ENVL_NOWHERE when CONFIG_ENV_IS_NOWHERE is enabled Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
* | ARM: dts: Freescale: Add ecc addr for sata nodePeng Ma2019-05-225-5/+15
| | | | | | | | | | | | | | Move the ecc addr from driver to dts. Signed-off-by: Peng Ma <peng.ma@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
* | armv8: ls1028aqds: Add support of LS1028AQDSYuantian Tang2019-05-224-1/+101
| | | | | | | | | | | | | | | | | | | | | | | | | | LS1028AQDS Development System is a high-performance computing, evaluation, and development platform that supports LS1028A QorIQ Architecture processor. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang yuantian <andy.tang@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
* | armv8: ls1028ardb: Add support for LS1028ARDBYuantian Tang2019-05-224-0/+102
| | | | | | | | | | | | | | | | | | | | | | | | | | LS1028A is an ARMv8 implementation. LS1028ARDB is an evaluation platform that supports the LS1028A family SoCs. This patch add basic support of the platform. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
* | armv8: ls1028a: Add NXP LS1028A SoC supportYuantian Tang2019-05-2210-2/+525
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
* | armv8: lx2160a: add PCIe controller DT nodesHou Zhiqiang2019-05-221-0/+85
| | | | | | | | | | | | | | | | The LX2160A integrated 6 PCIe Gen4 controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
* | kconfig: add dependency PCIE_LAYERSCAPE_GEN4 for FSL_PCIE_COMPATHou Zhiqiang2019-05-221-1/+1
| | | | | | | | | | | | | | | | | | The LX2160A PCIe is using driver PCIE_LAYERSCAPE_GEN4 instead of PCIE_LAYERSCAPE. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
* | armv8: lx2160a: add MMU table entries for PCIeHou Zhiqiang2019-05-223-1/+29
| | | | | | | | | | | | | | | | The lx2160a have up to 6 PCIe controllers and have different address and size of PCIe region. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
* | armv8: fsl-layerscpae: correct the PCIe controllers' region sizeHou Zhiqiang2019-05-221-0/+7
| | | | | | | | | | | | | | | | | | The LS2080A has 8GB region for each PCIe controller, while the other platforms have 32GB. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
* | armv8: layerscape: use PCIe address macro for precompile PCIe MMU entryHou Zhiqiang2019-05-221-1/+3
|/ | | | | | | | Change to use PCIe address macro to determine if precompile the PCIe MMU table entry. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
* Merge git://git.denx.de/u-boot-mpc83xxTom Rini2019-05-2156-369/+10368
|\ | | | | | | - Update MPC83xx platform support to current best practices, etc.
| * mpc83xx: Add gazerbeam boardDirk Eibach2019-05-212-1/+20
| | | | | | | | | | | | | | | | | | | | | | | | The gdsys gazerbeam board is based on a Freescale MPC8308 SOC. It boots from NOR-Flash, kernel and rootfs are stored on SD-Card. On board peripherals include: - 2x 10/100 Mbit/s Ethernet (optional) Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc> Signed-off-by: Mario Six <mario.six@gdsys.cc>
| * gazerbeam: Add u-boot specific dts include fileMario Six2019-05-212-0/+252
| | | | | | | | | | | | | | Add a U-Boot specific dts file, which encapsulates the needed modifications to the Gazerbeam Linux device tree. Signed-off-by: Mario Six <mario.six@gdsys.cc>
| * gazerbeam: Import Linux DTMario Six2019-05-219-0/+1178
| | | | | | | | | | | | Import the Linux device tree for the Gazerbeam board. Signed-off-by: Mario Six <mario.six@gdsys.cc>
| * mpc83xx: Define _end symbolMario Six2019-05-211-0/+6
| | | | | | | | | | | | | | | | | | | | To support OF_EMBED, the MPC83xx architecture has to define the "_end" symbol to correctly access the appended DT. Fortunately, MPC8xx already defines the symbol, and the linker script is quite similar to that of MPC83xx, so copy this approach for MPC83xx. Signed-off-by: Mario Six <mario.six@gdsys.cc>
| * powerpc: Simplify processor.hMario Six2019-05-211-120/+0
| | | | | | | | | | | | | | | | | | | | | | | | Lots of stuff in processor.h was taken verbatim from the Linux kernel. It was never synced, so most of it was removed or changed in the kernel since it was imported. Remove all the stuff that is unused in the current U-Boot sources; should anybody feel the need to re-sync with the kernel, they can do it later on. Signed-off-by: Mario Six <mario.six@gdsys.cc>
| * mpc83xx: Use pre-defined asm functionsMario Six2019-05-214-43/+60
| | | | | | | | | | | | | | | | | | | | For a lot of inline assembly calls in the mpc8xxx and mpc83xx directories, we already have convenient pre-defined helper functions, but they're not used, resulting in hard-to-read code. Use these helper functions where ever possible and useful. Signed-off-by: Mario Six <mario.six@gdsys.cc>
| * mpc83xx: Replace ppcDWstore with inline assemblyMario Six2019-05-212-12/+18
| | | | | | | | | | | | | | | | | | | | | | ppcDWstore/ppcDWload are hardly used by any board, but since they're implemented in start.S, they're always present in every U-Boot image, even if they're not needed. Re-implement these fuctions in C with inline assembly, so that the compiler can decide when to actually include them. Signed-off-by: Mario Six <mario.six@gdsys.cc>
| * mpc83xx: Don't define cpu_eth_init for DM ethMario Six2019-05-211-0/+2
| | | | | | | | | | | | | | Don't use the legacy method of initializing the ethernet controller on MPC83xx when DM is active. Signed-off-by: Mario Six <mario.six@gdsys.cc>
| * mpc83xx: Add arch clock.h to make SDHC workMario Six2019-05-211-0/+22
| | | | | | | | | | | | | | | | | | The fsl-esdhc driver can be used for the SDHC functionality on MPC83xx, but it needs some additional definitions. Add a clock.h file, so we can use the driver for MPC83xx. Signed-off-by: Mario Six <mario.six@gdsys.cc>
| * mpc83xx: Get rid of CONFIG_SYS_DDR_SDRAM_BASEMario Six2019-05-211-1/+1
| | | | | | | | | | | | | | | | CONFIG_SYS_DDR_SDRAM_BASE is set to the same value as CONFIG_SYS_SDRAM_BASE on all existing boards. Just use CONFIG_SYS_SDRAM_BASE instead. Signed-off-by: Mario Six <mario.six@gdsys.cc>
| * mpc83xx: Migrate CONFIG_LCRR_* to KconfigMario Six2019-05-214-22/+176
| | | | | | | | | | | | Migrate the CONFIG_LCRR_* settings to Kconfig. Signed-off-by: Mario Six <mario.six@gdsys.cc>
| * mpc83xx: Migrate SPCR to KconfigMario Six2019-05-215-28/+165
| | | | | | | | | | | | Migrate the SPCR setting to Kconfig. Signed-off-by: Mario Six <mario.six@gdsys.cc>
| * mpc83xx: Migrate arbiter config to KconfigMario Six2019-05-215-32/+173
| | | | | | | | | | | | Migrate the arbiter configuration to Kconfig. Signed-off-by: Mario Six <mario.six@gdsys.cc>
| * mpc8308: Migrate system io config to KconfigMario Six2019-05-215-0/+364
| | | | | | | | | | | | Migrate the system IO configuration setting to Kconfig. Signed-off-by: Mario Six <mario.six@gdsys.cc>
| * mpc83xx: Migrate CONFIG_SYS_IMMR to KconfigMario Six2019-05-211-0/+7
| | | | | | | | | | | | Migrate CONFIG_SYS_IMMR to Kconfig for MPC83xx. Signed-off-by: Mario Six <mario.six@gdsys.cc>
| * mpc83xx: Migrate HID config to KconfigMario Six2019-05-214-0/+639
| | | | | | | | | | | | Mirate the HID configuration settings to Kconfig. Signed-off-by: Mario Six <mario.six@gdsys.cc>
| * mpc83xx: Prepare usage of DM gpio driverMario Six2019-05-211-0/+8
| | | | | | | | | | | | | | | | The MPC85xx GPIO driver was converted to handle a broader range of SoCs. Prepare the MPC83xx code for usage of this driver. Signed-off-by: Mario Six <mario.six@gdsys.cc>
| * powerpc: mpc83xx: fdt: Use get_serial_clock()Mario Six2019-05-211-2/+2
| | | | | | | | | | | | | | | | | | | | Replace the hard-coded CONFIG_SYS_NS16550_CLK value for the FDT fixup with the previously introduced get_serial_clock function This will make it possible to activate DM for serial devices on MPC83xx later on. Signed-off-by: Mario Six <mario.six@gdsys.cc>
generated by cgit (git 2.34.1) at 2025-01-31 04:48:19 +0000