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* video: omap: drop domain clock enabling by SOC apiDario Binacchi2021-01-121-1/+1
| | | | | | | Enabling the domain clock is performed by the sysc interconnect target module driver during the video device probing. Signed-off-by: Dario Binacchi <dariobin@libero.it>
* video: omap: add panel driverDario Binacchi2021-01-1211-44/+141
| | | | | | | | | | | | | | | The previous version of am335x-fb.c contained the functionalities of two drivers that this patch has split. It was a video type driver that used the same registration compatible string that now registers a panel type driver. The proof of this is that two compatible strings were referred to within the same driver. There are now two drivers, each with its own compatible string, functions and API. Furthermore, the panel driver, in addition to decoding the display timings, is now also able to manage the backlight. Signed-off-by: Dario Binacchi <dariobin@libero.it> Reviewed-by: Simon Glass <sjg@chromium.org>
* dm: core: add a function to decode display timingsDario Binacchi2021-01-121-0/+46
| | | | | | | | The patch adds a function to get display timings from the device tree node attached to the device. Signed-off-by: Dario Binacchi <dariobin@libero.it> Reviewed-by: Simon Glass <sjg@chromium.org>
* arm: dts: am335x: enable scm_clocks auto bindingDario Binacchi2021-01-122-0/+16
| | | | | | | Adding the 'simple-bus' compatible string to the scm_clocks node will allow its automatic binding. Signed-off-by: Dario Binacchi <dariobin@libero.it>
* fdt: translate address if #size-cells = <0>Dario Binacchi2021-01-121-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The __of_translate_address routine translates an address from the device tree into a CPU physical address. A note in the description of the routine explains that the crossing of any level with since inherited from IBM. This does not happen for Texas Instruments, or at least for the beaglebone device tree. Without this patch, in fact, the translation into physical addresses of the registers contained in the am33xx-clocks.dtsi nodes would not be possible. They all have a parent with #size-cells = <0>. The CONFIG_OF_TRANSLATE_ZERO_SIZE_CELLS symbol makes translation possible even in the case of crossing levels with #size-cells = <0>. The patch acts conservatively on address translation, except for removing a check within the of_translate_one function in the drivers/core/of_addr.c file: + ranges = of_get_property(parent, rprop, &rlen); - if (ranges == NULL && !of_empty_ranges_quirk(parent)) { - debug("no ranges; cannot translate\n"); - return 1; - } if (ranges == NULL || rlen == 0) { offset = of_read_number(addr, na); memset(addr, 0, pna * 4); debug("empty ranges; 1:1 translation\n"); There are two reasons: 1 The function of_empty_ranges_quirk always returns false, invalidating the following if statement in case of null ranges. Therefore one of the two checks is useless. 2 The implementation of the of_translate_one function found in the common/fdt_support.c file has removed this check while keeping the one about the 1:1 translation. The patch adds a test and modifies a check for the correctness of an address in the case of enabling translation also for zero size cells. The added test checks translations of addresses generated by nodes of a device tree similar to those you can find in the files am33xx.dtsi and am33xx-clocks.dtsi for which the patch was created. The patch was also tested on a beaglebone black board. The addresses generated for the registers of the loaded drivers are those specified by the AM335x reference manual. Signed-off-by: Dario Binacchi <dariobin@libero.it> Tested-by: Dario Binacchi <dariobin@libero.it> Reviewed-by: Simon Glass <sjg@chromium.org>
* arm: dts: am335x: enable prcm_clocks auto bindingDario Binacchi2021-01-121-0/+4
| | | | | | | Adding the 'simple-bus' compatible string to the prcm_clocks node will allow its automatic binding. Signed-off-by: Dario Binacchi <dariobin@libero.it>
* ti: am33xx: fix do_enable_clocks() to accept NULL parametersDario Binacchi2021-01-121-4/+6
| | | | | | | | | Up till this commit passing NULL as input parameter was allowed, but not handled properly. When a NULL parameter was passed to the function a data abort was raised. Signed-off-by: Dario Binacchi <dariobin@libero.it> Reviewed-by: Simon Glass <sjg@chromium.org>
* arm: dts: am335x: include am33xx-u-boot.dtsiDario Binacchi2021-01-1211-0/+23
| | | | | | Include the SoC U-boot DTS in each am335x-<board>-u-boot.dtsi. Signed-off-by: Dario Binacchi <dariobin@libero.it>
* arm: ti: am33xx: add DPLL_EN_FAST_RELOCK_BYPASS macroDario Binacchi2021-01-121-0/+1
| | | | | | | Add missing DPLL_EN_FAST_RELOCK_BYPASS macro. Used to put the DPLL in idle bypass fast relock mode. Signed-off-by: Dario Binacchi <dariobin@libero.it>
* clk: add clk_round_rate()Dario Binacchi2021-01-121-0/+9
| | | | | | | | | | | | It returns the rate which will be set if you ask clk_set_rate() to set that rate. It provides a way to query exactly what rate you'll get if you call clk_set_rate() with that same argument. So essentially, clk_round_rate() and clk_set_rate() are equivalent except the former does not modify the clock hardware in any way. Signed-off-by: Dario Binacchi <dariobin@libero.it> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Sean Anderson <seanga2@gmail.com>
* arm: dts: sync am33xx with Linux 5.9-rc7Dario Binacchi2021-01-1210-542/+2273
| | | | | | | | | | | | | | | | | | | | | | There have been several changes to the am33xx.dtsi, so this patch re-syncs it with Linux. Let's add proper interconnect hierarchy for l4 interconnect instances with the related ti-sysc interconnect module data as documented in Documentation/devicetree/bindings/bus/ti-sysc.txt of the Linux kernel. With l4 interconnect hierarchy and ti-sysc interconnect target module data in place, we can simply move all the related child devices to their proper location and enable probing using ti-sysc. The am33xx-clock.dtsi file is the same as that of the Linux kernel, except for the reg property of the node l4-wkup-clkctrl@0. As for the am33xx.dtsi file, all the devices with drivers not yet implemented and those I was able to test with this patch have been moved to am33xx-l4.dtsi. In case of any regressions, problem devices can be reverted by moving them back and removing the related interconnect target module node. Signed-off-by: Dario Binacchi <dariobin@libero.it>
* bus: ti: add minimal sysc interconnect target driverDario Binacchi2021-01-121-0/+1
| | | | | | | | | | | | | We can handle the sysc interconnect target module in a generic way for many TI SoCs. Initially let's just enable domain clocks before the children are probed. The code is loosely based on the drivers/bus/ti-sysc.c of the Linux kernel version 5.9-rc7. For DT binding details see: - Documentation/devicetree/bindings/bus/ti-sysc.txt Signed-off-by: Dario Binacchi <dariobin@libero.it>
* arm: dts: k3-j721e: ddr: Update to 0.5.0 version of DDR config toolPraneeth Bajjuri2021-01-122-219/+219
| | | | | | | | Update the ddr settings to use the DDR reg config tool rev 0.5.0. This enables 4266MTs DDR configuration. Signed-off-by: Praneeth Bajjuri <praneeth@ti.com> Signed-off-by: Kevin Scholz <k-scholz@ti.com>
* arm: dts: am654-base-board-uboot: Add aliases for USB subsystemsAswath Govindraju2021-01-121-0/+2
| | | | | | | | | | | | | | The sequence number assigned for USB subsystem in a uclass is dependent on the order of occurrence in the device tree. If the dr_mode of USB3SS0 controller is varied then the sequence number of USB3SS1 controller also changes. If aliases are added then sequence numbers are assigned using the alias number. This makes the sequence number of USB3SS1 controller independent of USB3SS0 controller's dr_mode. Therefore, add aliases to fix the sequence number assigned to the USB subsystems. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
* arm: dts: am654-base-board-uboot: Set USB0 dr_mode to hostAswath Govindraju2021-01-121-1/+1
| | | | | | | USB3SS0 controller is to be used as a host in U-boot. Fix it by changing the dr_mode to host. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
* Merge branch 'next'Tom Rini2021-01-11148-457/+902
|\ | | | | | | Signed-off-by: Tom Rini <trini@konsulko.com>
| * Merge tag 'xilinx-for-v2021.04' of ↵Tom Rini2021-01-063-33/+75
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze into next Xilinx changes for v2021.04 arm64: - DT updates microblaze: - Add support for NOR device support spi: - Fix unaligned data write issue nand: - Minor code change xilinx: - Fru fix in limit calculation - Fill git repo link for all Xilinx boards video: - Add support for seps525 spi display tools: - Minor Vitis file support cmd/common - Minor code indentation fixes serial: - Uartlite debug uart initialization fix
| | * arm64: zynqmp: Add Ethernet node for zcu1285 revAHarini Katakam2021-01-051-0/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch add ethernet node gem1 to zcu1285 RevB. GMII to RGMII converter sits between MAC and external phy connected over GMII to MAC and RGMMI to external phy Signed-off-by: Harini Katakam <harini.katakam@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| | * arm64: zynqmp: Add ethernet node for zcu1275 revBSiva Durga Prasad Paladugu2021-01-051-0/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch add ethernet node gem1 to zcu1275 RevB. GMII to RGMII converter sits between MAC and external phy connected over GMII to MAC and RGMMI to external phy. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| | * arm64: zynqmp: Sync DT with Linux kernelMichal Simek2021-01-041-33/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All changes are recorded in lore.kernel.org. Here are links to that patches for the record. Link: https://lore.kernel.org/r/f59a63d8cb941592de6d2dee8afa6f120b2e40c8.1601379794.git.michal.simek@xilinx.com Link: https://lore.kernel.org/r/68f20a2b2bb0feee80bc3348619c2ee98aa69963.1598263539.git.michal.simek@xilinx.com Link: https://lore.kernel.org/r/f767fe007e446a2299fda9905e75b723c650a424.1605021644.git.michal.simek@xilinx.com Link: https://lore.kernel.org/r/cc294ae1a79ef845af6809ddb4049f0c0f5bb87a.1598259551.git.michal.simek@xilinx.com Link: https://lore.kernel.org/r/20200629081744.13916-1-krzk@kernel.org And there are other minor changes (just moving things around). Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | Merge tag 'dm-pull-5jan21' of git://git.denx.de/u-boot-dm into nextTom Rini2021-01-0582-215/+372
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Driver model: make some udevice fields private Driver model: Rename U_BOOT_DEVICE et al. dtoc: Tidy up and add more tests ns16550 code clean-up x86 and sandbox minor fixes for of-platdata dtoc prepration for adding build-time instantiation
| | * | dm: Rename DM_GET_DRIVER() to DM_DRIVER_GET()Simon Glass2021-01-0529-41/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the spirit of using the same base name for all of these related macros, rename this to have the operation at the end. This is not widely used so the impact is fairly small. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * | dm: Rename U_BOOT_DEVICE() to U_BOOT_DRVINFO()Simon Glass2021-01-059-14/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current macro is a misnomer since it does not declare a device directly. Instead, it declares driver_info record which U-Boot uses at runtime to create a device. The distinction seems somewhat minor most of the time, but is becomes quite confusing when we actually want to declare a device, with of-platdata. We are left trying to distinguish between a device which isn't actually device, and a device that is (perhaps an 'instance'?) It seems better to rename this macro to describe what it actually is. The macros is not widely used, since boards should use devicetree to declare devices. Rename it to U_BOOT_DRVINFO(), which indicates clearly that this is declaring a new driver_info record, not a device. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * | dm: core: Access device ofnode through functionsSimon Glass2021-01-051-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present ofnode is present in the device even if it is never used. With of-platdata this field is not used, so can be removed. In preparation for this, change the access to go through inline functions. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * | x86: Drop rtc from SPLSimon Glass2021-01-051-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The RTC is not currently used in SPL. Drop it so that it does not take up space. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * | x86: coral: Remove unwanted nodes from SPL/TPLSimon Glass2021-01-051-6/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some devices are not needed in SPL/TPL. For TPL this causes the generation of unnecessary of-platadata structs. Make some adjustments to fix this. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * | x86: apl: Adjust how the UART gets its platform dataSimon Glass2021-01-052-20/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present this driver calls malloc() to start a new platform data structure, fills it in and tells driver model to use it. We want to avoid malloc, particularly with the new version of of-platdata. Create a new struct which encompasses both the dtd struct and the ns16550 one, to avoid this. Unfortunately we must copy the data into the right place for the ns16550 driver. Add some comments about this. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * | x86: sysreset: Move priv/plat structs to headersSimon Glass2021-01-051-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With the new of-platdata, these need to be available to dt_platdata.c so must be in header files. Move them and add the dtd struct too. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
| | * | x86: apl: Use struct spi_nor instead of struct spi_flashSimon Glass2021-01-051-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This construct effectively uses struct spi_nor due to a #define in spi-nor.h so we may as well use that struct here. This allows dtoc to parse it correctly. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * | x86: Move priv/plat structs for intel_common to headersSimon Glass2021-01-054-27/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | With the new of-platdata, these need to be available to dt_platdata.c so must be in header files. Move them. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * | x86: apl: Move priv/plat structs to headersSimon Glass2021-01-055-26/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | | | With the new of-platdata, these need to be available to dt_platdata.c so must be in header files. Move them. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * | sandbox: Update dts files to reduce SPL sizeSimon Glass2021-01-052-8/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present there are require a few devices in the devicetree which are not actually used in SPL. This will cause problems with the new of-platdata, since it will try to instantiate devices which are not compiled into U-Boot. Update the devicetree to remove these devices from SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * | sandbox: i2c: Move priv into a header fileSimon Glass2021-01-051-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Move this struct into a header file so that dtoc can include it in its dt-platdata.c file. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * | sandbox: serial: Move priv into a header fileSimon Glass2021-01-051-0/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move this struct into a header file so that dtoc can include it in its dt-platdata.c file. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
| | * | sandbox: remove ram buffer file when U-Boot is loaded by SPLPatrick Delaunay2021-01-053-4/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update management of "--rm_memory" sandbox's option and force this option when U-Boot is loaded by SPL in os_spl_to_uboot() and remove the ram file after reading in main() as described in option help message: "Remove memory file after reading". This patch avoids that the file "/tmp/u-boot.mem.XXXXXX" [created in os_jump_to_file() when U-Boot is loaded by SPL] is never deleted because state_uninit() is not called after U-Boot execution (CtrlC or with running pytest for example). This issue is reproduced by > build-sandbox_spl/spl/u-boot-spl and CtrlC in U-Bot console > make qcheck One temp file is created after each SPL and U-Boot execution (7 tims in qcheck after test_handoff.py, test_ofplatdata.py, test_spl.py execution). Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| | * | x86: Fix header guard in asm/pmu.hSimon Glass2021-01-051-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | This has the wrong name. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * | x86: tpl: Remove unwanted devicetree stringSimon Glass2021-01-051-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update this driver to use of_match_ptr(). This reduces the TPL binary size by about 32 bytes. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * | x86: apl: Reduce size for TPLSimon Glass2021-01-058-11/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update various drivers to use of_match_ptr() and to avoid including debug strings in TPL. Omit the WiFi driver entirely, since it is not used in TPL. This reduces the TPL binary size by about 608 bytes. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * | x86: apl: Update hostbridge to remove unwanted TPL codeSimon Glass2021-01-051-5/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present several strings from this file appear in the TPL binary. Add preprocessor checks to drop them. This reduces the TPL binary size by about 128 bytes. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * | x86: coral: Move fsp-m settings to a subnodeSimon Glass2021-01-052-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present these settings are in the node for host-bridge and so are visible in TPL as well as SPL. But they are only used for SPL. Move them to a subnode so that TPL does not included them. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * | x86: Move call64 into its own sectionSimon Glass2021-01-051-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | When this code is not used (e.g. by TPL) we want it to be excluded from the image. Put it in its own section so that this happens. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * | x86: apl: Use const for driver operationsSimon Glass2021-01-052-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Update these declarations to const to ensure that the data ends up in the rodata section. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * | arc: m68k: nds32: nios2: sh: xtensa: Add empty spl.h headerSimon Glass2021-01-056-0/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present it is not possible to include spl.h in on these architectures since the asm/spl.h file is not present. We want to be able to use the spl_phase() function, so add empty headers to make things build. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * | dm: Use access methods for dev/uclass private dataSimon Glass2021-01-054-3/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Most drivers use these access methods but a few do not. Update them. In some cases the access is not permitted, so mark those with a FIXME tag for the maintainer to check. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Pratyush Yadav <p.yadav@ti.com>
| | * | x86: apl: Drop support for !OF_PLATDATA_PARENTSimon Glass2021-01-052-28/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This code was kept around after of-platdata started supporting parent devices. That feature seems stable now, so let's drop it. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * | spl: Drop bd_info in the data sectionSimon Glass2021-01-051-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This uses up space in the SPL binary but it always starts as zero. Also some boards cannot support data in TPL (e.g. Intel Apollo Lake). Use malloc() to allocate this structure instead, by moving the init a little later, after malloc() is inited. Make this function optional since it pulls in malloc(). This reduces the TPL binary size on coral by about 64 bytes Signed-off-by: Simon Glass <sjg@chromium.org>
| | * | sandbox: Drop unnecessary test nodeSimon Glass2021-01-051-5/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The spl-test4 node deliberately has an invalid compatible string. This causes a warning from dtoc and the check it does is not really necessary. Drop it, to avoid the warning and associated confusion. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * | serial: Rename ns16550 functions to lower caseSimon Glass2021-01-053-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Lower case should be used for function names. Update this driver and its callers accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
| | * | serial: Update NS16550_t and struct NS16550Simon Glass2021-01-055-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Typedefs should not be used in U-Boot and structs should be lower case. Update the code to use struct ns16550 consistently. Put a header guard on the file while we are here. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
| * | | Merge tag 'v2021.01-rc5' into nextTom Rini2021-01-05135-1913/+2012
| |\ \ \ | | |/ / | |/| / | | |/ | | | | | | Prepare v2021.01-rc5 Signed-off-by: Tom Rini <trini@konsulko.com>
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