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* Merge git://git.denx.de/u-boot-imxTom Rini2018-04-1515-26/+194
|\ | | | | | | Signed-off-by: Tom Rini <trini@konsulko.com>
| * imx: Create distinct pre-processed mkimage config filesTrent Piepho2018-04-151-7/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Each imx image is created by a separate sub-make and during this process the mkimage config file is run though cpp. The cpp output is to the same file no matter what imx image is being created. This means if two imx images are generated in parallel they will attempt to independently produce the same pre-processed mkimage config file at the same time. Avoid the problem by making the pre-processed config file name unique based on the imx image it will be used in. This way each image will create a unique config file and they won't clobber each other when run in parallel. This should fixed the build bug referenced in b5b0e4e3 ("imximage: Remove failure when no IVT offset is found"). Cc: Breno Lima <breno.lima@nxp.com> Cc: Thomas Petazzoni <thomas.petazzoni@bootlin.com> Cc: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Trent Piepho <tpiepho@impinj.com> Tested-by: Fabio Estevam <fabio.estevam@nxp.com>
| * mx31ads: DeleteTom Rini2018-04-151-6/+0
| | | | | | | | | | | | This platform has been marked as orphaned since September 2013, remove. Signed-off-by: Tom Rini <trini@konsulko.com>
| * imx31_phycore: DeleteTom Rini2018-04-151-12/+0
| | | | | | | | | | | | This platform has been marked as orphaned since September 2013, remove. Signed-off-by: Tom Rini <trini@konsulko.com>
| * imx: mx7: snvs: Add an SNVS init routineBryan O'Donoghue2018-04-154-1/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Working with HAB on the i.MX7 we've encountered a case where a board that successfully authenticates u-boot when booting Linux via OPTEE subsequently fails to properly bring up the RTC. The RTC registers live in the low-power block of the Secure Non-Volatile Storage (SNVS) block. The root cause of the error has been traced to the HAB handing off the SNVS-RTC in a state where HPCOMR::NPSWA_EN = 0 in other words where the Non-Privileged Software Access Enable bit is zero. In ordinary circumstances this is OK since we typically do not run in TZ mode, however when we boot via HAB and enablng TrustZone, it is required to set HPCOMR::NPSWA_EN = 1 in order for the upstream Linux driver to have sufficient permissions to manipulate the SNVS-LP block. On our reference board it is the difference between Linux doing this: root@imx7s-warp-mbl:~# dmesg | grep rtc snvs_rtc_enable read 0x00000000 from SNVS_LPLR @ 0x00000034 snvs_rtc_enable read 0x00000021 from SNVS_LPCR @ 0x00000038 snvs_rtc_enable read 0x00000000 from SNVS_HPLR @ 0x00000000 snvs_rtc_enable read 0x80002100 from SNVS_HPCOMR @ 0x00000004 snvs_rtc 30370000.snvs:snvs-rtc-lp: rtc core: registered 30370000.snvs:snvs-rtc-lp as rtc0 snvs_rtc 30370000.snvs:snvs-rtc-lp: setting system clock to2018-04-01 00:51:04 UTC (1522543864) and doing this: root@imx7s-warp-mbl:~# dmesg | grep rtc snvs_rtc_enable read 0x00000000 from SNVS_LPLR @ 0x00000034 snvs_rtc_enable read 0x00000020 from SNVS_LPCR @ 0x00000038 snvs_rtc_enable read 0x00000001 from SNVS_HPLR @ 0x00000000 snvs_rtc_enable read 0x00002020 from SNVS_HPCOMR @ 0x00000004 snvs_rtc 30370000.snvs:snvs-rtc-lp: failed to enable rtc -110 snvs_rtc: probe of 30370000.snvs:snvs-rtc-lp failed with error -110 hctosys: unable to open rtc device (rtc0) Note bit 1 of LPCR is not set in the second case and is set in the first case and that bit 31 of HPCOMR is set in the second case but not in the first. Setting NPSWA_EN in HPCOMR allows us to boot through enabling TrustZone and continue onto the kernel. The kernel then has the necessary permissions to set LPCR::SRTC_ENV (RTC enable in the LP command register) whereas in contrast - in the failing case the non-privileged kernel cannot do so. This patch adds a simple init_snvs() call which sets the permission-bit called from soc.c for the i.MX7. It may be possible, safe and desirable to perform this on other i.MX processors but for now this is only tested on i.MX7 as working. Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
| * imx: board: Add support for the K+P's kp_imx6q_tpc boardLukasz Majewski2018-04-151-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit provides support for Kieback & Peter GmbH IMX6Q based TPC board. U-boot console output: U-Boot SPL 2018.05-rc1-00005-g631e2d01fd (Apr 04 2018 - 21:16:24 +0200) Trying to boot from MMC1 U-Boot 2018.05-rc1-00005-g631e2d01fd (Apr 04 2018 - 21:16:24 +0200) CPU: Freescale i.MX6Q rev1.5 996 MHz (running at 792 MHz) CPU: Extended Commercial temperature grade (-20C to 105C) at 37C Reset cause: POR Board: K+P KP_IMX6Q_TPC i.MX6Q Watchdog enabled I2C: ready DRAM: 2 GiB MMC: FSL_SDHC: 0, FSL_SDHC: 1 Loading Environment from MMC... OK In: serial Out: serial Err: serial Net: FEC [PRIME] Autoboot in 3 seconds
| * imx: hab: Provide hab_auth_img_or_fail commandBryan O'Donoghue2018-04-151-0/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds hab_auth_img_or_fail() a command line function that encapsulates a common usage of authenticate and failover, namely if authenticate image fails, then drop to BootROM USB recovery mode. For secure-boot systems, this type of locked down behavior is important to ensure no unsigned images can be run. It's possible to script this logic but, when done over and over again the environment starts get very complex and repetitive, reducing that script repetition down to a command line function makes sense. Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Cc: Utkarsh Gupta <utkarsh.gupta@nxp.com> Cc: Breno Lima <breno.lima@nxp.com> Cc: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Tested-by: Breno Lima <breno.lima@nxp.com>
| * imx: mx7: Add comment to describe OTP TESTER registersBryan O'Donoghue2018-04-151-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The tester registers provide a unique chip-level identifier which get_board_serial() returns in a "struct tag_serialnr". This patch documents the properties of the registers; in summary. 31:0 OCOTP_TESTER0 (most significant) - FSL-wide unique, encoded LOT ID STD II/SJC CHALLENGE/ Unique ID OCOTP_TESTER1 (least significant) 31:24 - The X-coordinate of the die location on the wafer/SJC CHALLENGE/ Unique ID 23:16 - The Y-coordinate of the die location on the wafer/SJC CHALLENGE/ Unique ID 15:11 - The wafer number of the wafer on which the device was fabricated/SJC CHALLENGE/ Unique ID 10:0 - FSL-wide unique, encoded LOT ID STD II/SJC CHALLENGE/ Unique ID The 64 bits of data generate a unique serial number per-chip. Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
| * imx: mx7: Fix CONFIG_SERIAL_TAG compilationBryan O'Donoghue2018-04-151-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently when we define CONFIG_SERIAL_TAG we will barf with a failure to define "struct tag_serialnr". This structure is defined in <asm/setup.h>, this patch includes <asm/setup.h> to fix. Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
| * ARM: mx6: ddr: Add write leveling correction codeMarek Vasut2018-04-151-0/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When the DDR calibration is enabled, a situation may happen that it will fail on a few select boards out of a whole production lot. In particular, after the first write leveling stage, the MPWLDECTRLx registers will contain a value 0x1nn , for nn usually being 0x7f or slightly lower. What this means is that the HW write leveling detected that the DQS rising edge on one or more bundles arrives slightly _after_ CLK and therefore when the DDR DRAM samples CLK on the DQS rising edge, the CLK signal is already high (cfr. AN4467 rev2 Figure 7 on page 18). The HW write leveling then ends up adding almost an entire cycle (thus the 0x17f) to the DQS delay, which indeed aligns it, but also triggers subsequent calibration failure in DQS gating due to this massive offset. There are two observations here: - If the MPWLDECTRLx value is corrected from 0x17f to 0x0 , then the DQS gating passes, the entire calibration passes as well and the DRAM is perfectly stable even under massive load. - When using the NXP DRAM calibrator for iMX6/7, the value 0x17f or so in MPWLDECTRx register is not there, but it is replaced by 0x0 as one would expect. Someone from NXP finally explains why, quoting [1]: " Having said all that, the DDR Stress Test does something that we do not advertise to the users. The Stress Test iself looks at the values of the MPWLDECTRL0/1 fields before reporting results, and if it sees any filed with a value greater than 200/256 delay (reported as half-cycle = 0x1 and ABS_OFFSET > 0x48), the DDR Stress test will reset the Write Leveling delay for this lane to 0x000 and not report it in the log. The reason that the DDR Stress test does this is because a delay of more than 78% a clock cycle means that the DQS edge is arriving within the JEDEC tolerence of 25% of the clock edge. In most cases, DQS is arriving < 5% tCK of the SDCLK edge in the early case, and it does not make sense to delay the DQS strobe almost a full clock cycle and add extra latency to each Write burst just to make the two edges align exactly. In this case, we are guilty of making a decision for the customer without telling them we are doing it so that we don't have to provide the above explanation to every customer. They don't need to know it. " This patch adds the correction described above, that is if the MPWLDECTRx value is over 0x148, the value is corrected back to 0x0. [1] https://community.nxp.com/thread/456246 Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Eric Nelson <eric@nelint.com> Reviewed-by: Stefano Babic <sbabic@denx.de>
| * imx7: spl: Check for Serial Downloader in spl_boot_deviceEran Matityahu2018-03-291-0/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | Similarly to imx6, before reading the boot device, first check bmode to see if the serial downloader has been selected explicitly, then check whether the serial downloader has been activated due to unbootable primary boot devices (e.g. empty eMMC). If the serial downloader is activated, return BOOT_DEVICE_BOARD. This allows SPL with SDP support to wait for the U-Boot image to be loaded via the serial download protocol using imx_usb_loader. Signed-off-by: Eran Matityahu <eran.m@variscite.com>
| * imx7: Add src_base structure define macroEran Matityahu2018-03-291-0/+2
| | | | | | | | | | | | Add src_base structure global define macro, similarly to imx6 Signed-off-by: Eran Matityahu <eran.m@variscite.com>
| * ARM: dts: imx6ull: add wdog3Jörg Krause2018-03-291-0/+8
| | | | | | | | | | | | | | | | | | | | The i.MX6ULL has a WDOG3 located at start address 0x021E0000 in the AIPS-2 memory region [1]. [1] i.MX 6ULL Applications Processor Reference Manual, Rev. 1, 11/2017, Table 2-3. AIPS-2 memory map, p. 178 Signed-off-by: Jörg Krause <joerg.krause@embedded.rocks>
| * ARM: dts: imx6ul: add wdog3Jörg Krause2018-03-291-0/+8
| | | | | | | | | | | | | | | | | | | | The i.MX6UL has a WDOG3 located at start address 0x021E0000 in the AIPS-2 memory region [1]. [1] i.MX 6UltraLite Applications Processor Reference Manual, Rev. 1, 04/2016, Table-2-3 AIPS-2 memory map, p. 166 Signed-off-by: Jörg Krause <joerg.krause@embedded.rocks>
| * imx: fix CAAM base for i.MX6ULAnatolij Gustschin2018-03-291-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | HW accelerated "hash sha256 ..." command doesn't work on i.MX6UL, we get "CAAM was not setup properly or it is faulty" error message. This is due to wrong CAAM base 0x02100000, on i.MX6UL the CAAM base address is 0x02140000. Fix it. Note: with this patch applied the "hash sha256" commant still has some issues on i.MX6UL ("Invalid KEY Command" or other errors). With data cache off the "hash sha256" command works as expected. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
| * drivers: i2c: mxc: Update SYS_I2C_MXC_I2C support in KconfigSriram Dash2018-03-291-0/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | NXP layerscape platforms like ls1088a, ls2088a uses MXC I2C Controller. -Remove dependency of MX6 for the same. Update related configs to use Kconfig file. -Add SYS_I2C_MXC_I2C1,_I2C2,_I2C3,_I2C4 in Kconfig -Add CONFIG_SYS_MXC_I2C1_SPEED,_I2C2_,_I2C3_,_I2C4_ in Kconfig -Add CONFIG_SYS_MXC_I2C1_SLAVE,_I2C2_,_I2C3_,_I2C4_ in Kconfig Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
* | ARM: rmobile: Convert TPL to SPLMarek Vasut2018-04-133-9/+5
| | | | | | | | | | | | | | | | | | | | There is currently no use for building the SPL anymore, since the SPI loader can easily be replaced by TPL and TPL does load U-Boot directly. Upgrade TPL to SPL and replace what used to be SPL with it. This way we build the U-Boot sources only twice, not thrice. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* | ARM: rmobile: Shrink the TPLMarek Vasut2018-04-131-0/+4
| | | | | | | | | | | | | | | | | | Shrink the TPL by using tiny printf and tiny memset by default. This removes the biggest symbol -- vsnprintf_internal -- from the TPL and reduces the text segment by about 2 kiB. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* | ARM: rmobile: Update H2 StoutMarek Vasut2018-04-131-0/+3
| | | | | | | | | | | | | | | | | | | | The H2 Stout port was broken since some time. This patch updates the H2 Stout port to use modern frameworks, DM, DT probing, SPL and TPL for the preloading and puts it on par with the M2 Porter board. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* | ARM: rmobile: Enable SCIFA0 early on H2 StoutMarek Vasut2018-04-131-0/+4
| | | | | | | | | | | | | | | | The H2 Stout uses SCIFA0 for serial console, make sure it is available very early on when probing from DT. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* | vxworks: fixed cpu enable using PSCI on armv8Vasyl Vavrychuk2018-04-131-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Without armv8_setup_psci register VBAR_EL3 is not set up property which makes SMC calls jump to invalid location. smp_kick_all_cpus is required to make slave cpus leave gic_wait_for_interrupt. Without this they will never pursue booting process. Fix was applied to the two ways of booting VxWorks: bootvx and bootm commands. This implementation is very similar to what is done in boot_jump_linux in arch/arm/lib/bootm.c file. Tested on VxWorks 7 release SR0520 2017-12-08 Intel Stratix 10 SX SoC Development Kit board. Signed-off-by: Vasyl Vavrychuk <vasyl.vavrychuk@globallogic.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | ARM: rmobile: Fix the memory map on Gen3Marek Vasut2018-04-113-87/+9
| | | | | | | | | | | | | | | | | | Fix up the memory map on Gen3 to match datasheet properly. This simplifies the memory map setup as well, since we do no longer need this massive complexity. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* | ARM: rmobile: Add JTAG recovery support for M2 PorterMarek Vasut2018-04-111-0/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add JTAG recovery support into the M2 Porter TPL. This allows the TPL to be loaded over JTAG, initialize the system, wait for the JTAG debugger to load U-Boot image into RAM and then resume and start U-Boot from RAM. The procedure is as follows: 1) Load u-boot-tpl.bin to 0xe6300000 2) Write magic number 0x1337c0de to 0xe6300020 TPL checks for this particular magic and starts JTAG recovery if this number is present. This is not present by default. 3) Start U-Boot TPL from 0xe6300000 4) Wait for a message from TPL on UART indicating JTAG boot: "JTAG boot detected!" 5) Halt the system in JTAG debugger 6) Load U-Boot image (u-boot.img) to 0x4fffffc0 7) Write magic number 0xb33fc0de to 0xe6300024 TPL checks for this particular magic to verify that the U-Boot image was loaded into DRAM by the JTAG debugger. 8) Resume the system in JTAG debugger Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* | ARM: rmobile: Add TPL support on R8A7791 M2 PorterMarek Vasut2018-04-111-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add and enable TPL on M2 Porter. The TPL must fit into 16 kiB due to the Gen2 BootROM restriction. The TPL is running from MERAM and is capable of performing the initial initialization of PFC, Clock, GPIO, LBSC, DBSC and QSPI NOR. DBSC is responsible for bringing up the DDR DRAM access. The TPL is capable of loading the next stage, U-Boot, from either SPI NOR or UART as a fallback. If either does provide a valid U-Boot uImage, the system stops, which allows the operator to load U-Boot ie. via JTAG and start it manually. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* | ARM: rmobile: Do not init caches in TPL before DRAMMarek Vasut2018-04-111-0/+2
| | | | | | | | | | | | | | | | Skip the cache initialization, which can be done later on in U-Boot proper, since this interferes with early DRAM initialization in TPL. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* | ARM: Fix Makefile during SPL and TPL buildMarek Vasut2018-04-111-2/+2
| | | | | | | | | | | | | | | | | | | | The tiny variants of memset and memcpy implementations can be built for TPL as well, check whether a TPL build is in progress and avoid including the default variants. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com>
* | clk: add sandbox test for bulk APINeil Armstrong2018-04-101-0/+32
| | | | | | | | | | | | | | | | | | | | This patch adds the bulk clock API tests for the sandbox test suite. It's very similar to the main test but only uses the _bulk() API and checks if the clocks are correctly enabled/disabled. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | reset: add sandbox test for bulk APINeil Armstrong2018-04-101-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the bulk reset API tests for the sandbox test suite. Unlike the main test, it also check the "other" reset signal using the bulk API and checks if the resets are correctly asserted/deasserted. To allow the bulk API to work, and avoid changing the DT, the number of resets of the sandbox reset controller has been bumped to 101 for the "other" reset line to be valid. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | armv7m: disable icache before linux bootingPatrice Chotard2018-04-101-0/+3
| | | | | | | | | | | | | | | | Similarly to ARMV7, on ARMV7M instruction cache memory needs to be disabled before running linux kernel to avoid kernel to be stuck. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
* | Merge tag 'xilinx-for-v2018.05-rc2' of git://git.denx.de/u-boot-microblazeTom Rini2018-04-0932-710/+2614
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Xilinx changes for v2018.05-rc2 - Various DT changes and sync with mainline kernel - Various defconfig updates - Add SPL init for zcu102 revA - Add new zynqmp boards zcu100/zcu104/zcu106/zcu111/zc12XX and zc1751-dc3 - Net fixes - xlnx,phy-type - 64bit axi ethernet support - arasan: Fix nand write issue - fpga fixes - Maintainer file updates
| * | arm64: zynqmp: Add support for Xilinx zcu111-revAMichal Simek2018-04-092-0/+526
| | | | | | | | | | | | | | | | | | Xilinx zcu111 is a customer board. It is reusing some parts from zcu102. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | arm64: zynqmp: Add support for Xilinx zcu106-revAMichal Simek2018-04-092-0/+597
| | | | | | | | | | | | | | | | | | Xilinx zcu106 is a customer board. It is reusing some parts from zcu102. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | arm64: zynqmp: Add support for zcu104 customer boardMichal Simek2018-04-093-0/+533
| | | | | | | | | | | | | | | | | | | | | Xilinx zcu104 is another customer board. It is sort of zcu102 clone with some differences. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | arm64: zynqmp: Add support for zc12xx boardsMichal Simek2018-04-094-0/+234
| | | | | | | | | | | | | | | | | | | | | Add support for zc12xx boards. All of them are internal boards for silicon validation and share very similar base platforms. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | arm64: zynqmp: Add support for zc1751 dc3Michal Simek2018-04-092-0/+211
| | | | | | | | | | | | | | | | | | | | | zc1751 is based board with dc3 extenstion card which is used for silicon validation. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | arm64: zynqmp: Add support for zcu100 aka Ultra96 boardMichal Simek2018-04-092-0/+344
| | | | | | | | | | | | | | | | | | Add support for Xilinx zcu100. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | arm64: zynqmp: Get 200MHz clock early for MMCMichal Simek2018-04-091-0/+1
| | | | | | | | | | | | | | | | | | SPL MMC boot requires to have clock early. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | arm64: zynqmp: Remove pinctrl settingsMichal Simek2018-04-091-288/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | This part hasn't been pushed to mainline yet that's why remove it. The patch can be reverted in future when this is pushed there. Reported-by: Alexander Graf <agraf@suse.de> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Alexander Graf <agraf@suse.de>
| * | arm64: zynqmp: Remove power domain descriptionMichal Simek2018-04-091-194/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | This part hasn't been pushed to mainline yet that's why remove it. The patch can be reverted in future when this is pushed there. Reported-by: Alexander Graf <agraf@suse.de> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Alexander Graf <agraf@suse.de>
| * | fpga: zynqmp: Update zynqmp_load() as per latest xilfpgaSiva Durga Prasad Paladugu2018-04-091-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Latest xilfpga expects to set BIT5 of flags for nonsecure bitsream and also expects length in bytes instead of words This patch does the same. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
| * | arm: zynq: Use fixed partitions for spi flash for zc770 xm010Michal Simek2018-04-091-6/+9
| | | | | | | | | | | | | | | | | | Sync with mainline. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | arm: zynq: Fix eeprom dt nodesMichal Simek2018-04-094-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | - Use eeprom for node name - Use atmel compatible string instead of at. - Add missing labels Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | ARM: dts: zynq: Add generic compatible string for I2C EEPROMJavier Martinez Canillas2018-04-092-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The at24 driver allows to register I2C EEPROM chips using different vendor and devices, but the I2C subsystem does not take the vendor into account when matching using the I2C table since it only has device entries. But when matching using an OF table, both the vendor and device has to be taken into account so the driver defines only a set of compatible strings using the "atmel" vendor as a generic fallback for compatible I2C devices. So add this generic fallback to the device node compatible string to make the device to match the driver using the OF device ID table. Signed-off-by: Javier Martinez Canillas <javier@dowhile0.org> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | arm: zynq: Use i2c-mux instead of i2cswitch for pca9548Michal Simek2018-04-092-2/+2
| | | | | | | | | | | | | | | | | | i2c muxes should described like this. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | arm: zynq: Sync up licenses with mainline kernelMichal Simek2018-04-099-30/+13
| | | | | | | | | | | | | | | | | | | | | Use different location for SPDX line. Also update dates for new mainline DTS files. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | arm: zynq: Remove 0x prefixes from cc108Michal Simek2018-04-091-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The patch fixing issues reported by DTC: zynq-cc108.dtb: Warning (unit_address_format): Node /amba/spi@e000d000/flash@0/partition@0x400000 unit name should not have leading "0x" zynq-cc108.dtb: Warning (unit_address_format): Node /amba/spi@e000d000/flash@0/partition@0x800000 unit name should not have leading "0x" zynq-cc108.dtb: Warning (unit_address_format): Node /amba/spi@e000d000/flash@0/partition@0xc00000 unit name should not have leading "0x" zynq-cc108.dtb: Warning (unit_address_format): Node /amba/spi@e000d000/flash@0/partition@0xd00000 unit name should not have leading "0x" zynq-cc108.dtb: Warning (unit_address_format): Node /amba/spi@e000d000/flash@0/partition@0xf00000 unit name should not have leading "0x" Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | arm64: zynqmp: Remove double spaces from dts fileMichal Simek2018-04-091-1/+1
| | | | | | | | | | | | | | | | | | There is no reason to have double spaces for indentation. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | arm64: zynqmp: Add silabs prefix to u69 for zcu102Michal Simek2018-04-091-1/+1
| | | | | | | | | | | | | | | | | | Add vendor prefix to si5341. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | arm64: zynqmp: Remove number from clock-generator node nameMichal Simek2018-04-091-4/+4
| | | | | | | | | | | | | | | | | | There shouldn't be a number appended based on spec. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | arm64: zynqmp: Remove u-boot commands from dts filesMichal Simek2018-04-091-16/+10
| | | | | | | | | | | | | | | | | | U-Boot commands shouldn't be the part of kernel DTS files. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
generated by cgit (git 2.34.1) at 2024-11-19 21:53:19 +0000