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* Merge tag 'mips-pull-2019-05-03' of git://git.denx.de/u-boot-mipsTom Rini2019-05-0423-316/+629
|\ | | | | | | | | | | - mscc: small fixes, enhance network support for Serval, Luton and Ocelot - mt7620: rename arch to more generic name mtmips - mips: pass initrd addresses via DT as physical addresses
| * net: mscc: ocelot: Update DTS for Luton pcb90Horatiu Vultur2019-05-033-196/+290
| | | | | | | | | | | | | | | | Update device tree for luton to add support for luton pcb90. This pcb has 24 ports from which 12 ports are connected to SerDes6G. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
| * mips: rename mach-mt7620 to mach-mtmipsWeijie Gao2019-05-039-12/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently mach-mt7620 contains only support for mt7628. To avoid confusion, rename mach-mt7620 to mach-mtmips, which means MediaTek MIPS platforms. MT7620 and MT7628 should be distinguished by SOC_MT7620 and SOC_MT7628 because they do not share the same lowlevel codes. Dependencies of four drivers are changed to SOC_MT7628 as these drivers are only used by MT7628. Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * net: mscc: ocelot: Update DTS for Ocelot pcb120.Horatiu Vultur2019-05-033-81/+147
| | | | | | | | | | | | Update device tree for ocelot to add support for ocelot pcb120. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
| * net: mscc: ocelot: Update network driver for pcb120Horatiu Vultur2019-05-031-0/+1
| | | | | | | | | | | | Update Ocelot network driver to have support also for pcb120. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
| * arch: mips: Update initrd_start and initrd_endHoratiu Vultur2019-05-031-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Microsemi SoC defines CONFIG_SYS_SDRAM_BASE to be 0x80000000, which represents the start of kseg0 and represents a virtual address. Meaning that the initrd_start and initrd_end point somewhere kseg0. When these parameters are passed to linux kernel through DT they are pointing somewhere in kseg0 which is a virtual address but linux kernel expects the addresses to be physical addresses(in kuseg) because it is converting the physical address to a virtual one. Therefore update the uboot to pass the physical address of initrd_start and initrd_end by converting them using the function virt_to_phys before setting up the DT. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * MSCC: delete obsolete reference to MSCC_BITBANG_SPI_GPIORobert P. J. Day2019-05-031-1/+0
| | | | | | | | | | | | | | | | | | | | | | Remove "select MSCC_BITBANG_SPI_GPIO" since Kbuild option was deleted back in commit ace9c103df2875d2b435dbd7b36618020edfd1c0: commit ace9c103df2875d2b435dbd7b36618020edfd1c0 Author: Lars Povlsen <lars.povlsen@microchip.com> Date: Tue Jan 8 10:38:35 2019 +0100 mips: gpio: mscc: Obsoleted gpio-mscc-bitbang-spi.c
| * net: mscc: serval: Add ethernet nodes for ServalHoratiu Vultur2019-05-033-0/+146
| | | | | | | | | | | | | | Add ethernet nodes for Serval SoCs family. There are 2 pcb in this family: pcb105 and pcb106. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
| * mips: mscc: serval: Fix resetHoratiu Vultur2019-05-032-26/+31
| | | | | | | | | | | | | | | | | | In case the ddr training was failing, it couldn't reset, it was just hanging. Therefore reimplement it, so when ddr training is failing it would call _machine_restart, which power downs the DDR and does a force reset. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
* | delete Kbuild "select" of long-dead SPL_DISABLE_OF_CONTROLRobert P. J. Day2019-05-041-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | >From way back in 2015: commit dffb86e468c8e02ba77283989aefef214d904dc5 Author: Masahiro Yamada <yamada.masahiro@socionext.com> Date: Wed Aug 12 07:31:54 2015 +0900 of: flip CONFIG_SPL_DISABLE_OF_CONTROL into CONFIG_SPL_OF_CONTROL As we discussed a couple of times, negative CONFIG options make our life difficult; CONFIG_SYS_NO_FLASH, CONFIG_SYS_DCACHE_OFF, ... and here is another one. Now, there are three boards enabling OF_CONTROL on SPL: - socfpga_arria5_defconfig - socfpga_cyclone5_defconfig - socfpga_socrates_defconfig This commit adds CONFIG_SPL_OF_CONTROL for them and deletes CONFIG_SPL_DISABLE_OF_CONTROL from the other boards to invert the logic. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | arm: davinci: remove leftover code for dm* SoCsBartosz Golaszewski2019-05-0415-1133/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | The support for DaVinci DM* SoCs has been dropped a while ago. There's still a lot of leftover code in mach-davinci though. Entirely remove certain files and modify the common code to no longer reference unsupported chips. Note: all DaVinci platforms supported in u-boot now define SOC_DA8XX but not all define SOC_DA850 (e.g. omapl138). We can safely remove all ifdefs for the former, but let's leave the ones for the latter. Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
* | arm: davinci: remove dead code for PHYs used by DaVinci DM* boardsBartosz Golaszewski2019-05-046-354/+0
| | | | | | | | | | | | | | | | The support for DaVinci DM* boards has been dropped a while ago. The code for all those PHYs is no longer used and they have their own proper PHY drivers in drivers/net/phy anyway. Remove all dead code. Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
* | Merge git://git.denx.de/u-boot-socfpgaTom Rini2019-05-039-48/+54
|\ \ | | | | | | | | | - Misc MMC, FPGA bridge, general SoCFPGA fixes
| * | dts: arm: socfpga: fix socfpga_de10_nano consoleSimon Goldschmidt2019-04-291-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Booting this board failed as the initial console isn't found since commit c402e8170245 ("dts: arm: socfpga: merge gen5 devicetrees from linux") The uart0 devicetree entry was missing "clock-frequency = <100000000>:" since that commit Fixes: c402e8170245 ("dts: arm: socfpga: merge gen5 devicetrees from linux") Reported-by: rafael mello <rafaelmello_3@hotmail.com> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
| * | ARM: socfpga: Remove socfpga_sdram_apply_static_cfg()Marek Vasut2019-04-291-31/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The usage of socfpga_sdram_apply_static_cfg() seems rather dubious and is confirmed to lead to a rare system hang when enabling bridges. This patch removes the socfpga_sdram_apply_static_cfg() altogether, because it's use seems unjustified and problematic. The socfpga_sdram_apply_static_cfg() triggers write to SDRAM staticcfg register to set the applycfg bit, which according to old vendor U-Boot sources can only be written when there is no traffic between the SDRAM controller and the rest of the system. Empirical measurements confirm this, setting the applycfg bit when there is traffic between the SDRAM controller and CPU leads to the SDRAM controller accesses being blocked shortly after. Altera originally solved this by moving the entire code which sets the staticcfg register to OCRAM [1]. The commit message claims that the applycfg bit needs to be set after write to fpgaportrst register. This is however inverted by Altera shortly after in [2], where the order becomes the exact opposite of what commit message [1] claims to be the required order. The explanation points to a possible problem in AMP use-case, where the FPGA might be sending transactions through the F2S bridge. However, the AMP is only the tip of the iceberg here. Any of the other L2, L3 or L4 masters can trigger transactions to the SDRAM. It becomes rather non-trivial to guarantee there are no transactions to the SDRAM controller. The SoCFPGA SDRAM driver always writes the applycfg bit in SPL. Thus, writing the applycfg again in bridge enable code seems redundant and can presumably be dropped. [1] https://github.com/altera-opensource/u-boot-socfpga/commit/75905816ec95b0ccd515700b922628d7aa9036f8 [2] https://github.com/altera-opensource/u-boot-socfpga/commit/8ba6986b04a91d23c7adf529186b34c8d2967ad5 Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
| * | ARM: socfpga: Add support for selecting bridges in bridge commandMarek Vasut2019-04-295-10/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add optional "mask" argument to the SoCFPGA bridge command, to select which bridges should be enabled/disabled. This allows the user to avoid enabling bridges which are not connected into the FPGA fabric. Default behavior is to enable/disable all bridges. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
| * | ARM: socfpga: Fully unmap the FPGA bridges from L3 spaceMarek Vasut2019-04-291-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of just putting the bridges into reset, fully remove the bridges from the L3 main bridge space when disabling them by clearing bits in NIC-301 remap register. Moreover, only touch the 3 LSbits in brgmodrst register as the rest of the bits are undefined. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
| * | ARM: socfpga: Disable bridges in SPL unless booting from FPGAMarek Vasut2019-04-291-5/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Disable bridges between L3 Main switch and FPGA unless booting from FPGA and keep them disabled to prevent glitches and possible hangs of the L3 Main switch. The current version of the code could have enabled the bridges between the L3 Main switch and FPGA for a short period of time in board_init_f() in case the FPGA was programmed and then again disable them at the end of board_init_f(). Replace this with a code which only sets up the handoff registers and let the user enable the bridges later on. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
| * | ARM: socfpga: Factor out handoff register configurationMarek Vasut2019-04-292-2/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Factor out the code for programming preloader handoff register values, the ISWGRP Handoff 0 and 1. These registers later control which bridges are enabled by the "bridge" command on Gen5 devices. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
* | | Merge git://git.denx.de/u-boot-usbTom Rini2019-05-031-3/+0
|\ \ \ | | | | | | | | | | | | - DaVinci updates
| * | | ARM: davinci: Remove unused functions from headerAdam Ford2019-05-031-3/+0
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | There are a few functions defined in the header file, but they are not referenced by any Davinci code. In order to make a general function in the future with static function declarations, this patch will remove the references all together. Signed-off-by: Adam Ford <aford173@gmail.com>
* | | Merge git://git.denx.de/u-boot-marvellTom Rini2019-05-031-0/+7
|\ \ \ | | | | | | | | | | | | | | | | - Fix in kwbimage (return code checking) (Young Xiao) - Misc updates to Turris Omnia (Marek)
| * | | arm: mvebu: turris_omnia: add RESET button handlingMarek Behún2019-05-031-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is a Factory RESET button on the back side of the Turris Omnia router. When user presses this button before powering the device up and keeps it pressed, the microcontroller prevents the main CPU from booting and counts how long the RESET button is being pressed (and indicates this by lighting up front LEDs). The idea behind this is that the user can boot the device into several Factory RESET modes. This patch adds support for U-Boot to read into which Factory RESET mode the user booted the device. The value is an integer stored into the omnia_reset environment variable. It is 0 if the button was not pressed at all during power up, otherwise it is the number identifying the Factory RESET mode. This patch also changes bootcmd to a special hardcoded value if Factory RESET button was pressed during device powerup. This special bootcmd value sets the colors of all the LEDs on the front panel to green and then tries to load the rescue image from the SPI flash memory and boot it. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
| * | | arm: mvebu: turris_omnia: move ATSHA204A from defconfig to KconfigMarek Behún2019-05-031-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This driver is required for Turris Omnia to read ethernet addresses. Move the dependency from turris_omnia_defconfig to Kconfig. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
| * | | arm: mvebu: turris_omnia: move I2C dependencies to KconfigMarek Behún2019-05-031-0/+5
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The I2C dependencies are defined in include/configs/turris_omnia.h, because Turris Omnia won't boot correctly without I2C support. Move these dependencies to Kconfig, so that they are selected if Turris Omnia is selected as target. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
* | | Merge branch '2019-05-03-master-imports'Tom Rini2019-05-037-112/+472
|\ \ \ | | | | | | | | | | | | | | | | | | | | - Various btrfs fixes - Various TI platform fixes - Other fixes (cross build, taurus update, Kconfig help text)
| * | | ARM: dts: logicpd-som-lv: Fix MMC1 card detectAdam Ford2019-05-031-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The card detect pin was incorrectly using IRQ_TYPE_LEVEL_LOW instead of GPIO_ACTIVE_LOW when reading the state of the CD pin. Without this patch, MMC1 won't be detected. This is the same patch submitted to linux-omap, but I was hoping to get it applied to U-Boot without having to wait for the linux adoption and then backporting. Fixes: 5448ff33f281 ("ARM: DTS: Resync Logic PD SOM-LV 37xx devkit with Linux 4.18-RC4") Signed-off-by: Adam Ford <aford173@gmail.com>
| * | | ti: Add device-tree for am335x-pocketbeagle.Vagrant Cascadian2019-05-033-0/+362
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add device-tree files from linux 5.1-rc7 needed to complete support for PocketBeagle. Signed-off-by: Vagrant Cascadian <vagrant@debian.org> Reviewed-by: Tom Rini <trini@konsulko.com>
| * | | arm: dts: k3-am654: Sync IOPAD macros with LinuxAndreas Dannenberg2019-05-032-29/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Transition to the IOPAD macros as used in Linux in which the pin mux mode is specified using a dedicated parameter while also dropping the related MUX_MODEx macros that are no longer needed. This transition will allow us to keep both Linux and U-Boot DTS in sync more easily. While at it also align the file name of the include file itself and update any references accordingly. Signed-off-by: Andreas Dannenberg <dannenberg@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
| * | | at91: cleanup taurus portHeiko Schocher2019-05-031-80/+78
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - at91sam9g20-taurus.dts: use labels - cleanup taurus port to compile clean with current mainline again. SPL has no serial output anymore, so it fits into SRAM. Signed-off-by: Heiko Schocher <hs@denx.de>
| * | | armv7R: dts: k3: am654: Switch DMSC TX message thread IDAndreas Dannenberg2019-05-031-1/+1
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Switch from using the high priority DMSC transmit message queue used by the secure R5 MCU island boot context to the low priority message queue. While the change in priority is irrelevant for the current boot architecture it however gives us access to a deeper message queue that will allow us to buffer more messages. This is an important aspect when sending several messages without requesting and waiting for a response in a row which is a communication scheme used during core shutdown for example. See AM654 TISCI User Guide for additional details. Signed-off-by: Andreas Dannenberg <dannenberg@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
* | | Merge tag 'rockchip-for-2019.07' of git://git.denx.de/u-boot-rockchipTom Rini2019-05-0171-376/+1287
|\ \ \ | |/ / |/| | | | | | | | | | | | | | | | | | | | | | | Improvements and new features: - improved SPI driver for better read throughput - refactors initialisation of debug UART init - restructures header file paths - adds pinctrl improvements Adds Kever as a co-custodian.
| * | rockchip: rk3288: include header for back_to_bootromPhilipp Tomsich2019-05-011-0/+1
| | | | | | | | | | | | | | | | | | | | | To avoid a warning, we need to include the header defining back_to_bootrom for us. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| * | rockchip: rk3399: include gpio.hPhilipp Tomsich2019-05-011-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | After applying the series for debug_uart_init(), Travis-CI reports: arch/arm/mach-rockchip/rk3399/rk3399.c:90:2: error: implicit declaration of function 'spl_gpio_set_pull' [-Werror=implicit-function-declaration] spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_B, 2), GPIO_PULL_NORMAL); ^~~~~~~~~~~~~~~~~ This is caused by a missing header-file include. Fix it. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| * | rockchip: rk3399: add board_debug_uart_init()Kever Yang2019-05-012-49/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use board_debug_uart_init() for UART iomux init instead of do it in board_init_f, and move the function to soc file so that we can find all the soc/board setting in soc file and use a common board file for all rockchip SoCs later. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| * | rockchip: rk3399: use grf structure to access regKever Yang2019-05-011-1/+4
| | | | | | | | | | | | | | | | | | | | | Prefer to use structure to access register if we could. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| * | rockchip: rk3368: move board_debug_uart_init() to rk3368.cKever Yang2019-05-013-40/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | Move the function to soc file so that we can find all the soc/board setting in soc file and use a common board file later for all rockchip SoCs. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| * | rockchip: rk3288: add board_debug_uart_init()Kever Yang2019-05-013-24/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use board_debug_uart_init() for UART iomux init instead of do it in board_init_f, and move the function to soc file so that we can find all the soc/board setting in soc file and use a common board file for all rockchip SoCs later. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| * | rockchip: rk3288: use grf structure to access soc_con2Kever Yang2019-05-011-2/+4
| | | | | | | | | | | | | | | | | | | | | Prefer to use structure to access register if we can. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| * | rockchip: rk322x: move board_debug_uart_init() to rk322x.cKever Yang2019-05-014-72/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the function to soc file so that we can find all the soc/board setting in soc file and use a common board file later for all rockchip SoCs. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> [Fixed up header-list to not break FASTBOOT:] Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| * | rockchip: rk3188: add board_debug_uart_init()Kever Yang2019-05-013-27/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use board_debug_uart_init() for UART iomux init instead of do it in board_init_f, and move the function to soc file so that we can find all the soc/board setting in soc file and use a common board file. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| * | rockchip: rk3036: add board_debug_uart_init()Kever Yang2019-05-013-19/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use board_debug_uart_init() for UART iomux init instead of do it in board_init_f, and move the function to soc file so that we can find all the soc/board setting in soc file and use a common board file. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> [Fixed whitespace error:] Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| * | rockchip: enable DEBUG_UART_BOARD_INIT by defaultKever Yang2019-05-012-4/+1
| | | | | | | | | | | | | | | | | | | | | | | | All Rockchip SoCs use DEBUG_UART_BOARD_INIT to init per board UART IOMUX, enable it by default. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| * | rockchip: correct ARCH_SOC nameKever Yang2019-05-019-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ARCH_SOC name default as 'rockchip' and we put all the header file in 'arch/arm/include/asm/arch-rockchip/', but the 'rockchip' is not the SOC name, let's correct it after we update all the source file. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsiich <philipp.tomsich@theobroma-systems.com>
| * | rockchip: use 'arch-rockchip' as header file pathKever Yang2019-05-0143-127/+128
| | | | | | | | | | | | | | | | | | | | | | | | Rockchip use 'arch-rockchip' instead of arch-$(SOC) as common header file path, so that we can get the correct path directly. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| * | rockchip: arm: use 'arch-rockchip' for common headerKever Yang2019-05-013-2/+9
| | | | | | | | | | | | | | | | | | | | | | | | rockchip platform header file is in 'arch-rockchip' instead of arch-$(SOC) for all SoCs. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| * | rockchip: arm: remove no use macroKever Yang2019-05-011-2/+0
| | | | | | | | | | | | | | | | | | | | | TIMER7_BASE is no used by source code now, remove it. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| * | rk3288-board: remove pinctrl call for debug uartUrja Rannikko2019-05-011-12/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | This failed and caused a boot failure on c201, and afaik the pins should be setup by the new pinctrl driver. Signed-off-by: Urja Rannikko <urjaman@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| * | rockchip: rk3399: Add Orangepi RK3399 supportJagan Teki2019-05-013-0/+779
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add initial support for Orangepi RK3399 board. Specification - Rockchip RK3399 - 2GB/4GB DDR3 - 16GB eMMC - SD card slot - RTL8211E 1Gbps - AP6356S WiFI/BT - HDMI In/Out, DP, MIPI DSI/CSI - Mini PCIe - Sensors, Keys etc - DC12V-2A and DC5V-2A Commit details about Linux DTS sync: "arm64: dts: rockchip: Add support for the Orange Pi RK3399" (sha1: d3e71487a790979057c0fdbf32f85033639c16e6) Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| * | rockchip: dts: rk3399: Create initial rk3399-u-boot.dtsiJagan Teki2019-05-014-3/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | u-boot,dm-pre-reloc is required for SDMMC booted rk3399 boards and which is U-Boot specific devicetrees binding. Move it on global rk3399-u-boot.dtsi file and rest of the U-Boot bindings will move it future based on the requirement. This would help to sync the devicetrees from Linux whenever required instead of adding specific nodes. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
generated by cgit (git 2.34.1) at 2024-11-19 15:33:01 +0000