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* riscv: add support for multi-hart systemsLukas Auer2019-04-085-2/+147
| | | | | | | | | | | | | | | | | | On RISC-V, all harts boot independently. To be able to run on a multi-hart system, U-Boot must be extended with the functionality to manage all harts in the system. All harts entering U-Boot are registered in the available_harts mask stored in global data. A hart lottery system as used in the Linux kernel selects the hart U-Boot runs on. All other harts are halted. U-Boot can delegate functions to them using smp_call_function(). Every hart has a valid pointer to the global data structure and a 8KiB stack by default. The stack size is set with CONFIG_STACK_SIZE_SHIFT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* riscv: save hart ID in register tp instead of s0Lukas Auer2019-04-081-2/+2
| | | | | | | | | | | | | The hart ID passed by the previous boot stage is currently stored in register s0. If we divert the control flow inside a function, which is required as part of multi-hart support, the function epilog may not be called, clobbering register s0. Save the hart ID in the unallocatable register tp instead to protect the hart ID. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
* riscv: delay initialization of caches and debug UARTLukas Auer2019-04-081-8/+8
| | | | | | | | | | | | Move the initialization of the caches and the debug UART until after board_init_f_init_reserve. This is in preparation for SMP support, where code prior to this point will be executed by all harts. This ensures that initialization will only be performed once on the main hart running U-Boot. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* riscv: implement IPI platform functions using SBILukas Auer2019-04-083-0/+31
| | | | | | | | | | | | | | | | The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* riscv: import the supervisor binary interface header fileLukas Auer2019-04-081-0/+94
| | | | | | | | | | | Import the supervisor binary interface (SBI) header file from Linux (arch/riscv/include/asm/sbi.h). The last change to it was in commit 6d60b6ee0c97 ("RISC-V: Device, timer, IRQs, and the SBI"). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
* riscv: add infrastructure for calling functions on other hartsLukas Auer2019-04-085-0/+197
| | | | | | | | | | | | | | | | | | | | | | | | Harts on RISC-V boot independently, U-Boot is responsible for managing them. Functions are called on other harts with smp_call_function(), which sends inter-processor interrupts (IPIs) to all other available harts. Available harts are those marked as available in the device tree and present in the available_harts mask stored in global data. The available_harts mask is used to register all harts that have entered U-Boot. Functions are specified with their address and two function arguments (argument 2 and 3). The first function argument is always the hart ID of the hart calling the function. On the other harts, the IPI interrupt handler handle_ipi() must be called on software interrupts to handle the request and call the specified function. Functions are stored in the ipi_data data structure. Every hart has its own data structure in global data. While this is not required at the moment (all harts are expected to boot Linux), this does allow future expansion, where other harts may be used for monitoring or other tasks. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* Merge tag 'u-boot-imx-20190405' of git://git.denx.de/u-boot-imxTom Rini2019-04-051-1/+1
|\ | | | | | | | | | | | | | | Fixes for 2019.04 - fix bashism for MX8 - fix ethernet for MX53 - fix docs for i.MX8
| * DTS: Fix ETH PHY reset on HSC|DDC boards (imx53)Lukasz Majewski2019-04-021-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | After the commit: "eth: dm: fec: Add gpio phy reset binding" SHA1: efd0b791069af93e9d439a70d1fe2ae8994dbbfa The FEC ETH driver switched to PHY GPIO reset performed with data defined in DTS. For the HSC|DDC boards the GPIO reset signal is active low and hence the wrong DTS description must be changed (otherwise the reset for ETH is not properly setup). Signed-off-by: Lukasz Majewski <lukma@denx.de>
* | Merge branch 'master' of git://git.denx.de/u-boot-shTom Rini2019-04-011-0/+5
|\ \ | | | | | | | | | Minor fixes for the Alt board and PHY use on Gen2.
| * | ARM: dts: rmobile: Activate I2C7 on AltMarek Vasut2019-03-301-0/+5
| |/ | | | | | | | | | | | | Activate I2C7 on Alt to allow access to the PMIC. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* / Revert "rockchip: Drop call to rockchip_dnl_mode_check() for now"Philipp Tomsich2019-03-291-7/+1
|/ | | | | | | | Due to a final resolution not coming up in time for 2019.04 and following the consensus on the discussion, we'll keep this around for 2019.04 after all. This reverts commit 0d968ceb1ff63b0d220a571f438f0d5fe6350e88.
* Merge branch 'master' of git://git.denx.de/u-boot-shTom Rini2019-03-266-0/+34
|\ | | | | | | - Various fixes for bugs found by u-boot test.py
| * ARM: dts: rmobile: Increase off-on delay on the SD Vcc regulatorMarek Vasut2019-03-256-0/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | An ADATA 16GB Industrial MLC card has so much capacitance on the Vcc pin that the usual toggling of regulator to power the card off and on is insufficient. When the card is calibrated into UHS SDR104 mode, it will remain in that mode across the power cycle and subsequent attempt to communicate with the card will fail. The test with this card is to insert it into an SDHI slot and perform "mmc dev 0 ; mmc dev 0", where the second "mmc dev 0" will fail. Fix this problem by increasing the off-on delay from 0 to 20 mS. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* | Convert CONFIG_ENV_SPI_* to KconfigPatrick Delaunay2019-03-252-30/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This converts the following to Kconfig: CONFIG_ENV_SPI_BUS CONFIG_ENV_SPI_CS CONFIG_ENV_SPI_MAX_HZ CONFIG_ENV_SPI_MODE Most of time these value are not needed, CONFIG_SF_DEFAULT with same value is used, so I introduced CONFIG_USE_ENV_SPI_* to force the associated value for the environment. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
* | exynos: replace CONFIG_ENV_SPI_BASE by CONFIG_SYS_SPI_BASEPatrick Delaunay2019-03-251-1/+1
|/ | | | | | | | | Replace CONFIG_ENV_SPI_BASE by the better CONFIG_SYS_SPI_BASE (it is not the location for environment but the location for U-Boot) and, as it is the only platform with use this define, remove it from whitelist. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
* mips: add missing dtb-y to arch/mips/dts/MakefileMasahiro Yamada2019-03-221-0/+5
| | | | | | | | | | | | | | Since commit 27cb7300ffda ("Ensure device tree DTS is compiled"), build succeeds irrespective of the correctness of Makefile. In fact, you can compile any defconfig without adding any entry in arch/*/dts/Makefile. I am going to revert that commit, so device tree must be explicitly listed in Makefile. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* powerpc: fix arch/powerpc/dts/MakefileMasahiro Yamada2019-03-221-1/+1
| | | | | | | | | | | | Since commit 27cb7300ffda ("Ensure device tree DTS is compiled"), build succeeds irrespective of the correctness of Makefile. I am going to revert that commit, so wrong code must be fixed. CONFIG_MCR3000 is not defined anywhere. CONFIG_TARGET_MCR3000 is the correct one. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: fix arch/arm/dts/MakefileMasahiro Yamada2019-03-221-11/+100
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since commit 27cb7300ffda ("Ensure device tree DTS is compiled"), build succeeds irrespective of the correctness of Makefile. In fact, you can compile any defconfig without adding any entry in arch/*/dts/Makefile. As a result, a lot of wrong code have been merged unnoticed. I am going to revert that commit, and lots of hidden issues have come to light: [1] Typos armada-3720-uDPU.dts, sun8i-a83t-tbs-a711.dts use the extension ".dts" instead of ".dtb" [2] DTB is associated to undefined CONFIG option For example, mx6sllevk_defconfig defines CONFIG_MX6SLL, but associates its device tree to CONFIG_MX6SL, which is undefined. [3] Lots of entries are missing Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Chris Packham <judge.packham@gmail.com> [trini: add imx6ul pico dtbs] Signed-off-by: Tom Rini <trini@konsulko.com>
* armv8: Disable exception vectors in SPL by defaultAlexander Graf2019-03-222-3/+3
| | | | | | | | | | | | | | | | Commit 1416e2d2253 ("armv8: make SPL exception vectors optional") had a typo in it which effectively disabled exception handling in SPL code always. Since nobody complained, I guess we may as well disable exception handling in SPL always by default. So fix the bug to make the config option effective, but disable exception handling in SPL by default. This gets us to the same functionality as before by default, but with much less code included in the binary. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: Matthias Brugger <mbrugger@suse.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
* arm: lib: bootm: Push the Starting kernel print to the endKeerthy2019-03-221-2/+2
| | | | | | | | Push the Starting kernel print to the end just before the dm_remove_devices call. Signed-off-by: Keerthy <j-keerthy@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* Merge git://git.denx.de/u-boot-marvellTom Rini2019-03-197-5/+15
|\ | | | | | | | | | | | | | | | | | | | | | | - Enable network interface on clearfog_gt_8k (Baruch) - Fix dreamplug boot by adding an spi0 alias to the DT (Chris) - Fix / enhance Marvell ddr3 setup / parameters (Chris) - Change CONFIG_SYS_MALLOC_F_LEN to 0x2000 on db-88f6820-amc (Chris) - Enable SPL_FLASH_BAR on db-88f6820-amc (Chris) - Use correct pcie controller name in Armada-38x dts files (Chris) - Disable d-cache on Kirkwood platforms as currently needed (Chris) - Add a more descriptive comment to pci_mvebu.c (Stefan) - Update Marvell maintainers entry (Stefan)
| * ARM: kirkwood: disable dcache for Kirkwood boardsChris Packham2019-03-191-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | Prior to commit 93b283d49f93 ("ARM: CPU: arm926ejs: Consolidate cache routines to common file") the kirkwood boards didn't have and dcache support. The network and usb drivers rely on this. Set CONFIG_SYS_DCACHE_OFF in the Kirkwood specific config.h. Reported-by: Leigh Brown <leigh@solinno.co.uk> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
| * ARM: mvebu: use correct name for pcie controllerChris Packham2019-03-195-5/+5
| | | | | | | | | | | | | | | | | | | | | | When armada-385.dtsi was sync'd from Linux the name of the node describing the pcie controller was changed from pcie-controller to pcie. Some of the boards that include armada-385.dtsi were missed in the update retaining the old name. This updates the affected boards. Reported-by: Влад Мао <vlaomao@gmail.com> Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * ARM: kirkwood: add spi0 alias for dreamplugChris Packham2019-03-191-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | The conversion to DM_SPI managed to break accessing the environment on dreamplug. This is because the environment code relies on being to able to select the SPI device based on the sequence number. Add an alias so that the spi0 bus gets sequence number 0. Reported-by: Leigh Brown <leigh@solinno.co.uk> Signed-off-by: Chris Packham <judge.packham@gmail.com> Tested-by: Leigh Brown <leigh@solinno.co.uk> Signed-off-by: Stefan Roese <sr@denx.de>
* | Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini2019-03-191-0/+3
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| * ARM: dts: socfpga: Add missing altr,sysmgr-syscon for EMACLey Foon Tan2019-03-161-0/+3
| | | | | | | | | | | | | | | | | | | | | | Syscon register is required in dts to select correct PHY interface. Fix error below: Net: Failed to get syscon: -2 Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
* | Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini2019-03-153-7/+45
|\ \ | |/ |/| | | - DPAA2 fixes and DDR errata workaround for LS1021A
| * armv7: ls102xa: Add workaround for DDR erratum A-008850Alison Wang2019-03-153-7/+45
| | | | | | | | | | | | | | | | | | | | Barrier transactions from CCI400 need to be disabled till the DDR is configured, otherwise it may lead to system hang. The patch adds workaround to fix the erratum. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-samsungTom Rini2019-03-141-1/+21
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| * arm: dts: exynos: Adjust whitespace around status propertyKrzysztof Kozlowski2019-03-111-1/+1
| | | | | | | | | | | | | | | | Just add spaces around '=' sign for clarity. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * arm: dts: exynos: Add ramp delay property to LDO regulators to Odroid XU3 familyKrzysztof Kozlowski2019-03-111-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add startup time to LDO regulators of S2MPS11 PMIC on Odroid XU3/XU4/HC1 family of boards to be sure the voltage is proper before relying on the regulator. The datasheet for all the S2MPS1x family is inconsistent here and does not specify unambiguously the value of ramp delay for LDO. It mentions 30 mV/us in one timing diagram but then omits it completely in LDO regulator characteristics table (it is specified for bucks). However the vendor kernels for Galaxy S5 and Odroid XU3 use values of 12 mV/us or 24 mV/us. Without the ramp delay value the consumers do not wait for voltage settle after changing it. Although the proper value of ramp delay for LDOs is unknown, it seems safer to use at least some value from reference kernel than to leave it unset. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Reviewed-by: Lukasz Majewski <lukma@denx.de> Tested-by: Anand Moon <linux.amoon@gmail.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * arm: dts: exynos: Add supply for ADC block to Odroid XU3 familyKrzysztof Kozlowski2019-03-111-0/+1
| | | | | | | | | | | | | | | | | | The ADC block requires VDD supply to be on so provide one. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Reviewed-by: Lukasz Majewski <lukma@denx.de> Tested-by: Anand Moon <linux.amoon@gmail.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | arm: dts: imx6qdl-u-boot: Enable spba-bus@2000000 simple busAdam Ford2019-03-131-0/+3
| | | | | | | | | | | | | | | | | | spba-bus has a few nodes under it including the UART1 and some ESPI buses. In order to use them in SPL, the u-boot,dm-spl flag needs to be added to the spba-bus@2000000 container. Signed-off-by: Adam Ford <aford173@gmail.com>
* | imx8qxp: Fix the reported CPU frequencyFabio Estevam2019-03-131-10/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently the CPU frequency is incorrectly reported: CPU: NXP i.MX8QXP RevB A35 at 147228 MHz Fix this problem by using a direct call to the SCU firmware to retrieve the Cortex A35 CPU frequency. With this change applied the CPU frequency is displayed correctly: CPU: NXP i.MX8QXP RevB A35 at 1200 MHz Tested-by: Marcelo Macedo <marcelo.macedo@nxp.com> Signed-off-by: Fabio Estevam <festevam@gmail.com> Tested-by: Andrejs Cainikovs <andrejs.cainikovs@netmodule.com>
* | pico-imx6ul: Convert to DM MMCFabio Estevam2019-03-131-0/+2
| | | | | | | | | | | | | | | | | | Select CONFIG_DM_MMC=y in order to support MMC driver model. This allows the MMC board related code to be removed. Signed-off-by: Fabio Estevam <festevam@gmail.com> Acked-by: Otavio Salvador <otavio@ossystems.com.br>
* | pico-imx6ul: Import dts files from kernelFabio Estevam2019-03-133-0/+658
| | | | | | | | | | | | | | | | Import the device tree files from kernel 5.0-rc6 in preparation for driver model conversion. Signed-off-by: Fabio Estevam <festevam@gmail.com> Acked-by: Otavio Salvador <otavio@ossystems.com.br>
* | Merge git://git.denx.de/u-boot-x86Tom Rini2019-03-117-5/+48
|\ \ | | | | | | | | | | | | - ACPI changes and fixes to Intel Tangier/Edison - i8254 beeper fixes
| * | x86: crownbay: Enable the beeper sound driverBin Meng2019-03-111-0/+1
| | | | | | | | | | | | | | | | | | | | | Use the i8254 sound driver to support creating simple beeps. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | x86: coreboot: Add the missing pc speaker node in the device treeBin Meng2019-03-111-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | This is currently missing and without it the i8254 beeper driver won't work. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | x86: Add a dtsi file for the pc speakerBin Meng2019-03-111-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | The pc speaker driven by the i8254 is generic enough to deserve a single dtsi file to be included by boards that use it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | x86: Make sure i8254 is setup correctly before generating beepsBin Meng2019-03-111-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The i8254 timer control IO port (0x43) should be setup correctly by using PIT counter 2 to generate beeps, however in U-Boot other codes like TSC driver utilizes PIT for TSC frequency calibration and configures the counter 2 to a different mode that does not beep. Fix this by always ensuring the PIT counter 2 is correctly initialized so that the i8254 beeper driver works as expected. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | x86: edison: Add the rest of UARTs present on boardAndy Shevchenko2019-03-101-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Intel Edison has three UART ports, i.e. port 0 - Bluetooth port 1 - auxiliary, available for general purpose use port 2 - debugging, usually console output is here Enable all of them for future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: edison: Use proper number of serial interfaceAndy Shevchenko2019-03-101-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The console is actually serial #2. When we would like to enable other ports, this would be not okay to mess up with the ordering. Thus, fix the number of default console interface to be 2. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: acpi: Not every platform has serial console a first deviceAndy Shevchenko2019-03-101-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We may not do an assumption that current console device is always a first of UCLASS_SERIAL one. For example, on properly described Intel Edison board the console UART is a third one. Use current serial device as described in global data. Fixes: a61cbad78e67 ("dm: serial: Adjust serial_getinfo() to use proper API") Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: acpi: Add DMA descriptors for I2C1 on Intel TangierAndy Shevchenko2019-03-101-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Intel Tangier SoC has a general purpose DMA which can serve to speed up communications on SPI and I2C serial buses. Provide DMA descriptors to utilize this capability in the future. Note, I2C6, which is available to user, has no DMA request lines connected. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: acpi: Add DMA descriptors for SPI5 on Intel TangierAndy Shevchenko2019-03-101-0/+3
| |/ | | | | | | | | | | | | | | | | | | Intel Tangier SoC has a general purpose DMA which can serve to speed up communications on SPI and I2C serial buses. Provide DMA descriptors to utilize this capability in the future. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini2019-03-102-2/+4
|\ \ | | | | | | | | | - Arria10 DRAM fixes and Gen5 cache fixes
| * | ARM: socfpga: Disable D cache in SPLMarek Vasut2019-03-091-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The bootrom seems to leave the D-cache in messed up state, make sure the SPL disables it so it can not interfere with operation. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
| * | ARM: socfpga: fix data and tag latency values for pl310 cache controllerDinh Nguyen2019-03-091-2/+2
| |/ | | | | | | | | | | | | | | | | | | The values for the data and tag latency settings on the PL310 caches controller is an (n-1). For example, the "arm,tag-latency" is specified as <1 1 1>, so the values that should be written to register should be 0x000. And for the "arm,data-latency" specified as <2 1 1>, the register value should be 0x010. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
* | ARM: dts: rmobile: Zap redundant USB/SDHI nodes on M3NEugeniu Rosca2019-03-091-99/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | v2019.01 commit cbff9f80cedd ("ARM: dts: rmobile: Sync Gen3 DTs with Linux 4.19.6") made the sdhi/usb nodes available in r8a77965.dtsi. Hence, remove the SDHI/USB nodes from r8a77965-u-boot.dtsi. This is equivalent to partially reverting below v2019.01 commits: - f529bc551b6d ("ARM: dts: rmobile: Extract USB nodes on M3N") - 830b94f76867 ("ARM: dts: rmobile: Extract SDHI nodes on M3N") Duplicating the nodes from <soc>.dtsi to <soc>-u-boot.dtsi is obviously: - not needed if no U-boot-specific changes are needed in those nodes. - potentially dangerous/error-prone, since the duplicated properties override the properties originally defined in <soc>.dtsi. One possible consequence is that <soc>.dtsi is getting an update from Linux, while <soc>-u-boot.dtsi stays unchanged. In this situation, the obsolete property values from <soc>-u-boot.dtsi will take precedence masking some of the <soc>.dtsi updates, potentially leading to all kind of obscure issues. Below is the dtdiff of r8a77965-salvator-x-u-boot.dtb (the only "user" of r8a77965-u-boot.dtsi) before and after the patch (slightly reformatted to avoid 'git am/apply' issues and to reduce the width). What below output means is there is already a mismatch in some of SDHI/USB nodes between r8a77965.dtsi and r8a77965-u-boot.dtsi. Since no U-Boot customization is needed in SDHI/USB DT nodes, get rid of them in r8a77965-u-boot.dtsi. $> dtdiff before-r8a77965-salvator-x-u-boot.dtb \ after-r8a77965-salvator-x-u-boot.dtb --- /dev/fd/63 2019-03-09 12:57:40.877963983 +0100 +++ /dev/fd/62 2019-03-09 12:57:40.877963983 +0100 @@ -1471,7 +1471,7 @@ bus-width = <0x4>; cd-gpios = <0x51 0xc 0x1>; clocks = <0x6 0x1 0x13a>; - compatible = "renesas,sdhi-r8a77965"; + compatible = "renesas,sdhi-r8a77965", "renesas,rcar-gen3-sdhi"; interrupts = <0x0 0xa5 0x4>; max-frequency = <0xc65d400>; pinctrl-0 = <0x4d>; @@ -1492,7 +1492,7 @@ sd@ee120000 { clocks = <0x6 0x1 0x139>; - compatible = "renesas,sdhi-r8a77965"; + compatible = "renesas,sdhi-r8a77965", "renesas,rcar-gen3-sdhi"; interrupts = <0x0 0xa6 0x4>; max-frequency = <0xbebc200>; power-domains = <0x1 0x20>; @@ -1504,7 +1504,7 @@ sd@ee140000 { bus-width = <0x8>; clocks = <0x6 0x1 0x138>; - compatible = "renesas,sdhi-r8a77965"; + compatible = "renesas,sdhi-r8a77965", "renesas,rcar-gen3-sdhi"; fixed-emmc-driver-type = <0x1>; interrupts = <0x0 0xa7 0x4>; max-frequency = <0xbebc200>; @@ -1526,7 +1526,7 @@ bus-width = <0x4>; cd-gpios = <0x5a 0xf 0x1>; clocks = <0x6 0x1 0x137>; - compatible = "renesas,sdhi-r8a77965"; + compatible = "renesas,sdhi-r8a77965", "renesas,rcar-gen3-sdhi"; interrupts = <0x0 0xa8 0x4>; max-frequency = <0xc65d400>; pinctrl-0 = <0x56>; @@ -1868,14 +1868,14 @@ usb-phy@ee0a0200 { #phy-cells = <0x0>; - clocks = <0x6 0x1 0x2be>; + clocks = <0x6 0x1 0x2bf>; compatible = "renesas,usb2-phy-r8a77965", "renesas,rcar-gen3-usb2-phy"; phandle = <0x47>; pinctrl-0 = <0x4c>; pinctrl-names = "default"; power-domains = <0x1 0x20>; reg = <0x0 0xee0a0200 0x0 0x700>; - resets = <0x6 0x2be>; + resets = <0x6 0x2bf>; status = "okay"; }; Signed-off-by: Eugeniu Rosca <erosca@de.adit-jv.com>
generated by cgit (git 2.34.1) at 2024-11-19 23:02:45 +0000