summaryrefslogtreecommitdiffstats
path: root/arch
Commit message (Collapse)AuthorAgeFilesLines
* sandbox, test: add test for GPIO_HOG functionHeiko Schocher2020-07-051-0/+20
| | | | | | | | | | | | currently gpio hog function is not tested with "ut dm gpio" so add some basic tests for gpio hog functionality. For this enable GPIO_HOG in sandbox_defconfig, add in DTS some gpio hog entries, and add testcase in "ut dm gpio" command. Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* riscv: use log functions in fdt_fixupHeinrich Schuchardt2020-07-031-6/+8
| | | | | | | | | | | | | Replace printf() and debug() by log_err() and log_debug(). "No reserved memory region found in source FDT\n" is not an error but a debug information. %s/can not/cannot/ - use the more common spelling. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
* riscv: sifive: fu540: enable all cache ways from U-Boot properPragnesh Patel2020-07-034-0/+72
| | | | | | | | Add L2 cache node to enable all cache ways from U-Boot proper. Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* riscv: Use optimized version of fdtdec_get_addr_size_no_parentAtish Patra2020-07-031-3/+3
| | | | | | | | | | fdtdec_get_addr_size_no_parent is not an optimized version if parent node is already available with the caller. Use fdtdec_get_addr_size_auto_parent to read the "reg" property Signed-off-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com>
* riscv: Do not return error if reserved node already existsAtish Patra2020-07-031-1/+1
| | | | | | | | Not all errors are fatal. If a reserved memory node already exists in the destination device tree, we can continue to boot without failing. Signed-off-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com>
* riscv: Do not build reset.c if SYSRESET is onBin Meng2020-07-031-0/+2
| | | | | | | | | SYSRESET uclass driver already provides all the reset APIs, hence exclude our own ad-hoc reset.c implementation. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Sagar Kadam <sagar.kadam@sifive.com> Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
* riscv: Enable CONFIG_OF_BOARD_FIXUP by default for OF_SEPARATEBin Meng2020-07-021-0/+3
| | | | | | | | | | | | | Starting from OpenSBI v0.7, the SBI firmware inserts/fixes up the reserved memory node for PMP protected memory regions. All RISC-V boards need to copy the reserved memory node from the device tree provided by the firmware to the device tree used by U-Boot. Turn on CONFIG_OF_BOARD_FIXUP by default for OF_SEPARATE. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Rick Chen <rick@andestech.com>
* riscv: Expand the DT size before copy reserved memory nodeBin Meng2020-07-021-0/+12
| | | | | | | | | | The FDT blob might not have sufficient space to hold a copy of reserved memory node. Expand it before the copy. Reported-by: Rick Chen <rick@andestech.com> Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Rick Chen <rick@andestech.com>
* riscv: Avoid the reserved memory fixup if src and dst point to the same placeBin Meng2020-07-021-4/+8
| | | | | | | | | | The copy of reserved memory node from source dtb to destination dtb can be avoided if they point to the same place. This is useful when OF_PRIOR_STAGE is used. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Rick Chen <rick@andestech.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
* riscv: fu540: dts: Correct reg size of otp and dmc nodesBin Meng2020-07-021-2/+2
| | | | | Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
* riscv: fu540: dts: Remove the unnecessary space in the cpu2_intc nodeBin Meng2020-07-021-1/+1
| | | | | Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
* Merge tag 'u-boot-rockchip-20200628' of ↵Tom Rini2020-06-281-2/+19
|\ | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip - rk3188 cpu init and APLL fix; - rk3399: Add BOOTENV_SF command; - rk3288 correct vop0 vop1 setting;
| * rockchip: rk3188: Fix back to BROM bootAlexander Kochetkov2020-06-271-2/+19
| | | | | | | | | | | | | | | | | | | | | | | | Move the setting for noc remap out of SPL code. Changing noc remap inside SPL results in breaking back to BROM boot. Fixes commit c14fe2a8e192 ("rockchip: rk3188: Move SoC one time setting into arch_cpu_init()"). Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* | arm: socfpga: misc_s10: Fix EMAC register address calculationLey Foon Tan2020-06-261-1/+1
|/ | | | | | | | | Fix EMAC register address calculation, address need to multiply with sizeof(u32) or 4. This fixes write to invalid address. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
* ARM: dts: imx6q-tbs2910: Fix Ethernet regressionFabio Estevam2020-06-251-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since commit: commit 6333cbb3817ed551cd7d4e92f7359c73ccc567fc Author: Michael Walle <michael@walle.cc> Date: Thu May 7 00:11:58 2020 +0200 phy: atheros: ar8035: remove static clock config We can configure the clock output in the device tree. Disable the hardcoded one in here. This is highly board-specific and should have never been enabled in the PHY driver. If bisecting shows that this commit breaks your board it probably depends on the clock output of your Atheros AR8035 PHY. Please have a look at doc/device-tree-bindings/net/phy/atheros.txt. You need to set "clk-out-frequency = <125000000>" because that value was the hardcoded value until this commit. Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Joe Hershberger <joe.hershberger@ni.com> , the clock output setting for the AR803x driver is removed from being hardcoded in the PHY driver and should be passed via device tree instead. Update the device tree with the "qca,clk-out-frequency" property so that Ethernet can work again. Reported-by: Soeren Moch <smoch@web.de> Signed-off-by: Fabio Estevam <festevam@gmail.com> Tested-by: Soeren Moch <smoch@web.de>
* mx6cuboxi: enable MMC and eMMC in DT for SPLWalter Lozano2020-06-231-0/+8
| | | | Signed-off-by: Walter Lozano <walter.lozano@collabora.com>
* arm: dts: imx: fsl-imx8qm.dtsi: fix gpio aliasesYe Li2020-06-231-7/+8
| | | | | | | | | | | | | | | | | | | | | | | | | Current aliases missed gpio0 node, and this node shoud be aliased to gpio index 0 to align with i.MX8QXP. Otherwise, we will get below message when running "gpio status" command, and see the reason by "dm uclass". => gpio status Device 'gpio@5d090000': seq 0 is in use by 'gpio@5d080000' Device 'gpio@5d0a0000': seq 1 is in use by 'gpio@5d090000' Device 'gpio@5d0b0000': seq 2 is in use by 'gpio@5d0a0000' => dm uclass uclass 36: gpio 0 * gpio@5d080000 @ fbaefb90, seq 0, (req -1) 1 * gpio@5d090000 @ fbaefc70, seq 1, (req 0) 2 * gpio@5d0a0000 @ fbaefd50, seq 2, (req 1) 3 * gpio@5d0b0000 @ fbaefe30, seq 5, (req 2) 4 * gpio@5d0c0000 @ fbaeff10, seq 3, (req 3) 5 * gpio@5d0d0000 @ fbaefff0, seq 4, (req 4) 6 * gpio@5d0e0000 @ fbaf00d0, seq 6, (req 5) 7 * gpio@5d0f0000 @ fbaf01b0, seq 7, (req 6) Signed-off-by: Ye Li <ye.li@nxp.com>
* ARM: imx: soc: Select default TEXT_BASE for MX7Marek Vasut2020-06-221-0/+7
| | | | | | | | | | | | | | | | | | | | | Select default U-Boot and SPL text base for the MX7 SoC. The U-Boot text base is picked as the one used by various MX7 boards. The SPL text base however is different. The SPL text base is set to 0x912000 instead of the usual 0x911000, that is because the 0x911000 value cannot work. Using 0x911000 as a SPL text base will result in the DCD header being placed below the 0x911000 address, which is a reserved SRAM area which must not be used. This will actually trigger eMMC boot failure on MX7D at least. Hence the increment. Update all boards affected by this SPL problem to the new SPL_TEXT_BASE. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: NXP i.MX U-Boot Team <uboot-imx@nxp.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
* ARM: imx: soc: Switch BOARD_EARLY_INIT_F to imply on MX7Marek Vasut2020-06-221-1/+1
| | | | | | | | | | | | There are systems where board_early_init_f() is plain empty. Switch the config option from "select" to "imply", to permit user to unset the BOARD_EARLY_INIT_F if it were to be empty. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: NXP i.MX U-Boot Team <uboot-imx@nxp.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
* ARM: imx: ddr: Fill in missing DDRC ZQCTLx on i.MX7Marek Vasut2020-06-222-1/+4
| | | | | | | | | | | | | | | | The iMX7 defines further DDRC ZQCTLx registers, however those were thus far missing from the list of registers and not programmed. On systems with LPDDR2 or DDR3, those registers must be programmed with correct values, otherwise the DRAM may not work. However, existing systems which worked without programming these registers before are now setting those registers to 0, which is the default value, so no functional change there. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: NXP i.MX U-Boot Team <uboot-imx@nxp.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
* ARM: dts: imx6qdl-sabresd: Fix AR8031 phy-modeFabio Estevam2020-06-221-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | As per kernel commit 0672d22a1924 ("ARM: dts: imx: Fix the AR803X phy-mode) the correct phy-mode should be "rgmii-id", so fix it accordingly to fix the Ethernet regression. This problem has been exposed by commit: commit 13114f38e2ccea9386726d8b9831dfc310589548 Author: Vladimir Oltean <vladimir.oltean@nxp.com> Date: Thu May 7 00:11:51 2020 +0200 phy: atheros: Explicitly disable RGMII delays To eliminate any doubts about the out-of-reset value of the PHY, that the driver previously relied on. If bisecting shows that this commit breaks your board you probably have a wrong PHY interface mode. You probably want the PHY_INTERFACE_MODE_RGMII_RXID or PHY_INTERFACE_MODE_RGMII_ID mode. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Fabio Estevam <festevam@gmail.com>
* ARM: dts: imx6qdl-sabreauto: Fix AR8031 phy-modeFabio Estevam2020-06-221-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | As per kernel commit 0672d22a1924 ("ARM: dts: imx: Fix the AR803X phy-mode) the correct phy-mode should be "rgmii-id", so fix it accordingly to fix the Ethernet regression. This problem has been exposed by commit: commit 13114f38e2ccea9386726d8b9831dfc310589548 Author: Vladimir Oltean <vladimir.oltean@nxp.com> Date: Thu May 7 00:11:51 2020 +0200 phy: atheros: Explicitly disable RGMII delays To eliminate any doubts about the out-of-reset value of the PHY, that the driver previously relied on. If bisecting shows that this commit breaks your board you probably have a wrong PHY interface mode. You probably want the PHY_INTERFACE_MODE_RGMII_RXID or PHY_INTERFACE_MODE_RGMII_ID mode. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Fix the phy-mode accordingly to fix the regression. Signed-off-by: Fabio Estevam <festevam@gmail.com>
* ARM: dts: imx6qdl-sr-som: Sync with kernel 5.8-rc1Fabio Estevam2020-06-221-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | Sync the device tree with 5.8-rc1. It basically contains the following extra kernel commit: commit 86b08bd5b99480b79a25343f24c1b8c4ddcb5c09 Author: Russell King <rmk+kernel@armlinux.org.uk> Date: Wed Apr 15 16:44:17 2020 +0100 ARM: dts: imx6-sr-som: add ethernet PHY configuration Add ethernet PHY configuration ahead of removing the quirk that configures the clocking mode for the PHY. The RGMII delay is already set correctly. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org> , which passes the 'qca,clk-out-frequency' property and it is important to specify the correct frequency generated by the AR8035. Signed-off-by: Fabio Estevam <festevam@gmail.com> Tested-by: Tom Rini <trini@konsulko.com>
* Merge tag 'u-boot-stm32-20200619' of ↵Tom Rini2020-06-193-0/+7
|\ | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-stm - fix SD card cart detect on DHCOM and ST boards
| * ARM: dts: stm32: Reinstate card detect behavior on ST boardsPatrick Delaunay2020-06-192-0/+4
| | | | | | | | | | | | | | | | | | | | The cd-gpios with (GPIO_ACTIVE_LOW | GPIO_PULL_UP) gpio is thus far unsupported, reinstate the old cd-gpios behavior until this handling is fully implemented. This avoid potential issue for SDCard boot: the card detect fails with floating gpio. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
| * ARM: dts: stm32: Reinstate card detect behavior on DHSOMMarek Vasut2020-06-191-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | The cd-gpios with (GPIO_ACTIVE_LOW | GPIO_PULL_UP) gpio is thus far unsupported, reinstate the old cd-gpios behavior until this handling is fully implemented. This permits the DHSOM to boot from SD again, without this patch the card detect fails. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
* | ARM: tegra: Enable PSCI support for Tegra210 and Tegra186Jon Hunter2020-06-182-0/+10
|/ | | | | | | | | | | | | | | | The PSCI nodes are currently not populated for the Tegra210 and Tegra186 devices. This prevents the PSCI driver from being able to identify the PSCI method used by these devices and causes the probe of the PSCI driver to fail. Since commit 81ea00838c68 ("efi_loader: PSCI reset and shutdown") was added, which moves the PSCI EFI system reset handler into the PSCI driver, this has prevented the EFI system reset from working for Tegra210 and Tegra186. Therefore, populating these nodes is necessary to fix the EFI system reset for Tegra210 and Tegra186. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Peter Robinson <pbrobinson@gmail.com>
* dts: ARM: stm32mp15: add OP-TEE node in u-boot DTSIEtienne Carriere2020-06-164-10/+29
| | | | | | | | | | | | | | | | | | | | Add OP-TEE firmware node in stm32mp15 U-Boot DTSI. This node is needed since commit [1] that changed U-Boot/stm32mp15 to detect OP-TEE availability by probing the resource instead of relying on U-Boot configuration. The software sequence implemented by [1] is fine but U-Boot DTS/DTSI files were not updated accordingly since, hence OP-TEE presence is never detected by U-Boot, preventing Linux kernel from using OP-TEE resources. For consistency and to synchronize stm32mp15 DTSI files (excluding U-Boot specific DTSI files) with the Linux kernel ones, this change also moves the OP-TEE reserved memory nodes from board generic DTSI files to U-Boot specific board DTSI files. Link: [1] commit 43df0a159df6 ("stm32mp1: dynamically detect op-tee presence") Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
* board: stm32mp1: fix handling of DT OP-TEE reserved memory nodesEtienne Carriere2020-06-161-5/+9
| | | | | | | | | | | | | | | | Fix the sequence in stm32mp1 fdt.c that disables OP-TEE resources defined in FDT when U-boot detects OP-TEE firmware is not present. Before this change, helper function stm32_fdt_disable_optee() set property status to "disabled" for the OP-TEE reserved memory nodes but this has no impact since Linux kernel does not consider the status property for reserved-memory subnodes. This change make U-Boot to attempt to delete the node instead. Fixes: 4a1b975dac02 ("board: stm32mp1: reserve memory for OP-TEE in device tree") Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
* Merge tag 'mmc-2020-6-15' of https://gitlab.denx.de/u-boot/custodians/u-boot-mmcTom Rini2020-06-151-3/+1
|\ | | | | | | | | | | | | - fsl_esdhc sdr104 and hs200 fix and error path fix - fsl_esdhc workaround 3.3v io issue - ca_dw_mmc cleanup - presidio-asic emmc DT update.
| * board: presidio-asic: update eMMC DT informationAlex Nemirovsky2020-06-151-3/+1
| | | | | | | | | | | | | | | | | | | | Change DT compatibility name to match change in driver's name. Remove unused io_ds and fifo_mode fields from DT. Signed-off-by: Alex Nemirovsky <alex.nemirovsky@cortina-access.com> CC: Peng Fan <peng.fan@nxp.com> CC: Jaehoon Chung <jh80.chung@samsung.com> CC: Tom Rini <trini@konsulko.com>
* | Merge https://gitlab.denx.de/u-boot/custodians/u-boot-socfpgaTom Rini2020-06-141-0/+4
|\ \ | |/ |/| | | - cyclone5 bugfix
| * arm: dts: socfpga: cyclone5: Update i2c-scl-falling-time-nsLey Foon Tan2020-06-141-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit e71b6f6622d6 ("i2c: designware_i2c: Rewrite timing calculation") change the hcnt and lcnt timing calculation. New timing calculation is based on calculation from Designware i2c databook. After this new timing calculation, hcnt will have negative value with i2c-scl-falling-time-ns 5000 that set in socfpga_cyclone5_socdk.dts. This patch overwrite i2c-scl-falling-time-ns to 300ns (default SCL fall time used in Designware i2c driver) for Uboot. Before the fix: => i2c dev 0 Setting bus to 0 Failure changing bus number (-22) After the fix: => i2c dev 0 Setting bus to 0 => i2c probe Valid chip addresses: 17 51 55 5B 5C 5E 66 68 70 Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
* | arm: Remove pcm051 boardJagan Teki2020-06-111-1/+0
| | | | | | | | | | | | | | | | | | | | OF_CONTROL, DM_SPI and other driver model migration deadlines are expired for this board. Remove it. Acked-by: Lars Poeschel <poeschel@lemonage.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
* | arm: Remove omap3_pandora_defconfig boardJagan Teki2020-06-111-1/+0
|/ | | | | | | | | | OF_CONTROL, DM_SPI and other driver model migration deadlines are expired for this board. Remove it. Acked-by: Grazvydas Ignotas <notasas@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
* Merge tag 'u-boot-imx-20200609' of ↵Tom Rini2020-06-096-24/+55
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-imx Fixes for 2020.07 ----------------- - mx53: mx53menlo Convert to DM_ETH, fix fail boot - imx8mp_evk: fix boot issue - MX6, display5: fix environment - drop warnings (watchdog) for i.MX8mm i.mx8mp - enable bootaux for i.MX8M Travis: https://travis-ci.org/github/sbabic/u-boot-imx/builds/695929999
| * Revert "imx: rom api: fix image offset computation"Stefano Babic2020-06-091-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 1f63ee656698724bcdc4e711b4ccd267f6bf64ab. As reported by Ye Li on ML: 1. Removing the image_offset will break secondary (redundant) boot support for sd and emmc. 2. When booting from emmc boot partition, the image_offset is 0. But the flash.bin generated by mkimage with imximage-8mp-lpddr4.cfg is for sd. It expects to be burn at 32KB offset. The fit offset 0x60000 has already included the 32KB offset. So when you burn this flash.bin to emmc boot partition at offset 0, the fit offset should subtract the 32KB (0x60000 - 0x8000). Signed-off-by: Stefano Babic <sbabic@denx.de>
| * ARM: dts: imx: m53menlo: Convert to DM_ETHMarek Vasut2020-06-081-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | Convert the board to DM_ETH instead of legacy networking. This requires a minor addition to the DT to satisfy the requirement for specifying a PHY node. No functional change from board user perspective. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: NXP i.MX U-Boot Team <uboot-imx@nxp.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
| * ARM: imx: ddr: Add missing PHY resetMarek Vasut2020-06-082-3/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The iMX7D RM 9.2.4.9.3 Power removal flow Table 9-11. Re-enabling power explicitly says both the DDR controller and the PHY must be reset in the correct sequence. Currently the code only resets the controller. This leads to a misbehavior where the system brings the DRAM up after reboot, but the DRAM is unstable. Add the missing reset. The easiest way to trigger this is by triggering WDT without having the WDT assert WDOG_B signal, i.e. mw.w 0x30280000 0x25 . Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: NXP i.MX U-Boot Team <uboot-imx@nxp.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
| * imx: rom api: fix image offset computationSébastien Szymanski2020-06-081-6/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | When not booting from FlexSPI, the offset computation is: offset = image_offset + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512 - 0x8000; When booting from SD card or eMMC user partition, image_offset is 0x8000. It is useless to add and remove 0x8000. When booting from other device, image_offset is 0 so this computation is wrong. Simplfy this computation to work on all booting devices. Signed-off-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com>
| * imx: move ATF to the back of the FIT to fix loading over yModemPatrick Wildt2020-06-081-14/+17
| | | | | | | | | | | | | | | | | | | | | | | | With yModem the FIT Image is only supplied once, so we can only seek forward in the yModem supplied image and never backwards. With the recent changes to the SPL mechanism, including loading U-Boot first, FDT after, then the loadables, we must also reorder the FIT image script to make sure that the loadables are last in the FIT image. Signed-off-by: Patrick Wildt <patrick@blueri.se> Tested-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com>
| * imx: Kconfig: enable IMX_BOOTAUX for i.MX8MPeng Fan2020-06-081-1/+1
| | | | | | | | | | | | | | i.MX8M could use imx bootaux to boot m4/m7 core, so let's add it to the dependency list. Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * ARM: dts: imxrt1050: indent lcdif node correctlyGiulio Benetti2020-06-081-6/+6
| | | | | | | | | | | | | | | | Accidentally submitted a patch with indentation not correct, let's fix it by indenting wrong lines. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Acked-by: Peng Fan <peng.fan@nxp.com>
* | Merge https://gitlab.denx.de/u-boot/custodians/u-boot-mpc85xxTom Rini2020-06-0855-8/+2772
|\ \ | | | | | | | | | | | | | | | | | | - DM_ETH support for P2041RDB, T1024RDB, P5040DS, P3041DS, P4080DS, bug fixes - Add TBI PHY access through MII - DDR: Rework errata workaround for A008109, A008378, 009942
| * | ddr: Rework errata A008109, A008378, 009942 workaroundJaiprakash Singh2020-06-041-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | Move errata A008109, A008378, 009942 workaround implementation from compute_fsl_memctl_config_regs() to fsl_ddr_set_memctl_regs() and add register write after each workaround implementation. Signed-off-by: Jaiprakash Singh <Jaiprakash.singh@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | ddr: fsl: Impl. Erratum A008109Joakim Tjernlund2020-06-041-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | Impl. erratum as descibed in errata doc. Enable A008109 for T1040 and T1024 Signed-off-by: Joakim Tjernlund <joakim.tjernlund@infinera.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | powerpc: dts: add QorIQ DPAA 1 FMan v3 to T1024RDBMadalin Bucur2020-06-041-1/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | Introduce the QorIQ DPAA 1 Frame Manager nodes in the T1024RDB device tree. The device tree fragments are copied over with little modification from the Linux kernel source code. Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | powerpc: dts: add QorIQ DPAA 1 FMan v3 for T102xMadalin Bucur2020-06-042-0/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add the QorIQ DPAA 1 Frame Manager v3 device tree nodes for the T102x SoCs. The device tree fragments are copied over with little modification from the Linux kernel source code. Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | powerpc: dts: add QorIQ DPAA 1 FMan to P5040DSMadalin Bucur2020-06-041-1/+251
| | | | | | | | | | | | | | | | | | | | | | | | | | | Introduce the QorIQ DPAA 1 Frame Manager nodes in the P5040DS device tree. The device tree fragments are copied over with little modification from the Linux kernel source code. Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | powerpc: dts: add QorIQ DPAA 1 FMan for P5040Madalin Bucur2020-06-041-0/+69
| | | | | | | | | | | | | | | | | | | | | | | | The device tree fragments are copied over with little modification from the Linux kernel source code. Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
generated by cgit (git 2.34.1) at 2024-10-02 00:38:22 +0000