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* armv8: Add workaround for USB erratum A-009007Ran Wang2017-09-114-0/+65
| | | | | | | | | | | | | | | Rx Compliance tests may fail intermittently at high jitter frequencies using default register values. Program register USB_PHY_RX_OVRD_IN_HI in certain sequence to make the Rx compliance test pass. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Suresh Gupta <suresh.bhagat@nxp.com> Signed-off-by: Ran Wang <ran.wang_1@nxp.com> [YS: Reordered Kconfig options] Reviewed-by: York Sun <york.sun@nxp.com>
* armv8: Add workaround for USB erratum A-008997Ran Wang2017-09-113-0/+34
| | | | | | | | | | | | | | | | Low Frequency Periodic Signaling(LFPS) Peak-to-Peak Differential Output Voltage Test Compliance fails using default transmitter settings Change config of transmitter signal swings by setting register PCSTXSWINGFULL to 0x47 to pass compliance tests. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com> Signed-off-by: Ran Wang <ran.wang_1@nxp.com> [YS: Reordered Kconfig options] Reviewed-by: York Sun <york.sun@nxp.com>
* armv8: Add workaround for USB erratum A-009798Ran Wang2017-09-114-0/+32
| | | | | | | | | | | | | | | | The default setting for USB High Speed Squelch Threshold results in a threshold close to or lower than 100mV. This leads to Receiver Compliance test failure for a 100mV threshold. Shift the threshold from ~100mV towards ~130mV by setting SQRXTUNE to 0x0 to pass USB High Speed Receiver Sensitivity Compliance test. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com> Signed-off-by: Ran Wang <ran.wang_1@nxp.com> [YS: Reordered Kconfig options] Reviewed-by: York Sun <york.sun@nxp.com>
* armv8: Add workaround for USB erratum A-009008Ran Wang2017-09-114-0/+36
| | | | | | | | | | | | | USB High Speed (HS) EYE Height Adjustment USB HS speed eye diagram fails with the default value at many corners, particularly at a high temperature Optimal eye at TXREFTUNE value to 0x9 is observed, change set the same value. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> [YS: Reordered Kconfig options] Reviewed-by: York Sun <york.sun@nxp.com>
* armv8: Add scfg_clrsetbits_32(), scfg_clrbits_32()Ran Wang2017-09-111-0/+4
| | | | | | | Some erratum patch might need it to program registers. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8: fsl-layerscape: Support to add RGMII for ls1088aqdsAshish Kumar2017-09-114-0/+32
| | | | | | | | | | | | This patch adds support for RGMII protocol NXP's LDPAA2 support RGMII protocol. LS1088A is the first Soc supporting both RGMII and SGMII. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Amrita Kumari <amrita.kumari@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8: ls1088aqds: Add support of LS1088AQDSAshish Kumar2017-09-114-2/+86
| | | | | | | | | | | | | This patch add support of LS1088AQDS platform. The LS1088A QorIQTM Development System (QDS) is a high-performance computing, evaluation, and development platform that supports the LS1088A QorIQ Architecture processor. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8: ls1088ardb: Add support for LS1088ARDB platformAshish Kumar2017-09-115-1/+58
| | | | | | | | | | | | | | | | LS1088A is an ARMv8 implementation. The LS1088ARDB is an evaluatoin platform that supports the LS1088A family SoCs. This patch add basic support of the platform. Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> [YS: Disabled NAND in board header file] Reviewed-by: York Sun <york.sun@nxp.com> WIP: disable NAND for LS1088ARDB
* armv8: ls1088a: Add NXP LS1088A SoC supportAshish Kumar2017-09-1113-11/+393
| | | | | | | | | | | | | | | | LS1088A is compliant with the Layerscape Chassis Generation 3 with eight ARM v8 Cortex-A53 cores in 2 cluster, CCI-400, one 64-bit DDR4 SDRAM memory controller with ECC, Data path acceleration architecture 2.0 (DPAA2), Ethernet interfaces (SGMIIs, RGMIIs, QSGMIIs, XFIs), QSPI, IFC, PCIe, SATA, USB, SDXC, DUARTs etc. Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> [YS: Revised commit message] Reviewed-by: York Sun <york.sun@nxp.com>
* armv8: fsl-layerscape: Fix final MMU table for QSPI and IFCSuresh Gupta2017-09-111-2/+4
| | | | | | | | | For QSPI and IFC addresses execution shouldn't be allowed when u-boot running from DDR. Revise the MMU final table to enforce execute-never bits. Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8: fsl: Use correct conditional compile for ls1012aRan Wang2017-09-111-1/+1
| | | | | | | | | | According current code base, CONFIG_LS1012A should be CONFIG_ARCH_LS1012A, or function fsl_fdt_disable(blob) will be wrongly called to disable all dwc3 USB nodes on LS1012A, which cause Linux USB function stop working at all. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8: fsl-lsch3: Make CCN-504 related code conditionalAshish Kumar2017-09-112-3/+9
| | | | | | | | | | LS2080 family has CCN-504 cache coherent interconnet. Other SoCs in LSCH3 family may have differnt interconnect. Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> [YS: revised commit message] Reviewed-by: York Sun <york.sun@nxp.com>
* LS2080ARDB: QSPI boot: Secure Boot image validationUdit Agarwal2017-09-112-1/+7
| | | | | | | | | | Adds header address for PPA to be validated during ESBC phase for ARCH_LS2088 and QSPI_BOOT. Moves sec_init prior to ppa_init(). It must be initialized before the PPA. Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> [YS: revised commit message] Reviewed-by: York Sun <york.sun@nxp.com>
* SECURE_BOOT: Unify memory map for Layerscape based platformsSumit Garg2017-09-112-38/+28
| | | | | | | | | | Unify memory map for Layerscape based platforms. This patch includes changes in bootscript, bootscript header and PPA header addresses change as per unified memory map. Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Tested-by: Vinitha Pillai <vinitha.pillai@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* fsl-layerscape: Consolidate registers space defination for CCI-400 busAshish Kumar2017-09-118-101/+37
| | | | | | | | | | | | | | | | CoreLink Cache Coherent Interconnect (CCI) provides full cache coherency between two clusters of multi-core CPUs and I/O coherency for devices and I/O masters. This patch add new config option SYS_FSL_HAS_CCI400 and moves existing register space definaton of CCI-400 bus to fsl_immap to be shared. CONFIG_SYS_CCI400_ADDR is replaced with SYS_CCI400_OFFSET in Kconfig. Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> [YS: revised commit message, squashed patches for armv8 and armv7] Reviewed-by: York Sun <york.sun@nxp.com>
* usb: net: migrate USB Ethernet adapters to KconfigChris Packham2017-09-083-0/+8
| | | | | | | | This migrates ASIX, ASIX88179, MCS7830, RTL8152 and SMSC95XX to Kconfig. Update defconfigs. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* usb: net: migrate CONFIG_USB_HOST_ETHER to KconfigChris Packham2017-09-082-0/+2
| | | | | | | | | | CONFIG_USB_HOST_ETHER is the framework that the drivers are dependent on USB_HOST_ETHER. Use this as a menu and move the existing LAN75XX and LAN78XX options under new menu. Finally update the defconfigs that need CONFIG_USB_HOST_ETHER. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* rockchip: enable SPL_SYSRESET config for all Rockchip SoCsKever Yang2017-09-081-0/+1
| | | | | | | | | | With Makefiles testing for $(SPL_TPL_)SYSRESET, we need SPL_SYSRESET for do_reset() in SPL for Rockchip SoCs. References: 87c16d4 "drivers: spl: consistently use the $(SPL_TPL_) macro" Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* rockchip: rk3328: fix syscon id tableKever Yang2017-09-081-0/+1
| | | | | | | | | syscon id table need a dummy member as NULL ending, or else system will panic while try to match a compatible in this table as a list. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* Merge git://git.denx.de/u-boot-rockchipTom Rini2017-09-052-0/+51
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| * rockchip: rk3288: Add reset reason detectionWadim Egorov2017-09-052-0/+51
| | | | | | | | | | | | | | | | | | | | Sometimes it's helpful to know the reset reason caused in the SoC. Add reset reason detection for the RK3288 SoC. This will set an environment variable which represents the reset reason. Signed-off-by: Wadim Egorov <w.egorov@phytec.de> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* | Merge branch 'rmobile' of git://git.denx.de/u-boot-shTom Rini2017-09-041-0/+42
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| * ARM: rmobile: Add missing IPSR18 bits to R8A7795 PFCMarek Vasut2017-09-051-0/+42
| | | | | | | | | | | | | | | | | | | | | | The IPSR18 register bits were missing from the R8A7795 ES2.0+ PFC tables, which triggered a BUG() in sh_pfc driver. This is because of an out-of-bounds access to the pinmux_gpios[] array in the PFC tables, which was too short due to the missing IPSR18 bits. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* | x86: baytrail: acpi: Add full reset bit to the reset register value in FADTBin Meng2017-09-021-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | It was noticed a few times, that the reboot from Linux (reboot command) is different from the reboot (reset command) under U-Boot. The U-Boot version does seem to reset the board more deeply (PCI cards etc) than the Linux reboot. This is actually caused by missing full reset bit in the reset register value in the ACPI FADT table. Reported-by: Stefan Roese <sr@denx.de> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Stefan Roese <sr@denx.de>
* | Convert CONFIG_SPL_OMAP3_ID_NAND to KconfigAdam Ford2017-09-012-0/+7
| | | | | | | | | | | | | | | | This converts the following to Kconfig: CONFIG_SPL_OMAP3_ID_NAND Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | Convert CONFIG_SYS_I2C_BUS_MAX to KconfigAdam Ford2017-09-014-4/+0
| | | | | | | | | | | | | | | | | | | | This converts the following to Kconfig: CONFIG_SYS_I2C_BUS_MAX Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Heiko Schocher <hs@denx.de> [trini: Fix AM43XX drop AM44XX] Signed-off-by: Tom Rini <trini@konsulko.com>
* | Configs: Migrate I2C_BUS_MAX to CONFIG_SYS_I2C_BUS_MAXAdam Ford2017-09-014-4/+4
| | | | | | | | | | | | | | | | For consistency with other platforms and in preparation of Kconfig migration, let's change Several TI platforms that use I2C_BUS_MAX to CONFIG_SYS_I2C_BUS_MAX Signed-off-by: Adam Ford <aford173@gmail.com>
* | Kconfig: Migrate all of cmd/fastboot/Kconfig to defconfigsTom Rini2017-09-011-0/+6
| | | | | | | | | | | | | | | | | | | | - Move ANDROID_IMAGE_SUPPORT to top level Kconfig under images as it's not strictly part of fastboot. - Add some defaults for the fastboot buffer location and size - Migrate all options listed in cmd/fastboot/Kconfig - Cleanup the README Signed-off-by: Tom Rini <trini@konsulko.com>
* | Merge git://git.denx.de/u-boot-sunxiTom Rini2017-09-011-1/+1
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| * | sunxi: Fix CONFIG_SUNXI_GMAC referencesDave Prue2017-09-011-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SUNXI_GMAC was still used to configure the code where as the same has been renamed and moved to Kconfig in below commit "sunxi: Move SUNXI_GMAC to Kconfig" (sha1: 4d43d065db3262f9a9918ba72457bf36dfb8e0bb) Signed-off-by: Dave Prue <dave@prue.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jagan@openedev.com> Reviewed-by: Mark Kettenis <kettenis@openbsd.org> Tested-by: Mark Kettenis <kettenis@openbsd.org> [Tweek commit message, config_whitelist.txt, build-whitelist.sh] Signed-off-by: Jagan Teki <jagan@openedev.com>
* | | Merge git://git.denx.de/u-boot-imxTom Rini2017-09-0110-41/+63
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: configs/imx6qdl_icore_mmc_defconfig configs/imx6qdl_icore_rqs_defconfig
| * | | i.MX6Q: spl: Fix falcon to use dram_init_banksizeJagan Teki2017-08-301-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Memory dt node update introduced by spl_fixup_fdt() in below commit was making DDR configuration in-appropriate to boot falcon mode. Hence added dram_init_banksize for explicit assignment of proper base and size of DDR. "boot: fdt: Perform arch_fixup_fdt() on the given device tree for falcon boot" (sha1: 6e7585bb64b12f632681c80c4b193349e1985d92) Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * | | imx: remove SATA boot mode for i.MX 6UL and 6ULLStefan Agner2017-08-301-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The NXP i.MX 6UL and 6ULL do not support SATA and have no SATA boot mode, hence remove it from the boot device detecion. This fixes a build error introduced with 3bd1642d4d50 ("imx: fix USB boot mode detection for i.MX 6UL and 6ULL") Fixes: 3bd1642d4d50 ("imx: fix USB boot mode detection for i.MX 6UL and 6ULL") Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Reviewed-by: Stefano Babic <sbabic@denx.de> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * | | imx6: don't include unneeded boot_mode array in SPLAnatolij Gustschin2017-08-291-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The soc_boot_modes array is only used by bmode command and not needed in SPL. Don't include it into SPL. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Stefano Babic <sbabic@denx.de>
| * | | imx: timer: don't clear the GPT control register multiple timesAnatolij Gustschin2017-08-291-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is no need to clear the control register 100 times in a loop, a single zero write clears the register. I didn't find any justification why clearing this register in a loop is needed (no info in i.MX6 errata or GPT timer linux driver, linux driver uses single write to clear this control register). Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
| * | | imx: imx6: Move gpr_init() function to soc.cBreno Lima2017-08-282-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since the gpr_init() function is common for boards using MX6S, MX6DL, MX6D, MX6Q and MX6QP processors move it to the soc.c file. Signed-off-by: Breno Lima <breno.lima@nxp.com> Acked-by: Stefano Babic <sbabic@denx.de> Reviewed-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
| * | | imx: use BOOT_DEVICE_BOARD instead of UARTStefan Agner2017-08-251-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | i.MX 6 serial downloader is not necessarily booting via UART but can also boot from USB. In fact only some i.MX chips have serial downloader support via UART (e.g. 6UL/ULL and Vybrid) but all of them have serial downloader support via USB. Use the more appropriate BOOT_DEVICE_BOARD define which is used for ROM provided recovery mechanisms in general. Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
| * | | imx: fix USB boot mode detection for i.MX 6UL and 6ULLStefan Agner2017-08-252-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the reserved boot mode used in the bmode command for i.MX 6UL and 6ULL as introduced in commit 3fd9579085fa ("imx: mx6ull: fix USB bmode for i.MX 6UL and 6ULL"). Also replace BMODE_UART with BMODE_RESERVED, which is more appropriate. Commit 96aac843b68d ("imx: Use IMX6_BMODE_* macros instead of numericals") added macros for boot modes, in the process the reserved boot mode got named BMODE_UART. We use the reserved boot mode in the bmode command to let the boot ROM enter serial downloader recovery mode. But this is only a side effect, the actual boot mode is reserved... Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
| * | | imx: fix licensing in i.MX filesStefano Babic2017-08-234-35/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some files for i.MX do not yet have the SPDX ID to reference the correct license. Signed-off-by: Stefano Babic <sbabic@denx.de> Reviewed-by: Wolfgang Denk <wd@denx.de>
| * | | imx: mx7: psci: add copyright and licensePeng Fan2017-08-232-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add copyright and license header. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
* | | | Merge git://git.denx.de/u-boot-marvellTom Rini2017-09-011-1/+1
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| * | | | ARM: mvebu: add "spi-flash" compatible stringChris Packham2017-08-301-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | U-boots spi-nor support is currently considered a work in progress. For now to avoid issues it is necessary to add a "spi-flash" compatible string. Eventually the "jedec,spi-nor" will be sufficient when the core U-boot code is updated to support it. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Signed-off-by: Stefan Roese <sr@denx.de>
* | | | | Merge git://git.denx.de/u-boot-uniphierTom Rini2017-09-0132-163/+328
|\ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - add {ofnode,dev}_read_resource_byname - provide DT probe hook to Denali NAND driver - update clk/reset driver - update DT - misc cleanups
| * | | | | ARM: uniphier: set system bus pinmux for PXs3Masahiro Yamada2017-08-301-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The system bus is not enabled by default for NAND, eMMC boot etc. of PXs3. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | | | | ARM: uniphier: move CONFIG_NAND to defconfigMasahiro Yamada2017-08-301-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This imply was added when the option was moved by the moveconfig tool, but the intention is not clear. Move it to defconfig. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | | | | ARM: dts: uniphier: update PXs3 SoC/board DTMasahiro Yamada2017-08-302-50/+142
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Support PXs3 SoC and its reference development board. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | | | | ARM: dts: uniphier: sync with LinuxMasahiro Yamada2017-08-3022-62/+90
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Import updates queued up for Linux 4.14-rc1. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | | | | ARM: uniphier: fix DSPLL init code for LD20 SoCDai Okamura2017-08-301-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Dai Okamura <okamura.dai@socionext.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | | | | ARM: uniphier: remove ad-hoc pin settings for NANDMasahiro Yamada2017-08-301-24/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is now set up by the pinctrl driver when the NAND driver is probed. Remove the legacy code. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | | | | ARM: uniphier: add PLL settings for PXs3Masahiro Yamada2017-08-301-0/+55
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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