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* Merge tag 'efi-2020-01-rc3' of ↵Tom Rini2019-11-143-0/+92
|\ | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-efi Pull request for UEFI sub-system for efi-2020-01-rc3 The following changes for the UEFI subsystem are provided: * allow building UEFI binaries on the sandbox * enable access to file systems without partition tables * correctly check the return value of efi_dp_from_file()
| * efi_loader: support building UEFI binaries on sandboxHeinrich Schuchardt2019-11-123-0/+92
| | | | | | | | | | | | | | | | | | | | On the sandbox the UEFI binaries must match the host architectures. Adjust the Makefiles. Provide the PE/COFF header and relocation files. Allow building helloworld.efi on the sandbox. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
* | arm: mvebu: clearfog: fix boot from SD cardBaruch Siach2019-11-141-0/+4
| | | | | | | | | | | | | | | | Enable gpio0 in SPL to allow the sdhci driver read the SD card-detect signal. Signed-off-by: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Stefan Roese <sr@denx.de>
* | ARM: mvebu: don't dereference null bd pointerChris Packham2019-11-141-10/+0
|/ | | | | | | | As mentioned in doc/README.arm-relocation gd->bd is not available in dram_init() so we shouldn't attempt to access it. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
* Merge tag 'u-boot-imx-20191105' of ↵Tom Rini2019-11-1225-17/+2976
|\ | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-imx u-boot-imx-20191105 ------------------- i.MX8MN SoC support ROM API image download support i.MX8MM enet enabling
| * imx: imx8mm-evk: enable ethernetPeng Fan2019-11-051-0/+4
| | | | | | | | | | | | | | | | add phy-reset-gpios to reset phy Add board_phy_config to configure phy Enable DM_ETH Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * arm: dts: imx8mm: drop assigned clocks for clk nodePeng Fan2019-11-051-0/+3
| | | | | | | | | | | | | | Drop assigned clocks for clk node, this will break boot on i.MX8MM EVK board. Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * imx: imx8m: fix boot when CONFIG_$(SPL_)CLK not definedPeng Fan2019-11-051-6/+8
| | | | | | | | | | | | | | | | | | | | When CONFIG_$(SPL_)CLK not defined, the clock controller device not exist, so to avoid boot failure for platform not have CONFIG_$(SPL_)CLK, add a check. Reviewed-by: Patrick Wildt <patrick@blueri.se> Tested-by: Patrick Wildt <patrick@blueri.se> Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * imx: add i.MX8MN DDR4 board supportPeng Fan2019-11-055-3/+324
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Support pinctrl/clk/sdhc, include ddr4 timing data. Log: U-Boot SPL 2019.10-rc3-00356-g497c500423-dirty (Sep 16 2019 - 10:54:58 +0800) Normal Boot Trying to boot from BOOTROM image offset 0x8000, pagesize 0x200, ivt offset 0x0 U-Boot 2019.10-rc3-00356-g497c500423-dirty (Sep 16 2019 - 10:54:58 +0800) CPU: Freescale i.MX8MNano rev1.0 at 24 MHz Reset cause: POR Model: NXP i.MX8MNano DDR4 EVK board DRAM: 2 GiB MMC: FSL_SDHC: 1, FSL_SDHC: 2 Loading Environment from MMC... *** Warning - bad CRC, using default environment In: serial Out: serial Err: serial Net: No ethernet found. Hit any key to stop autoboot: 0 Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * imx: add dtsi for i.MX8MNPeng Fan2019-11-052-0/+1358
| | | | | | | | | | | | Add dtsi for i.MX8MN Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * imx8m: add i.MX8MN ddr4 image cfg filePeng Fan2019-11-051-0/+17
| | | | | | | | | | | | Add cfg file for i.MX8MN DDR4 Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * imx8mn: add get_boot_devicePeng Fan2019-11-051-0/+48
| | | | | | | | | | | | | | No ROM INFO structure on iMX8MN, use new ROM API to get boot device from ROM. Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * imx: cpu: restrict get_boot_devicePeng Fan2019-11-051-1/+1
| | | | | | | | | | | | | | i.MX8MN has its own get_boot_device, so restrict with i.MX8MQ and i.MX8MM. Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * imx: add rom api supportPeng Fan2019-11-054-0/+331
| | | | | | | | | | | | | | i.MX8MN support loading images with rom api, so we implement reuse board_return_to_bootrom to let ROM loading images. Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * imx: spl: use spl_board_boot_device for i.MX8MNPeng Fan2019-11-051-1/+1
| | | | | | | | | | | | i.MX8MN follow same logic as i.MX8MM, so use spl_board_boot_device Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * imx8mn: add pin headerPeng Fan2019-11-051-0/+763
| | | | | | | | | | | | Add pin header for i.MX8MN Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * imx: add i.MX8MN PE propertyPeng Fan2019-11-051-1/+1
| | | | | | | | | | | | i.MX8MN does not have LVTTL, it has a PE property Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * imx8mn: set BYPASS ID SWAP to avoid AXI bus errorsPeng Fan2019-11-051-1/+1
| | | | | | | | | | | | | | Set the BYPASS ID SWAP bit (GPR10 bit 1) in order for GPU not to generated AXI bus errors with TZC380 enabled. Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * imx8m: add clk support for i.MX8MNPeng Fan2019-11-054-3/+83
| | | | | | | | | | | | | | | | i.MX8MN has similar architecture with i.MX8MM, so it could reuse the clock code of i.MX8MM, but i.MX8MN has different CCM root configurations, so need a separate root entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * imx8mn: support get_cpu_revPeng Fan2019-11-054-1/+8
| | | | | | | | | | | | Add a dummy cpu type and support get_cpu_rev for i.MX8MN Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * imx: add i.MX8MN kconfig entryPeng Fan2019-11-051-0/+4
| | | | | | | | | | | | Add i.MX8MN kconfig entry Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * arm: dts: imx8qm-mek: add u-boot, dm-spl for lpuart0Peng Fan2019-11-051-0/+8
| | | | | | | | | | | | | | | | | | lpuart0 is the uart used by SPL and U-Boot proper, and DM_SERIAL is enabled. Since uclass power domain is also enabled, to make lpuart work properly, need add u-boot,dm-spl for lpuart power domain and its parent. Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * arm: dts: imx8qxp-mek: add u-boot, dm-spl for lpuart0Peng Fan2019-11-051-0/+8
| | | | | | | | | | | | | | | | | | lpuart0 is the uart used by SPL and U-Boot proper, and DM_SERIAL is enabled. Since uclass power domain is also enabled, to make lpuart work properly, need add u-boot,dm-spl for lpuart power domain and its parent. Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * imx8qm: mek: enable dm-spl for pmPeng Fan2019-11-051-0/+5
| | | | | | | | | | | | | | | | | | with u-boot,dm-spl added for imx8qm-pm node, and SPL_SIMPLE_BUS enabled, the bind and probe code in board file could be removed. Also we need to enlarge SYS_MALLOC_F_LEN to avoid calloc fail. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* | Merge tag 'u-boot-rockchip-20191110' of ↵Tom Rini2019-11-1113-16/+727
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip - Add support for rockchip pmic rk805,rk809, rk816, rk817 - Add rk3399 board Leez support - Fix bug in rk3328 ram driver - Adapt SPL to support ATF bl31 with entry at 0x40000 - Fix the u8 type comparision with '-1'. - Fix checkpatch warning for multi blank line and review signature.
| * | rockchip: firefly-rk3288: Enable TPL supportKever Yang2019-11-101-0/+1
| | | | | | | | | | | | | | | | | | | | | This patch enable TPL support for firefly-rk3288 board, which works ths same way with other RK3288 board like Tinker, evb. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
| * | rockchip: adding the missing "/" in entries of boot_devicesLevin Du2019-11-105-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Without the prefix, "same-as-spl" in `u-boot,spl-boot-order` will not work as expected. When board_boot_order() `spl-boot-order.c` meets "same-as-spl", it gets the conf by looking the boot_devices table by boot source, and parse the node by the conf with: node = fdt_path_offset(blob, conf); which will failed without the "/" indicating the path. Currently only entries of boot_devices in rk3399 have the "/" prefix. Therefore add the missing ones in other boards. Signed-off-by: Levin Du <djw@t-chip.com.cn> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * | rockchip: rk3399: update SPL_STACK_R_ADDRKever Yang2019-11-101-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the same SPL_STACK_R_ADDR in Kconfig instead of each board config; default to 0x4000000(64MB) instead of 0x80000(512KB) for this address can support all the SoCs including those may have only 64MB memory, and also reserve enough space for atf, kernel(in falcon mode) loading. After the ATF entry move to 0x40000, the stack from 0x80000 may be override when loading ATF bl31. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
| * | rockchip: make_fit_atf.py: allow inclusion of a tee binaryHeiko Stuebner2019-11-101-6/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A trusted execution environment should also get loaded as loadable from a fit image, so add the possibility to present a tee.elf to make_fit_atf.py that then gets included as additional loadable into the generated its. For ease of integration the additional loadable is created as atf_(x+1) after all others to re-use core generation loops. Tested against the combinations of 1-part-atf and multi-part-atf each time with and without a tee binary present. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * | rockchip: dts: rk3328: rock64: Add same-as-spl orderEmmanuel Vadot2019-11-101-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | rk3328 can use same-as-spl option so next loaders are loaded from the same medium. Add the boot order in the rock64 dts otherwise booting from sdcard will result in u-boot looking into the eMMC. Signed-off-by: Emmanuel Vadot <manu@freebsd.org> Reviewed-by: Peter Robinson <pbrobinson@gmail.com> Tested-by: Peter Robinson <pbrobinson@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * | clk: rockchip: rk3328: Configure CPU clockSimon South2019-11-101-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | Add a call to rk3328_configure_cpu() during initialization to set the CPU-clock frequency. Signed-off-by: Simon South <simon@simonsouth.net> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * | rockchip: rk3399: Add Leez P710 supportAndy Yan2019-11-103-0/+659
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Specification - Rockchip RK3399 - LPDDR4 - TF sd scard slot - eMMC - M.2 B-Key for 4G LTE - AP6256 for WiFi + BT - Gigabit ethernet - HDMI out - 40 pin header - USB 2.0 x 2 - USB 3.0 x 1 - USB 3.0 Type-C x 1 - TYPE-C Power supply Commit details of rk3399-leez-p710.dts sync from linus tree for Linux 5.4-rc1: "arm64: dts: rockchip: Add dts for Leez RK3399 P710 SBC" (sha1: fc702ed49a8668a17343811ee28214d845bfc5e6) Signed-off-by: Andy Yan <andyshrk@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* | Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriqTom Rini2019-11-1120-31/+157
|\ \ | | | | | | | | | | | | | | | - Rename CONFIG_SECURE_BOOT to CONFIG_NXP_ESBC. - Few bug fixes and updates related to SPI, hwconfig, ethernet, fsl-layerscape, pci, icid, PSCI
| * | freescale/powerpc: Rename the config CONFIG_SECURE_BOOT nameUdit Agarwal2019-11-085-15/+15
| | | | | | | | | | | | | | | | | | | | | | | | Rename the CONFIG_SECURE_BOOT name to CONFIG_NXP_ESBC to avoid conflicts with UEFI secure boot. Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | freescale/layerscape: Rename the config CONFIG_SECURE_BOOT nameUdit Agarwal2019-11-083-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | Rename CONFIG_SECURE_BOOT to CONFIG_NXP_ESBC to avoid conflict with UEFI secure boot. Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | fsl-layerscape: fix warning if no hwconfig is definedPankaj Bansal2019-11-081-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While getting the 'subarg' of 'hwconfig' env variable in config_core_prefetch(), if no hwconfig variable is defined, below warning is received: WARNING: Calling __hwconfig without a buffer and before environment is ready Fix this by checking 'hwconfig' env variable. If not found return without further processing. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Tested-by: Michael Walle <michael@walle.cc>
| * | armv8: fsl-layerscape: introduce fsl_board_late_init()Michael Walle2019-11-081-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The fsl-layerscape already occupies board_late_init(), therefore it is not possible for a board to have its own board_late_init(). Introduce fsl_board_late_init() which can be implemented in the board specific code. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | armv8: fsl-lsch3: convert CONFIG_TARGET_x to CONFIG_ARCH_xMichael Walle2019-11-081-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The clocks are not dependent on the target but only on the SoC. Therefore, convert the CONFIG_TARGET_x macros to the corresponding CONFIG_ARCH_x. This will allow other targets to automatically use the common code. Otherwise every new target would have to add itself to the "#if defined(CONFIG_TARGET_x) || .." macros. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | armv8: ls1028a: add erratum A-050382 workaroundLaurentiu Tudor2019-11-082-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Erratum A-050382 states that the eDMA ICID programmed in the eDMA_AMQR register in DCFG is not correctly forwarded to the SMMU. The workaround consists in programming the eDMA ICID in the eDMA_AMQR register in DCFG to 40. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | armv8: lx2160a: add icid setup for platform devicesLaurentiu Tudor2019-11-085-2/+55
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add ICID setup for the platform devices contained on this chip: usb, sata, sdhc, sec. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Horia Geanta <horia.geanta@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | fsl-layerscape: add missing SATA3 and SATA4 base addressesLaurentiu Tudor2019-11-081-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | LX2160A chips have 4 sata controllers. Add missing base addresses for SATA3 and SATA4. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Horia Geanta <horia.geanta@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | armv8: ls2088a: add icid setup for platform devicesLaurentiu Tudor2019-11-083-1/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add ICID setup for the platform devices contained on this chip: usb, sata, sdhc, sec. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Horia Geanta <horia.geanta@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | fsl-layerscape: fix compile error with sec fw disabledLaurentiu Tudor2019-11-081-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If SEC FW support is not enabled (ARMV8_SEC_FIRMWARE_SUPPORT=n), below compilation error appears arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h:169:4: error: 'CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT' undeclared here (not in a function) Fix it by wrapping with CONFIG_IS_ENABLED(). Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Horia Geanta <horia.geanta@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | armv8: fsl-layerscape: guard caam specific definesLaurentiu Tudor2019-11-082-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | These macros should only be used when CONFIG_FSL_CAAM is present. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Horia Geanta <horia.geanta@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | fsl-layerscape: do not use layerscape EFI reset if PSCI usedMathew McBride2019-11-081-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | If the secure world reset handlers are used (via CONFIG_PSCI_RESET), then do not use the layerscape-specific implementation. Signed-off-by: Mathew McBride <matt@traverse.com.au> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | armv8: dts: ls1088a: add PSCI binding for LS1088AMathew McBride2019-11-081-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This allows the use of PSCI calls to trusted firmware to initiate reset and poweroff events with CONFIG_PSCI_RESET and CONFIG_ARM_PSCI_FW. This is desirable, for example, if the target board has implemented a custom reset or poweroff procedure in EL3. Signed-off-by: Mathew McBride <matt@traverse.com.au> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* | | Merge branch '2019-11-07-master-imports'Tom Rini2019-11-086-0/+149
|\ \ \ | | | | | | | | | | | | | | | | | | | | - Add Phytium Durian Board - Assorted bugfixes - Allow for make ERR_PTR/PTR_ERR architecture specific
| * | | arm: add initial support for the Phytium Durian Boardliu hao2019-11-073-0/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds platform code and the device tree for the Phytium Durian Board. The initial support comprises the UART and the PCIE. Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Kever Yang <kever.yang@rock-chips.com> Cc: Tom Rini <trini@konsulko.com> Cc: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Steven Hao <liuhao@phytium.com.cn>
| * | | arm: caches: Disable mmu only if mmu is availableLokesh Vutla2019-11-071-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As part of disabling caches MMU as well gets disabled. But MMU is not available on all armv7 cores like R5F. So disable MMU only if it is available. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * | | arm: socfpga: gen5: fix ERR_PTR_OFFSETSimon Goldschmidt2019-11-071-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The default implementation of ERR_PTR/PTR_ERR maps errno values at the and of the address range (e.g. -EINVAL/-22 gets 0xFFFFFFEA). For socfpga gen5 SPL, this doesn't really work, as the heap is nearly at the end of the 32 bit address range. This patch adjusts the ERR_PTR_OFFSET to map errno values into the range of the Boot ROM, which should not be used for valid pointers. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
generated by cgit (git 2.34.1) at 2025-03-04 07:35:33 +0000