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* pci: sandbox: Move the emulators into their own nodeSimon Glass2019-10-082-16/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Sandbox pci works using emulation drivers which are currently children of the pci device: pci-controller { pci@1f,0 { compatible = "pci-generic"; reg = <0xf800 0 0 0 0>; emul@1f,0 { compatible = "sandbox,swap-case"; }; }; }; In this case the emulation device is attached to pci device on address f800 (device 1f, function 0) and provides the swap-case functionality. However this is not ideal, since every device on a PCI bus has a child device. This is only really the case for sandbox, but we want to avoid special-case code for sandbox. Worse, child devices cannot be probed before their parents. This forces us to use 'find' rather than 'get' to obtain the emulator device. In fact the emulator devices are never probed. There is code in sandbox_pci_emul_post_probe() which tries to track when emulators are active, but at present this does not work. A better approach seems to be to add a separate node elsewhere in the device tree, an 'emulation parent'. This could be given a bogus address (such as -1) to hide the emulators away from the 'pci' command, but it seems better to keep it at the root node to avoid such hacks. Then we can use a phandle to point from the device to the correct emulator, and only on sandbox. The code to find an emulator does not interfere with normal pci operation. Add a new UCLASS_PCI_EMUL_PARENT uclass which allows finding an emulator given a bus, and finding a bus given an emulator. Update the existing device trees and the code for finding an emulator. This brings PCI emulators more into line with I2C. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: fix 3 typos in the commit message; encode bus number in the labels of swap_case_emul nodes; mention commit 4345998ae9df in sandbox_pci_get_emul()] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* sandbox: Allow use of real I/O with readl(), etc.Simon Glass2019-10-083-9/+72
| | | | | | | | | | | | | | At present these functions are stubbed out. For more comprehensive testing with PCI devices it is useful to be able to fully emulate I/O access. Add simple implementations for these. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: change to use 'const void *' in sandbox_write(); cast 'addr' in read/write macros in arch/sandbox/include/asm/io.h; remove the unnecessary cast in readq/writeq in nvme.h] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* sandbox: pci: Increase the memory spaceSimon Glass2019-10-081-1/+1
| | | | | | | | Increase the memory space so we can support the p2sb bus which needs multiples of 1MB. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* sandbox: Add a -T flag to use the test device treeSimon Glass2019-10-081-0/+25
| | | | | | | | | | | | | | | | | U-Boot already supports using -D to indicate that it should use the normal device tree. It is sometimes useful to run with the test device tree, e.g. when running a test. Add a -T option for this along with some documentation. It can be used like this: /tmp/b/sandbox/u-boot -T -c "ut dm pci_busdev" (this will use /tmp/b/sandbox/arch/sandbox/dts/test.dtb as the DT) Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* sandbox: Add support for clrsetio_32() and friendsSimon Glass2019-10-082-12/+42
| | | | | | | | These functions are available on x86 but not sandbox. They are useful shortcuts and clarify the code, so add them to sandbox. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* sandbox: Rename PCI ID for swap_case to be more specificSimon Glass2019-10-081-1/+1
| | | | | | | | | Rename this ID to SANDBOX_PCI_SWAP_CASE_EMUL_ID since it is more descriptive and allows us to add new PCI emulators without any conflict or confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* sandbox: spmi: Add ranges property for address translationSimon Glass2019-10-081-0/+2
| | | | | | | | | | | | | | | At present address translation does not work since there is no ranges property in the spmi nodes. Add empty ranges properties and a little more logging so that this shows the error: /tmp/b/sandbox/u-boot -d /tmp/b/sandbox/arch/sandbox/dts/test.dtb \ -c "ut dm spmi_access_peripheral" -L7 -v ... pm8916_gpio_probe() bad address: returning err=-22 Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* dm: core: Add device_foreach_child()Simon Glass2019-10-081-2/+2
| | | | | | | | We have a 'safe' version of this function but sometimes it is not needed. Add a normal version too and update a few places that can use it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Rename turbo ratio MSR to MSR_TURBO_RATIO_LIMITSimon Glass2019-10-082-3/+2
| | | | | | | | | | This MSR number is used on most modern Intel processors, so drop the confusing NHM prefix (which might mean Nehalem). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: drop MSR_IVT_TURBO_RATIO_LIMIT as no code uses it] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add various MTRR indexes and valuesSimon Glass2019-10-082-0/+23
| | | | | | | | Add some new MTRRs used by Apollolake as well as a mask for the MTRR type. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add more comments to the start-up codeSimon Glass2019-10-083-3/+17
| | | | | | | | The full start-up sequence (TPL->SPL->U-Boot) can be a bit confusing since each phase has its own 'start' file. Add comments to explain this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Change condition for using CARSimon Glass2019-10-082-2/+10
| | | | | | | | | | | | | | | | | At present we assume that CAR (Cache-as-RAM) is used if HOBs (Hand-off blocks) are not, since HOBs typically indicate that an FSP is in use, and FSPs handle the CAR init. However this is a bit indirect, and for FSP2 machines which use their own CAR implementation (such as apollolake) but use the FSP for other functions, the logic is wrong. To fix this, add a dedicated Kconfig option to indicate when CAR is used. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: fix a typo in the commit message] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* x86: fsp: Save usable RAM and hob_list in the handoff areaSimon Glass2019-10-083-0/+24
| | | | | | | | | | | | | | The useable RAM is calculated when the RAM is inited. Save this value so that it can be easily used in U-Boot proper. Also save a pointer to the hob list so that it is accessible (before relocation only) in U-Boot proper. This avoids having to scan it in SPL, for everything U-Boot proper might need later. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: guard handoff_arch_save() with IS_ENABLED(CONFIG_USE_HOB)] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* x86: spl: Move broadwell-specific code out of generic x86 splSimon Glass2019-10-083-5/+12
| | | | | | | | | When TPL is running, broadwell needs to do different init from SPL. There is no need for this code to be in the generic x86 SPL file, so move it to arch_cpu_init(). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: spl: Reduce priority of the basic SPL image loaderSimon Glass2019-10-083-6/+6
| | | | | | | | | | | | | | This image loader works on systems where the flash is directly mapped to the last part of the 32-bit address space. On recent Intel systems (such as apollolake) this is not the case. Reduce the priority of this loader so that another one can override it. While we are here, rename the loader to BOOT_DEVICE_SPI_MMAP since BOOT_DEVICE_BOARD is not very descriptive. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: spl: Use hang() instead of a while() loopSimon Glass2019-10-082-4/+2
| | | | | | | | Use the standard hang() function when booting fails since this implements the defined U-Boot behaviour for this situation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: pci: Add a function to clear and set PCI config regsSimon Glass2019-10-082-0/+59
| | | | | | | | | | At present the x86 pre-DM equivalent of pci_bus_clrset_config32() does not exist. Add it to simplify PCI init code on x86. Also add the missing functions to this header. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add binman symbols to the imageSimon Glass2019-10-081-0/+6
| | | | | | | | | It is useful in SPL and TPL to access symbols from binman, such as the position and size of an entry in the ROM. Collect these symbols together in the SPL binaries. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Move common Intel CPU info code into a functionSimon Glass2019-10-084-14/+32
| | | | | | | | | Add cpu_intel_get_info() to find out the CPU info on modern Intel CPUs. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: add parameter and return value descriptions] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* x86: fsp: Add access to variable MRC dataSimon Glass2019-10-083-0/+23
| | | | | | | | | With FSP2 the non-volatile storage used by the FSP to init memory can be split into a fixed piece (determined at compile time) and a variable piece (determined at run time). Add support for reading the latter. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: fsp: Add a few more definitions for FSP2Simon Glass2019-10-081-1/+14
| | | | | | | Add definitions for the FSP signature and the FSP init phase. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: fsp: Move common support functions into a common fileSimon Glass2019-10-083-167/+177
| | | | | | | | | Some of this file can be shared between FSP1 and FSP2. Move it into a shared file. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Move common fsp functions into a common fileSimon Glass2019-10-085-97/+122
| | | | | | | | | Some of this file can be shared between FSP1 and FSP2. Move it into a shared file. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* x86: fsp: Move common dram functions into a common fileSimon Glass2019-10-085-77/+111
| | | | | | | | | | | Most of the DRAM functionality can be shared between FSP1 and FSP2. Move it into a shared file. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/next to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* x86: fsp: Tidy up comment style a littleSimon Glass2019-10-084-44/+54
| | | | | | | | | | | The comments in the FSP code use a different style from the rest of the x86 code. I am not sure it this is intentional. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: fix 2 comment style issues] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* x86: fsp: Use if() instead of #ifdefSimon Glass2019-10-082-8/+6
| | | | | | | | | | Update a few #ifdefs to if() to improve build coverage. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: recover the codes that got wrongly deleted in dram_init()] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* x86: fsp: Create a common fsp_support.h headerSimon Glass2019-10-082-116/+128
| | | | | | | | | | | Many support functions are common between FSP1 and FSP2. Add a new header to handle this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: remove forward declarations in fsp_support.h] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Rename some FSP functions to have an fsp_ prefixSimon Glass2019-10-087-19/+19
| | | | | | | | | Given these exported function an fsp_ prefix since they are declared in an fsp.h header. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* spl: Add an arch-specific hook for writing to SPL handoffSimon Glass2019-10-081-0/+7
| | | | | | | | | | | | At present there is an arch-specific area in the SPL handoff area intended for use by arch-specific code, but there is no explicit call to fill in this data. Add a hook for this. Also use the hook to remove the sandbox-specific test code from write_spl_handoff(). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Move fsp_ffs.h include to fsp_arch.hSimon Glass2019-10-081-0/+1
| | | | | | | | | This include file is only used for FSP v1. Avoid including it from fdt_support.h so we can use the latter with FSP v2. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Move fsp_bootmode.h to the generic fsp directorySimon Glass2019-10-082-1/+1
| | | | | | | | | This header file is the same for FSP v1 and v2, although there may be some additions to come. Move it into the generic fsp directory. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Move fsp_infoheader.h to the generic fsp directorySimon Glass2019-10-082-1/+1
| | | | | | | | | | | This header file is the same for FSP v1 and v2. Move it into the general fsp directory. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: move rename of fsp_infoheader.h from previous patch to this one] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Move fsp_hob.h to the generic fsp directorySimon Glass2019-10-082-1/+1
| | | | | | | | | | | This header file is the same for FSP v1 and v2. Move it into the general fsp directory. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: remove inclusion of fsp_hob.h in fsp_support.h] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Move fsp_fv.h to the generic fsp directorySimon Glass2019-10-082-1/+1
| | | | | | | | | This header file is the same for FSP v1 and v2. Move it into the general fsp directory. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Move fsp_types.h to the generic fsp directorySimon Glass2019-10-082-1/+1
| | | | | | | | | This header file is the same for FSP v1 and v2. Move it into the general fsp directory. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Move fsp_api.h inclusion out of fsp_support.hSimon Glass2019-10-082-1/+1
| | | | | | | | | This header file is different for each version of FSP. Move it into the fsp_arch.h header file. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Create a new fsp_arch.h headerSimon Glass2019-10-082-2/+21
| | | | | | | | | | | | | At present fsp_support.h includes fsp_vpd.h which is an FPSv1 concept (VPD means Vital Product Data). For FSPv2 only UPD (Updatable Product Data) is used. To avoid mangling header files, put these two includes in a separate header which we can adjust as necessary for FSPv2. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Move fsp_azalia.h to the generic fsp directorySimon Glass2019-10-082-2/+1
| | | | | | | | | | | This header file is the same for FSP v1 and v2. Move it into the general fsp directory. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: remove forward declarations in fsp_support.h] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Rename existing FSP code to fsp1Simon Glass2019-10-0824-13/+37
| | | | | | | | | | | | | | | Since there is now a new version of the FSP and it is incompatible with the existing version, move the code into an fsp1 directory. This will allow us to put FSP v2 code into an fsp2 directory. Add a Kconfig which defines which version is in use. Some of the code in this new fsp1/ directory is generic across both FSPv1 and FSPv2. Future patches will address this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* NET: DW: fix regression for ARC boardsEugeniy Paltsev2019-10-072-2/+2
| | | | | | | | | | | | | The commit 642b80d256e ("net: designware: drop compatible altr, socfpga-stmmac") breaks designware ethernet for all ARC boards. It removes "altr, socfpga-stmmac" compatible from "drivers/net/designware.c" without changing compatible in the boards which use it. Fix that by adding "snps,arc-dwmac-3.70a" compatible string to "drivers/net/designware.c" and using it in ARC boards device tree. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
* Merge branch 'master' of git://git.denx.de/u-boot-shTom Rini2019-10-057-0/+44
|\ | | | | | | - ARM: dts: rmobile: Restore increase off-on delay on the SD Vcc regulator
| * ARM: dts: rmobile: Restore increase off-on delay on the SD Vcc regulatorMarek Vasut2019-09-307-0/+44
| | | | | | | | | | | | | | | | | | | | | | This patch restores commit c49d0ac38a76 ("ARM: dts: rmobile: Increase off-on delay on the SD Vcc regulator"), which was accidentally dropped during DT resync in commit 317d13ac6307 ("ARM: dts: rmobile: Synchronize Gen3 DTs with Linux 5.0"). Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Fixes: 317d13ac6307 ("ARM: dts: rmobile: Synchronize Gen3 DTs with Linux 5.0")
* | ARM: dts: imx6q-logicpd: Add missing imx6q-logicpd-u-boot for SPLAdam Ford2019-10-041-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | The SPL device tree is missing the entires for gpio1, uart1, usdhc1 and usdhc2. This creates the missing imx6q-logicpd-u-boot.dtsi file which will enable these functions so SPL can properly setup UART, detect microSD card, and startup. Fixes: 8f4691e31a18 ("ARM: imx6q_logic: With SPL_OF_CONTROL enabled, remove MMC init") Signed-off-by: Adam Ford <aford173@gmail.com>
* | board: ti: am654: Disable TRNG node for HS devicesAndrew F. Davis2019-10-042-0/+22
| | | | | | | | | | | | | | | | On HS devices the access to TRNG is restricted on the non-secure ARM side, disable the node in DT to prevent firewall violations. Signed-off-by: Andrew F. Davis <afd@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
* | arm: K3: Increase default SYSFW image size allocationAndrew F. Davis2019-10-041-1/+1
| | | | | | | | | | | | | | | | | | | | The memory allocated to store the FIT image containing SYSFW and board configuration data is statically defined to the largest size expected. This was 269000 bytes but now needs to be grown to 276000 to make room for the signatures attached to the board configuration data on High Security devices. Signed-off-by: Andrew F. Davis <afd@ti.com>
* | x86: zImage: Propagate acpi_rsdp_addr to kernel via boot parametersAndy Shevchenko2019-10-012-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is reincarnation of the U-Boot commit 3469bf4274540d1491d58e878a9edc0bdcba17ac Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Date: Wed Jan 10 19:40:15 2018 +0200 x86: zImage: Propagate acpi_rsdp_addr to kernel via boot parameters after upstream got eventually the Linux kernel commit e6e094e053af75cbc164e950814d3d084fb1e698 Author: Juergen Gross <jgross@suse.com> Date: Tue Nov 20 08:25:29 2018 +0100 x86/acpi, x86/boot: Take RSDP address from boot params if available Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | rockchip: make_fit_atf.py: fix .its generation for a single atf imageHeiko Stuebner2019-09-281-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The commit 619f002db864 ("rockchip: make_fit_atf.py: fix loadables property set error") fixed the double-loading of the primary atf-image, but didn't take into account that there may be rare atf images with only that main section present. Right now this will result in a broken its due to the loadables section not getting closed correctly, so fix that by adapting the guards around the loop. The guards now protect against 0 segments when the bl31 binary doesn't contain any section and 1 segment when only a core atf section is present. Fixes: 619f002db864 ("rockchip: make_fit_atf.py: fix loadables property set error") Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
* | rockchip: misc: read the correct number of bytes from the efuseHeiko Stuebner2019-09-281-1/+1
|/ | | | | | | | | | | | | | | | | | Originally the cpuid var the value gets read into was defined as u8 cpuid[RK3399_CPUID_LEN]; hence the sizeof(cpuid) would return the correct the correct number of array elements. With the move to a separate function cpuid becomes a pointer and sizeof(cpuid) hence returns the pointer size - 8 in the arm64 case. We do have the actual id length available as function param so use it for actual amount of bytes to read. Fixes: 04825384999f ("rockchip: rk3399: derive ethaddr from cpuid") Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
* rockchip: rk3288-tinker: Attach missing peripherals at SPLMichael Trimarchi2019-09-191-7/+19
| | | | | | | | | | | Tinker board needs to mux all the sdmmc gpio and activate the regulator connected to bank 7. Remove all the bank that are not in use and mark them as dm,spl so-that it would initialize at SPL. Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
* rockchip: spi-boot-order: Trival fix to newline missingJagan Teki2019-09-191-1/+1
| | | | | | | newline \n was missed in fdt_path_offset, error loop. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
generated by cgit (git 2.34.1) at 2024-11-12 21:20:13 +0000