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* watchdog: tangier: Convert to use WDT classAndy Shevchenko2019-06-222-1/+4
| | | | | | | Convert legacy driver to use watchdog class. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Stefan Roese <sr@denx.de>
* x86: Revert "Don't set up MTRRs in SPL"Andy Shevchenko2019-06-221-4/+1
| | | | | | | | | | This breaks Intel Edison to work. It gets laggish and unable to boot kernel. Reverts commit 665cb18ea64aabbeb03d27a4c92ddec1baccb87a for now till better solution will be proposed. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Bin Meng <bmeng.cn@gmail.com>
* x86: coreboot: make it possible to process unhandled tagsChristian Gmeiner2019-05-191-0/+7
| | | | | | | | | | coreboot makes it possible to add own entries into coreboot's table at a per mainboard basis. As there might be some custom ones it makes sense to provide a way to process them. Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* Fix spelling of available.Vagrant Cascadian2019-05-093-3/+3
| | | | Signed-off-by: Vagrant Cascadian <vagrant@debian.org>
* x86: samus: Update device tree for verified bootSimon Glass2019-05-081-1/+21
| | | | | | | | Add nvdata drivers for the TPM and RTC as used on samus. These are needed for Chromium OS verified boot on samus. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: samus: Update device tree for SPLSimon Glass2019-05-081-3/+28
| | | | | | | Add tags to allow required nodes to be present in SPL / TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add a simple TPL implementationSimon Glass2019-05-084-5/+183
| | | | | | | | Add the required CPU code so that TPL builds correctly. Also update the SPL code to deal with being booted from TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add a way to jump from TPL to SPLSimon Glass2019-05-081-0/+13
| | | | | | | | When TPL finishes it needs to jump to SPL with the stack set up correctly. Add a function to handle this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: broadwell: Update PCH to work in TPLSimon Glass2019-05-081-3/+9
| | | | | | | | The early init should only happen once. Update the probe method to deal with TPL, SPL and U-Boot proper. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Fix device-tree indentationSimon Glass2019-05-081-74/+73
| | | | | | | | With the use of a phandle we can outdent the device tree nodes a little. Fix this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Update device tree for Chromium OS verified bootSimon Glass2019-05-081-2/+15
| | | | | | | | | | | The standard image generated by U-Boot on x86 is u-boot.rom. Add a separate image called image.bin for verified boot. This supports verification in TPL of which SPL/U-Boot to start, then jumping to the correct one, with SPL setting up the SDRAM and U-Boot proper providing the user interface if needed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Update device tree for TPLSimon Glass2019-05-081-2/+32
| | | | | | | | | Add TPL binaries to the device x86 binman desciption. When enabled, TPL will start first, doing the 16-bit init, then jump to SPL and finally U-Boot proper. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Don't generate a bootstage report in SPLSimon Glass2019-05-081-1/+1
| | | | | | | | This report is normally generated by U-Boot proper. Correct the condition here so that it respects the Kconfig options for bootstage. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Don't set up MTRRs in SPLSimon Glass2019-05-081-1/+4
| | | | | | | | The MTRRs are normally set up in U-Boot proper, so avoid setting them up in SPL as well. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Support TPL in Intel common codeSimon Glass2019-05-081-3/+6
| | | | | | | | Update the Makefie rules to ensure that the correct files are built when TPL is being used. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: broadwell: Implement PCH_REQ_PMBASE_INFOSimon Glass2019-05-081-0/+25
| | | | | | | Implement this ioctl() to support power off. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Implement PCH_REQ_PMBASE_INFOSimon Glass2019-05-081-0/+15
| | | | | | | Implement this ioctl() to support power off. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: mrccache: Add more debuggingSimon Glass2019-05-081-4/+12
| | | | | | | | When the MRC cache fails to save it is useful to have some debugging info to indicate what when wrong. Add some more debug() calls. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Support saving MRC data from SPLSimon Glass2019-05-082-9/+38
| | | | | | | | | When SPL is used to set up the memory controller we want to save the MRC data in SPL to avoid needing to pass it up to U-Boot proper to save. Add a function to handle that. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add common Intel code for SPLSimon Glass2019-05-082-0/+33
| | | | | | | | Add an implementation of arch_cpu_init_f() so that the x86 SPL code builds and identifies the CPU. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: broadwell: Select refcode and CPU code for SPLSimon Glass2019-05-081-3/+4
| | | | | | | Allow broadwell to build for SPL and include the reference code. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: broadwell: Allow booting from SPLSimon Glass2019-05-082-0/+78
| | | | | | | | | At present broadwell only supports booting straight into U-Boot proper. Add a separate init file to boot from SPL into U-Boot proper, and select it when SPL is in use. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Allow 16-bit init to be in TPLSimon Glass2019-05-083-4/+4
| | | | | | | | At present we support having 16-bit init be in SPL or U-Boot proper, but not TPL. Add support for this so that TPL can boot. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add support for starting from SPL/TPLSimon Glass2019-05-084-1/+146
| | | | | | | | | | | When a previous phase of U-Boot has run we need to adjust the init of subsequent states to avoid messing up the CPU state. Add a new version of the start logic for SPL, when it boots from TPL (start_from tpl.c) and a new version for U-Boot when it boots from SPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: broadwell: Split CPU initSimon Glass2019-05-083-673/+695
| | | | | | | | | Split the CPU init into two parts - the 'full' init which happens in the first U-Boot phase, and the rest of the init that happens on subsequent stages. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: broadwell: Move init of debug UART to cpu.cSimon Glass2019-05-082-11/+13
| | | | | | | | | | | At present the debug UART is set up in sdram.c which is not the best place since it has nothing in particular to do with SDRAM. Since we want to support initing this in SPL too, move it to a common file. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: added 'broadwell' tag in the commit title] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* x86: broadwell: Allow SDRAM init from SPLSimon Glass2019-05-083-94/+101
| | | | | | | | | | | | | At present, for broadwell, SDRAM is always set up in U-Boot proper since the 64-bit mode (which uses SDRAM init in SPL) is not supported. Update the code to allow SDRAM init in SPL instead so that U-Boot proper can be loaded into SDRAM and run from there. This allows U-Boot to be compressed to reduce space, since it is not necessary to run it directly from flash. It could later allow us to support 64-bit U-Boot on broadwell. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: broadwell: Improve SDRAM debugging outputSimon Glass2019-05-081-12/+20
| | | | | | | | Add debugging during SDRAM init so that problems are easier to diagnose. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add a handoff header fileSimon Glass2019-05-081-0/+15
| | | | | | | | Add an arch-specific handoff header so that we can use the HANDOFF feature on x86 devices. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Support booting with TPLSimon Glass2019-05-081-1/+8
| | | | | | | | | | | Some boards want to use TPL as the first phase of U-Boot. This allows selection of A or B SPL phases, thus allowing the memory init to be upgraded in the field. Add a new Kconfig option for this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Support SPL and TPLSimon Glass2019-05-081-1/+0
| | | | | | | | | | | At present only chromebook_link64 supports SPL. It is useful to eb able to support both TPL and SPL to implement verified boot on x86. Enable the options for both along with some suitable default options needed to boot through these phases. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: dts: Add device-tree labels for rtc and resetSimon Glass2019-05-082-2/+2
| | | | | | | Add labels for these nodes so that board DT files can reference them. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add a way to reinit the cpuSimon Glass2019-05-083-44/+94
| | | | | | | | | We cannot init the CPU fully both than once during a boot. Add a new function which can be called to figure out the CPU identity, but which does not change anything. For x86_64, this is empty for now. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: mp_init: Use proper error numbersSimon Glass2019-05-081-5/+5
| | | | | | | | At present many of the functions in this file return -1 as an error number. which is -EPERM. Update the code to use real error numbers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Update a stale comment about ifdtoolSimon Glass2019-05-082-2/+2
| | | | | | | | We use binman to build the x86 image now. Update a comment which still refers to ifdtool. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: start64: Fix copyright messageSimon Glass2019-05-081-1/+1
| | | | | | | There is a typo in this header. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: dts: switch spi-flash to jedec, spi-nor compatibleNeil Armstrong2019-04-1212-12/+12
| | | | | | | | | | The x86 code and DT uses "spi-flash" to detect a flash node, switch to "jedec,spi-nor" in the DTS files and in fdtdec by switching the GENERIC_SPI_FLASH value to to jedec,spi-nor. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
* x86: crownbay: Enable the beeper sound driverBin Meng2019-03-111-0/+1
| | | | | | | Use the i8254 sound driver to support creating simple beeps. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: coreboot: Add the missing pc speaker node in the device treeBin Meng2019-03-111-0/+1
| | | | | | | | This is currently missing and without it the i8254 beeper driver won't work. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: Add a dtsi file for the pc speakerBin Meng2019-03-111-0/+5
| | | | | | | | The pc speaker driven by the i8254 is generic enough to deserve a single dtsi file to be included by boards that use it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: Make sure i8254 is setup correctly before generating beepsBin Meng2019-03-111-0/+4
| | | | | | | | | | | | The i8254 timer control IO port (0x43) should be setup correctly by using PIT counter 2 to generate beeps, however in U-Boot other codes like TSC driver utilizes PIT for TSC frequency calibration and configures the counter 2 to a different mode that does not beep. Fix this by always ensuring the PIT counter 2 is correctly initialized so that the i8254 beeper driver works as expected. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: edison: Add the rest of UARTs present on boardAndy Shevchenko2019-03-101-0/+18
| | | | | | | | | | | | Intel Edison has three UART ports, i.e. port 0 - Bluetooth port 1 - auxiliary, available for general purpose use port 2 - debugging, usually console output is here Enable all of them for future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: edison: Use proper number of serial interfaceAndy Shevchenko2019-03-101-3/+3
| | | | | | | | | | The console is actually serial #2. When we would like to enable other ports, this would be not okay to mess up with the ordering. Thus, fix the number of default console interface to be 2. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: acpi: Not every platform has serial console a first deviceAndy Shevchenko2019-03-101-3/+3
| | | | | | | | | | | | | | | We may not do an assumption that current console device is always a first of UCLASS_SERIAL one. For example, on properly described Intel Edison board the console UART is a third one. Use current serial device as described in global data. Fixes: a61cbad78e67 ("dm: serial: Adjust serial_getinfo() to use proper API") Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: acpi: Add DMA descriptors for I2C1 on Intel TangierAndy Shevchenko2019-03-101-0/+11
| | | | | | | | | | | | Intel Tangier SoC has a general purpose DMA which can serve to speed up communications on SPI and I2C serial buses. Provide DMA descriptors to utilize this capability in the future. Note, I2C6, which is available to user, has no DMA request lines connected. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: acpi: Add DMA descriptors for SPI5 on Intel TangierAndy Shevchenko2019-03-101-0/+3
| | | | | | | | | | Intel Tangier SoC has a general purpose DMA which can serve to speed up communications on SPI and I2C serial buses. Provide DMA descriptors to utilize this capability in the future. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add sound support for samusSimon Glass2019-02-201-4/+45
| | | | | | | Enable sound on samus using the broadwell I2S and an RT5677 audio codec. Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: broadwell: Add support for serial I/O devicesSimon Glass2019-02-202-0/+192
| | | | | | | | Add support for initing the I2C device and ADSP on broadwell. These are needed for sound to work. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: broadwell: Don't bother probing the PCH for pinctrlSimon Glass2019-02-201-1/+2
| | | | | | | | | | | | At present the pinctrl probes the PCH but since it only uses it to obtain a PCI address, this is no necessary. Avoiding this fixes one of the two co-dependent loops in broadwell. This driver really should be a proper pinctrl driver, but for now it remains a syscon device. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: broadwell: Add support for the ADSPSimon Glass2019-02-205-0/+208
| | | | | | | | The Application Digital Signal Processor is used for sound processing with broadwell. Add a driver to support this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
generated by cgit (git 2.34.1) at 2025-02-07 09:49:57 +0000