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* Revert "x86: Convert MMC to driver model"Bin Meng2017-06-274-1/+43
| | | | | | | | | | | | | This reverts commit ddb3ac3c716f56cead695444e65a7ba7b0946555. With MMC converted to driver model, SCSI driver is broken due to zero address access at (ops->read) in block_dread() function. The fix (SCSI driver converted to DM) is ready in u-boot-dm branch, but it is too late for this relese to get that in. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: Don't include asm/u-boot.h in commonSimon Glass2017-06-051-1/+3
| | | | | | | With a small fixup to u-boot-x86.h, this is not actually needed anywhere, so drop it. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Make u-boot-x86.h a private headerSimon Glass2017-06-051-0/+1
| | | | | | | | | | Rather than including this arch-specific header file in common.h, include it from within x86's u-boot.h header. Also drop the comment about something to be fixed. It is not clear what needs fixing. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: fsp: Remove the call to set up internal uart in fsp_init()Bin Meng2017-06-051-4/+0
| | | | | | | | | | | | First of all, it's inappropriate to call setup_internal_uart() in a generic API fsp_init(), as CONFIG_INTERNAL_UART is an option that is only available on BayTrail platform. Secondly even for BayTrail, there is no need to call setup_internal_uart() at all, as Intel FSP will do this for us. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: baytrail: Fix boot hang with a debug buildBin Meng2017-06-052-0/+9
| | | | | | | | | | | | It was observed that when -DDEBUG is used to generate a debug build, U-Boot does not boot on MinnowMax board. A workaround is to disable CONFIG_DEBUG_UART. The real issue is that in order to have the debug uart to work, BayTrail SoC needs to be configured so that its internal uart is available to be used as the debug uart. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: baytrail: Change lpe/lpss-sio/scc FSP properties to integerBin Meng2017-06-058-22/+33
| | | | | | | | | | | | At present lpe/lpss-sio/scc FSP properties are all boolean, but in fact for "enable-lpe" it has 3 possible options. This adds macros for these options and change the property from a boolean type to an integer type, and change their names to explicitly indicate what the property is really for. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: baytrail: Use macros instead of magic numbers for FSP settingsBin Meng2017-06-057-72/+159
| | | | | | | | | Introduce various meaningful macros for FSP settings and switch over to use them instead of magic numbers. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: baytrail: Remove "serial-debug-port-*" settingsBin Meng2017-06-055-12/+1
| | | | | | | | | "serial-debug-port-address" and "serial-debug-port-type" settings are actually reserved in the FSP UPD data structure. Remove them. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: baytrail: Change "fsp, mrc-init-tseg-size" default value to 1Bin Meng2017-06-056-6/+6
| | | | | | | | | The default value of "fsp,mrc-init-tseg-size" should be 1 (1MB) per FSP default settings. 0 is not valid. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: minnowmax: Remove incorrect pad-offset of several pinsBin Meng2017-05-171-5/+0
| | | | | | | | | | | Remove 'pad-offset' of soc_gpio_s5_0, soc_gpio_s5_1, soc_gpio_s5_2, pin_usb_host_en0 and pin_usb_host_en1. These offsets are actually wrong. Correct value should be added by 0x2000, but since they are supposed to be 'mode-gpio', 'pad-offset' is not needed at all. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: ich6_gpio: Add use-lvl-write-cache for I/O access modeBin Meng2017-05-175-0/+30
| | | | | | | | | | | | | | | | | | | | Add a device-tree property use-lvl-write-cache that will cause writes to lvl to be cached instead of read from lvl before each write. This is required on some platforms that have the register implemented as dual read/write (such as Baytrail). Prior to this fix the blue USB port on the Minnowboard Max was unusable since USB_HOST_EN0 was set high then immediately set low when USB_HOST_EN1 was written. This also resolves the 'gpio clear | set' command warning like: "Warning: value of pin is still 0" Signed-off-by: George McCollister <george.mccollister@gmail.com> <rebased on latest origin/master, fixed all baytrail boards> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: bootm: Add dm_remove_devices_flags() call to bootm_announce_and_cleanup()Stefan Roese2017-05-171-0/+9
| | | | | | | | | | | This patch adds a call to dm_remove_devices_flags() to bootm_announce_and_cleanup() so that drivers that have one of the removal flags set (e.g. DM_FLAG_ACTIVE_DMA_REMOVE) in their driver struct, may do some last-stage cleanup before the OS is started. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: Convert MMC to driver modelSimon Glass2017-05-174-43/+1
| | | | | | | | | Convert the pci_mmc driver over to driver model and migrate all x86 boards that use it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* x86: acpi: Fix Windows S3 resume failureBin Meng2017-05-174-2/+71
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | U-Boot sets up the real mode interrupt handler stubs starting from address 0x1000. In most cases, the first 640K (0x00000 - 0x9ffff) system memory is reported as system RAM in E820 table to the OS. (see install_e820_map() implementation for each platform). So OS can use these memories whatever it wants. If U-Boot is in an S3 resume path, care must be taken not to corrupt these memorie otherwise OS data gets lost. Testing shows that, on Microsoft Windows 10 on Intel Baytrail its wake up vector happens to be installed at the same address 0x1000. While on Linux its wake up vector does not overlap this memory range, but after resume kernel checks low memory range per config option CONFIG_X86_RESERVE_LOW which is 64K by default to see whether a memory corruption occurs during the suspend/resume (it's harmless, but warnings are shown in the kernel dmesg logs). We cannot simply mark the these memory as reserved in E820 table because such configuration makes GRUB complain: unable to allocate real mode page. Hence we choose to back up these memories to the place where we reserved on our stack for our S3 resume work. Before jumping to OS wake up vector, we need restore the original content there. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Stefan Roese <sr@denx.de>
* x86: pci: Allow conditionally run VGA rom in S3Bin Meng2017-05-171-0/+12
| | | | | | | | | Introduce a new CONFIG_S3_VGA_ROM_RUN option so that U-Boot can bypass executing VGA roms in S3. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Stefan Roese <sr@denx.de>
* x86: acpi: Turn on ACPI mode for S3Bin Meng2017-05-171-0/+3
| | | | | | | | | Before jumping to OS waking up vector, we need turn on ACPI mode for S3, just like what we do for a normal boot. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Stefan Roese <sr@denx.de>
* x86: acpi: Refactor acpi_resume()Bin Meng2017-05-175-12/+33
| | | | | | | | | | | | | | | To do something more in acpi_resume() like turning on ACPI mode, we need locate ACPI FADT table pointer first. But currently this is done in acpi_find_wakeup_vector(). This changes acpi_resume() signature to accept ACPI FADT pointer as the parameter. A new API acpi_find_fadt() is introduced, and acpi_find_wakeup_vector() is updated to use FADT pointer as the parameter as well. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Stefan Roese <sr@denx.de>
* x86: acpi: Make enter_acpi_mode() publicBin Meng2017-05-172-1/+10
| | | | | | | | | enter_acpi_mode() is useful on other boot path like S3 resume, so make it public. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Stefan Roese <sr@denx.de>
* x86: apci: Change PM1_CNT register access to RMWBin Meng2017-05-171-1/+3
| | | | | | | | | | In enter_acpi_mode() PM1_CNT register is changed to PM1_CNT_SCI_EN directly without preserving its previous value. Update to change the register access to read-modify-write (RMW). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Stefan Roese <sr@denx.de>
* x86: Adjust board_final_cleanup() orderBin Meng2017-05-171-2/+2
| | | | | | | | | | Call board_final_cleanup() before write_tables(), so that anything done in board_final_cleanup() on a normal boot path is also done on an S3 resume path. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Stefan Roese <sr@denx.de>
* x86: Do not clear high table area for S3Bin Meng2017-05-171-1/+6
| | | | | | | | | | When SeaBIOS is being used, U-Boot reserves a memory area to be used for configuration tables like ACPI. But it should not be cleared otherwise ACPI table will be missing. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Stefan Roese <sr@denx.de>
* x86: fsp: Save stack address to CMOS for next S3 bootBin Meng2017-05-174-1/+89
| | | | | | | | | | At the end of pre-relocation phase, save the new stack address to CMOS and use it as the stack on next S3 boot for fsp_init() continuation function. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Stefan Roese <sr@denx.de>
* x86: Add an early CMOS access libraryBin Meng2017-05-173-0/+95
| | | | | | | | | This adds a library that provides CMOS (inside RTC SRAM) access at a very early stage when driver model is not available yet. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Stefan Roese <sr@denx.de>
* x86: acpi: Resume OS if resume vector is foundBin Meng2017-05-174-0/+45
| | | | | | | | | In an S3 resume path, U-Boot does everything like a cold boot except in the last_stage_init() it jumps to the OS resume vector. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Stefan Roese <sr@denx.de>
* x86: acpi: Add one API to find OS wakeup vectorBin Meng2017-05-173-0/+83
| | | | | | | | | This adds one API acpi_find_wakeup_vector() to locate OS wakeup vector from the ACPI FACS table, to be used in the S3 boot path. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Stefan Roese <sr@denx.de>
* x86: acpi: Add wake up assembly stubBin Meng2017-05-173-0/+88
| | | | | | | | This adds a wake up stub before jumping to OS wake up vector. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Stefan Roese <sr@denx.de>
* x86: fsp: Mark memory used by U-Boot as reserved in the E820 table for S3Bin Meng2017-05-172-0/+20
| | | | | | | | | | U-Boot itself as well as everything that is consumed by U-Boot (like heap, stack, dtb, etc) needs to be reserved and reported in the E820 table when S3 resume is on. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Stefan Roese <sr@denx.de>
* x86: baytrail: Conditionally report S3 in the ACPI tableBin Meng2017-05-172-1/+3
| | | | | | | | | When U-Boot is built without ACPI S3 support, it should not report S3 in the ACPI table otherwise when kernel does STR it won't work. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Stefan Roese <sr@denx.de>
* x86: Store and display previous sleep stateBin Meng2017-05-174-0/+23
| | | | | | | | | Add one member in the global data to store previous sleep state, and display the state during boot in print_cpuinfo(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Stefan Roese <sr@denx.de>
* x86: fsp: acpi: Pass different boot mode to FSP initBin Meng2017-05-172-1/+43
| | | | | | | | | When ACPI S3 resume is turned on, we should pass different boot mode to FSP init instead of default BOOT_FULL_CONFIG. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Stefan Roese <sr@denx.de>
* x86: Add post codes for OS resumeBin Meng2017-05-171-0/+2
| | | | | | | | This adds OS_RESUME (0x40) and RESUME_FAILURE (0xed) post codes. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Stefan Roese <sr@denx.de>
* x86: baytrail: acpi: Add APIs for determining/clearing sleep stateBin Meng2017-05-172-0/+71
| | | | | | | | | This adds APIs for determining previous sleep state from ACPI I/O registers, as well as clearing sleep state on BayTrail SoC. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Stefan Roese <sr@denx.de>
* x86: acpi: Add Kconfig option and header file for ACPI resumeBin Meng2017-05-172-0/+76
| | | | | | | | | This introduces a Kconfig option for ACPI S3 resume, as well as a header file to include anything related to ACPI S3 resume. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Stefan Roese <sr@denx.de>
* fs: Kconfig: Add a separate config for FS_CBFSSimon Glass2017-04-301-0/+1
| | | | | | | | | | | Rather than using CMD_CBFS for both the filesystem and its command, we should have a separate option for each. This allows us to enable CBFS support without the command, if desired, which reduces U-Boot's size slightly. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: imply FS_CBFS on SYS_COREBOOT] Signed-off-by: Tom Rini <trini@konsulko.com>
* fs: Convert CONFIG_CMD_CBFS to KconfigSimon Glass2017-04-301-0/+1
| | | | | | | | | This converts the following to Kconfig: CONFIG_CMD_CBFS Signed-off-by: Simon Glass <sjg@chromium.org> [trini: imply CMD_CBFS on SYS_COREBOOT] Signed-off-by: Tom Rini <trini@konsulko.com>
* x86: Display the SPL banner only onceSimon Glass2017-04-181-2/+1
| | | | | | | | | | | At present on a cold reboot we must reset the CPU to get it to full speed. With 64-bit U-Boot this happens in SPL. At present we print the banner before doing this, the end result being that we print the banner twice. Print the banner a little later (after the CPU is ready) to avoid this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Drop leading spaces in cpu_x86_get_desc()Simon Glass2017-04-181-1/+5
| | | | | | | | The Intel CPU name can have leading spaces. Remove them since they are not useful. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Introduce minimal PMU driver for Intel MID platformsAndy Shevchenko2017-04-104-0/+130
| | | | | | | | | | | | | This simple PMU driver allows to tyrn power on and off for selected devices. In particularly Intel Tangier needs to power on SDHCI controllers in order to access to them during board initialization. In the future it might be expanded to cover other Intel MID platforms, that's why it's located under arch/x86/lib and called pmu.c. Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: Add SCU IPC driver for Intel MID platformsFelipe Balbi2017-04-105-0/+200
| | | | | | | | | | | | Intel MID platforms have few microcontrollers inside SoC, one of them is so called System Controller Unit (SCU). Here is the driver to communicate with microcontroller. Signed-off-by: Vincent Tinelli <vincent.tinelli@intel.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: bootm: Fix FIT image booting on x86Stefan Roese2017-04-101-1/+1
| | | | | | | | | | | | | | | | Checking 'is_zimage' at this time will always fail and therefore booting a FIT style image will always lead to this error message: "## Kernel loading failed (missing x86 kernel setup) ..." This change now removes this check and booting of FIT images works just fine. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add file names from Kconfig in descriptor/intel-me nodes in u-boot.dtsiStefan Roese2017-04-101-0/+2
| | | | | | | | | | | Since we now have the file names configurable via Kconfig for the flash descriptor and intel-me files, add these from Kconfig in the corresponding dts nodes. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Kconfig: Add options to configure the descriptor.bin / me.bin filenamesStefan Roese2017-04-101-0/+16
| | | | | | | | | | This introduces two Kconfig options to enable board specific filenames for the Intel binary blobs to be used to generate the SPI flash image. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* board_f: Make relocation functions genericSimon Glass2017-04-052-18/+1
| | | | | | | This header file is used by three archs. It could be used by all of them since relocation is a common function. Move it into a generic file. Signed-off-by: Simon Glass <sjg@chromium.org>
* board_f: Make init_helpers genericSimon Glass2017-04-052-14/+1
| | | | | | | | This header file is used by two archs. It could be used by all of them since it allows the cache to be on during relocation. Move it into a generic file. Signed-off-by: Simon Glass <sjg@chromium.org>
* Move dram_init_banksize() to a common headerSimon Glass2017-04-051-1/+0
| | | | | | | | This is an weak function present on all archs so we should have it in the common header file. Remove it from arch-specific headers and add a function comment. Signed-off-by: Simon Glass <sjg@chromium.org>
* board_f: Drop setup_dram_config() wrapperSimon Glass2017-04-059-10/+26
| | | | | | | | By making dram_init_banksize() return an error code we can drop the wrapper. Adjust this and clean up all implementations. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de>
* board_f: x86: Use checkcpu() for CPU initSimon Glass2017-04-059-7/+55
| | | | | | | | | | | | | At present we misuse print_cpuinfo() do so CPU init on x86. This is done because it is the next available call after the console is enabled. But several arches use checkcpu() instead. Despite the horrible name (which we can fix), it seems a better choice. Adjust the various x86 CPU implementations to move their init code into checkcpu() and use print_cpuinfo() only for printing CPU info. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de>
* board_f: x86: Rename x86_fsp_init() to arch_fsp_init()Simon Glass2017-04-052-4/+1
| | | | | | | | | | | | While x86 is the only user and this could in principle be moved to arch_cpu_init() there is some justification for this being a separate call. It provides a way to handle init which is not CPU-specific, but must happen before the CPU can be set up. Rename the function to be more generic. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de>
* dm: core: Add flags parameter to device_remove()Stefan Roese2017-04-041-2/+2
| | | | | | | | | | | | | This patch adds the flags parameter to device_remove() and changes all calls to this function to provide the default value of DM_REMOVE_NORMAL for "normal" device removal. This is in preparation for the driver specific pre-OS (e.g. DMA cancelling) remove support. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Intel MID platforms has no microcode updateAndy Shevchenko2017-02-211-1/+2
| | | | | | | | | | | There is no microcode update available for SoCs used on Intel MID platforms. Use conditional to bypass it. Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
generated by cgit (git 2.34.1) at 2024-11-06 01:15:27 +0000