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* x86: ivybridge: Drop the special PCI driverSimon Glass2016-01-242-47/+0
| | | | | | | | There is nothing special about the ivybridge pci driver now, so just use the generic one. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Move LPC init into the LPC probe() methodSimon Glass2016-01-242-12/+9
| | | | | | | | Drop the lpc_init_extra() function and just use the post-relocation LPC probe() instead. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Move lpc_enable() into gma.cSimon Glass2016-01-243-8/+4
| | | | | | | | This graphics init code is best placed in the gma init code. Move the code and drop the function. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Use driver model PCI API in sata.cSimon Glass2016-01-241-49/+45
| | | | | | | Adjust the functions in this file to use the driver model PCI API. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Use the SATA driver to do the initSimon Glass2016-01-242-9/+8
| | | | | | | | Instead of manually initing the device, probe the SATA device and move the init there. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Drop the unused bd82x6x_init_extra()Simon Glass2016-01-242-17/+0
| | | | | | | This function does nothing now so can be dropped. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Do the SATA init before relocationSimon Glass2016-01-243-3/+27
| | | | | | | | | The SATA device needs to set itself up so that it appears correctly on the PCI bus. The easiest way to do this is to set it up to probe before relocation. This can do the early setup. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Drop unnecessary northbridge setupSimon Glass2016-01-241-20/+0
| | | | | | | This is done by default with PCI auto-config. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Use driver model PCI API in bd82x6x.cSimon Glass2016-01-241-13/+7
| | | | | | | | | Adjust most of the remaining functions in this file to use the driver model PCI API. The one remaining function is bridge_silicon_revision() which will need a little more work. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Move northbridge and PCH init into driversSimon Glass2016-01-242-46/+12
| | | | | | | | | | Instead of calling the northbridge and PCH init from bd82x6x_init_extra() when the PCI bus is probed, call it from the respective drivers. Also drop the Northbridge init as it has no effect. The registers it touches appear to be read-only. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Move early init code into northbridge.cSimon Glass2016-01-243-82/+67
| | | | | | | | This code is now part of the northbridge driver, so move it into the same place. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Drop the dead MTRR codeSimon Glass2016-01-241-10/+0
| | | | | | | This is not used and MTRRs are set up elsewhere now. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Set up the thermal target correctlySimon Glass2016-01-241-11/+10
| | | | | | | | | This uses a non-existent node at present. It should use the first CPU node. The referenced property does not exist (the correct value is the default of 0), but this allows the follow-on init to complete. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Move CPU init code into the driverSimon Glass2016-01-242-7/+4
| | | | | | | | Use the CPU driver's probe() method to perform the CPU init. This will happen automatically when the first CPU is probed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Use common CPU init codeSimon Glass2016-01-241-52/+42
| | | | | | | | | The existing ivybridge code predates the normal multi-core CPU init, and it is not used. Remove it and add CPU nodes to the device tree so that all four CPUs are set up. Also enable the 'cpu' command. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Move GPIO init to the LPC init() methodSimon Glass2016-01-242-4/+3
| | | | | | | This init can happen in the driver also. Move it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Move sandybridge init to the lpc probe() methodSimon Glass2016-01-242-17/+18
| | | | | | | | The watchdog can be reset later when probing the LPC after relocation. Move it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Move graphics init much laterSimon Glass2016-01-243-78/+76
| | | | | | | | We don't need to init the graphics controller so early. Move it alongside the other graphics setup, just before we run the ROM. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Probe the LPC in CPU initSimon Glass2016-01-241-3/+2
| | | | | | | | We can drop the explicit probe of the PCH since the LPC is a child device and this will happen automatically. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Rename lpc_init() to lpc_init_extra()Simon Glass2016-01-242-2/+2
| | | | | | | | In preparation for adding an init() method to the LPC uclass, rename this existing function so that it will not conflict. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Move LPC and PCH init into northbridge probe()Simon Glass2016-01-241-23/+24
| | | | | | | Move more code into the northbridge probe() function. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Move northbridge init into the probe() methodSimon Glass2016-01-242-14/+21
| | | | | | | | Now that we have a proper driver for the nortbridge, set it up in by probing it, and move the early init code into the probe() method. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Add a driver for the bd82x6x northbridgeSimon Glass2016-01-241-0/+18
| | | | | | | | Add a driver with an empty probe function where we can move init code in follow-on patches. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Rename bd82x6x_init()Simon Glass2016-01-243-2/+10
| | | | | | | | Rename the existing bd82x6x_init() to bd82x6x_init_extra(). We will remove this in a later patch. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Move more init to the probe() functionSimon Glass2016-01-242-43/+43
| | | | | | | | Move SPI and port80 init to lpc_early_init(), called from the LPC's probe() method. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Move lpc_early_init() to probe()Simon Glass2016-01-242-16/+25
| | | | | | | | Move this code to the LPC's probe() method so that it will happen automatically when the LPC is probed before relocation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Set up the LPC device using driver modelSimon Glass2016-01-243-1/+14
| | | | | | | | | | Find the LPC device in arch_cpu_init_dm() as a first step to converting this code to use driver model. Probing the LPC will probe its parent (the PCH) automatically, so make sure that probing the PCH does nothing before relocation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: x86: spi: Convert ICH SPI driver to driver model PCI APISimon Glass2016-01-241-1/+46
| | | | | | | | | | | | | | | | | | | | | | | | | At present this SPI driver works by searching the PCI buses for its peripheral. It also uses the legacy PCI API. In addition the driver has code to determine the type of Intel PCH that is used (version 7 or version 9). Now that we have proper PCH drivers we can use those to obtain the information we need. While the device tree has a node for the SPI peripheral it is not in the right place. It should be on the PCI bus as a sub-peripheral of the LPC device. Update the device tree files to show the SPI controller within the PCH, so that PCI access works as expected. This patch includes Bin's fix-up patch from here: https://patchwork.ozlabs.org/patch/569478/ Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* Merge branch 'master' of git://git.denx.de/u-boot-x86Tom Rini2016-01-141-1/+0
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| * x86: ivybridge: Do not require HAVE_INTEL_MEBin Meng2016-01-131-1/+0
| | | | | | | | | | | | | | | | | | Do not set HAVE_INTEL_ME by default as for some cases Intel ME firmware even does not reside on the same SPI flash as U-Boot. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* | dm: pci: video: Convert video and pci_rom to use DM PCI APISimon Glass2016-01-121-2/+2
| | | | | | | | | | | | | | | | | | | | Adjust these files to use the driver-model PCI API instead of the legacy functions. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* | dm: x86: ivybridge: Convert graphics init to use DM PCI APISimon Glass2016-01-122-10/+11
|/ | | | | | | | | Use the driver-model PCI functions here where possible. For now we have to search for the device with pci_bus_find_bdf() but at some point we can put this in a proper driver and avoid this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Remove HAVE_ACPI_RESUMEBin Meng2015-12-093-34/+0
| | | | | | | | | These are currently dead codes. Until we have complete ACPI support, we don't know if it works or not. Remove to avoid confusion. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* x86: Remove CPU_INTEL_SOCKET_RPGA989Bin Meng2015-12-091-11/+4
| | | | | | | | | | This Kconfig option name indicates it has something to do with cpu socket, however it is actually not the case. Remove it and move options inside it to NORTHBRIDGE_INTEL_IVYBRIDGE. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* x86: Clean up ivybridge/chrome Kconfig optionsBin Meng2015-12-091-30/+0
| | | | | | | | | | There are some options which are never used, and also some options which are selected by others but have never been a Kconfg option. Clean these up. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* x86: ivybridge: Remove NORTHBRIDGE_INTEL_SANDYBRIDGEBin Meng2015-12-091-32/+1
| | | | | | | | NORTHBRIDGE_INTEL_SANDYBRIDGE is for sandybridge, not ivybridge. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* x86: Convert to use driver model timerBin Meng2015-12-011-1/+0
| | | | | | | Convert all x86 boards to use driver model tsc timer. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: ivybridge: Enable the MRC cacheBin Meng2015-10-211-8/+2
| | | | | | | | | This works correctly now, so enable it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Dropped malloc() and adjusted commit message: Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Measure the MRC code execution timeSimon Glass2015-10-211-0/+3
| | | | | | | | This code takes about 450ms without the MRC cache and about 27ms with the cache. Add a debug timer so that this time can be displayed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Fix car_uninit() to correctly set run stateSimon Glass2015-10-211-1/+1
| | | | | | | | At present a missing $ causes this code to hang when using the MRC cache/ Fix it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Check the RTC return valueSimon Glass2015-10-211-3/+10
| | | | | | | The RTC can fail, so check the return value for reads. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Use 'ret' instead of 'rcode'Simon Glass2015-10-211-8/+8
| | | | | | | For consistency, use 'ret' to handle a return value. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: chromebook_link: Enable the debug UARTSimon Glass2015-10-211-0/+7
| | | | | | | Add support for the debug UART on link. This is useful for early debugging. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Correct two typos for MRCBin Meng2015-10-211-2/+2
| | | | | | | It should be MRC, not MCR. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Use struct mrc_region to describe a mrc regionBin Meng2015-10-211-1/+1
| | | | | | | | | | | | | | | | Currently struct fmap_entry is used to describe a mrc region. However this structure contains some other fields that are not related to mrc cache and causes confusion. Besides, it does not include a base address field to store SPI flash's base address. Instead in the mrccache.c it tries to use CONFIG_ROM_SIZE to calculate the SPI flash base address, which unfortunately is not 100% correct as CONFIG_ROM_SIZE may not match the whole SPI flash size. Define a new struct mrc_region and use it instead. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: ivybridge: Use APIs provided in the mrccache libBin Meng2015-10-211-108/+4
| | | | | | | | Remove the call to custom mrc cache APIs, and use the ones provided in the mrccache lib. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Move mrccache.[c|h] to a common placeBin Meng2015-10-213-159/+1
| | | | | | | | mrccache implementation can be common for all boards. Move it from ivybridge cpu directory to the common lib directory. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: ivybridge: Remove the dead codes that programs pci bridgeBin Meng2015-10-211-32/+0
| | | | | | | Remove bd82x6x_pci_bus_enable_resources() that is not called anywhere. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Enable DM RTC support for all x86 boardsBin Meng2015-07-282-9/+24
| | | | | | | | Add a RTC node in the device tree to enable DM RTC support. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> (Squashed in 'x86: Fix RTC build error on ivybridge')
* Kill unneeded #include <linux/kconfig.h>Masahiro Yamada2015-07-271-1/+0
| | | | | | | | | | | | | | | | Because the top-level Makefile forces all the source files to include include/linux/kconfig.h (see the UBOOTINCLUDE define), these includes are redundant. By the way, there are exceptions for the statement above; host programs. In fact, host tools in U-Boot depend on a particular board configuration, although I think they should not. So, some files still include <linux/config.h> to work around build errors on host tools. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Acked-by: Simon Glass <sjg@chromium.org>
generated by cgit (git 2.34.1) at 2025-09-04 19:02:45 +0000