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| * mips: octeon: Add cvmx-dtx-defs.h header fileAaron Williams2021-04-231-0/+6962
| | | | | | | | | | | | | | | | | | Import cvmx-dtx-defs.h header file from 2013 U-Boot. It will be used by the later added drivers to support PCIe and networking on the MIPS Octeon II / III platforms. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * mips: octeon: Add cvmx-dpi-defs.h header fileAaron Williams2021-04-231-0/+1460
| | | | | | | | | | | | | | | | | | Import cvmx-dpi-defs.h header file from 2013 U-Boot. It will be used by the later added drivers to support PCIe and networking on the MIPS Octeon II / III platforms. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * mips: octeon: Add cvmx-dbg-defs.h header fileAaron Williams2021-04-231-0/+33
| | | | | | | | | | | | | | | | | | Import cvmx-dbg-defs.h header file from 2013 U-Boot. It will be used by the later added drivers to support PCIe and networking on the MIPS Octeon II / III platforms. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * mips: octeon: Add cvmx-ciu-defs.h header fileAaron Williams2021-04-231-0/+7351
| | | | | | | | | | | | | | | | | | Import cvmx-ciu-defs.h header file from 2013 U-Boot. It will be used by the later added drivers to support PCIe and networking on the MIPS Octeon II / III platforms. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * mips: octeon: Add cvmx-bgxx-defs.h header fileAaron Williams2021-04-231-0/+4106
| | | | | | | | | | | | | | | | | | Import cvmx-bgxx-defs.h header file from 2013 U-Boot. It will be used by the later added drivers to support PCIe and networking on the MIPS Octeon II / III platforms. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * mips: octeon: Add cvmx-asxx-defs.h header fileAaron Williams2021-04-231-0/+709
| | | | | | | | | | | | | | | | | | Import cvmx-asxx-defs.h header file from 2013 U-Boot. It will be used by the later added drivers to support PCIe and networking on the MIPS Octeon II / III platforms. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * mips: octeon: Add cvmx-agl-defs.h header fileAaron Williams2021-04-231-0/+3135
| | | | | | | | | | | | | | | | | | Import cvmx-agl-defs.h header file from 2013 U-Boot. It will be used by the later added drivers to support PCIe and networking on the MIPS Octeon II / III platforms. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * mips: octeon: Add misc cvmx-helper header filesAaron Williams2021-04-2324-0/+5498
| | | | | | | | | | | | | | | | | | Import misc cvmx-helper header files from 2013 U-Boot. They will be used by the later added drivers to support PCIe and networking on the MIPS Octeon II / III platforms. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * mips: global_data.h: Add Octeon specific data to arch_global_data structStefan Roese2021-04-231-0/+9
| | | | | | | | | | | | | | This will be used by the upcoming Serdes and driver code ported from the original 2013 U-Boot code to mainline. Signed-off-by: Stefan Roese <sr@denx.de>
* | Merge branch '2021-04-22-assorted-updates'Tom Rini2021-04-231-1/+0
|\ \ | |/ |/| | | | | - Move LMB to Kconfig, improve functionality - Add partlabel support to more fs cmds
| * lmb: move CONFIG_LMB in KconfigPatrick Delaunay2021-04-221-1/+0
| | | | | | | | | | | | Migrate CONFIG_LMB in Kconfig. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
* | mips: octeon: mrvl,octeon_ebb7304.dts: Add MMC DT nodeStefan Roese2021-04-221-0/+57
| | | | | | | | | | | | | | | | | | | | Add the MMC DT node to the Octeon EBB7304 DT file including the regulator node for the MMC power supply. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Aaron Williams <awilliams@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* | mips: octeon: mrvl,cn73xx.dtsi: Add MMC DT nodeStefan Roese2021-04-221-0/+27
| | | | | | | | | | | | | | | | | | Add the MMC DT node to the Octeon CN73xx dtsi file. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Aaron Williams <awilliams@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* | mmc: octeontx_hsmmc: Add support for MIPS OcteonStefan Roese2021-04-221-0/+614
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Until now, the Octeontx MMC driver did only support the ARM Octeon TX/Tx2 platforms. This patch adds support for the MIPS Octeon platform to this driver. Here a short summary of the changes: - Enable driver compilation for MIPS Octeon, including the MMC related header file - Reorder header inclusion - Switch to using the clk framework to get the input clock - Remove some functions for MIPS Octeon, as some registers don't exist here Signed-off-by: Stefan Roese <sr@denx.de> Cc: Peng Fan <peng.fan@nxp.com> Cc: Aaron Williams <awilliams@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* | mips: mt7628: fix the displayed DDR type of mt7628Weijie Gao2021-04-221-0/+3
| | | | | | | | | | | | | | | | | | | | The MT7688KN is a multi-chip package with 8MiB DDR1 KGD. So the DDR type from bootstrap register must be ignored, and always be assumed as DDR1. This patch fixes the displayed DDR type of mt7628. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> Reviewed-by: Stefan Roese <sr@denx.de>
* | mips: mt7628: fix ddr_type for MT7688KNWeijie Gao2021-04-221-3/+3
| | | | | | | | | | | | | | | | | | | | | | The MT7688KN is a multi-chip package with 8MiB DDR1 KGD. So the DDR type from bootstrap register must be ignored, and always be assumed as DDR1. This patch fixes an issue that mt7628_ddr_pad_ldo_config() may be passed with a wrong ddr_type in MT7688KN. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> Reviewed-by: Stefan Roese <sr@denx.de>
* | net: jr2: Reset switchHoratiu Vultur2021-04-221-2/+4
|/ | | | | | | Make sure to reset the switch core at probe time. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
* common: Drop asm/global_data.h from common headerSimon Glass2021-02-0226-1/+26
| | | | | | | | | | | | Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
* mips: mtmips: add two reference boards for mt7620Weijie Gao2021-01-244-0/+216
| | | | | | | | | | | The mt7620_rfb board supports integrated 10/100M PHYs plus two external giga PHYs. It also has 8MB SPI-NOR, mini PCI-e x1 slot, SDHC and USB. The mt7620_mt7530_rfb boards supports an external MT7530 giga switch and a 16MB SPI-NOR flash. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
* mips: mtmips: add support for MediaTek MT7620 SoCWeijie Gao2021-01-2413-0/+1117
| | | | | | | | This patch adds support for MediaTek MT7620 SoC. All files are dedicated for u-boot. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
* mips: mtmips: add support to initialize SDRAMWeijie Gao2021-01-242-0/+63
| | | | | | | This patch adds support for mtmips SoCs to initialize the SDRAM. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
* mips: enable _machine_restart for splWeijie Gao2021-01-241-1/+1
| | | | | | | | | | The sysreset driver has a config CONFIG_SPL_SYSRESET for the spl stage. Change CONFIG_SYSRESET to CONFIG_IS_ENABLED(SYSRESET) will give spl a chance to use _machine_restart instead of the sysreset driver. Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
* mips: mtmips: fix dram size detection in dram_initWeijie Gao2021-01-241-3/+2
| | | | | | | | | | | CONFIG_SYS_SDRAM_BASE points to cached memory, i.e. KSEG0, which is not suitable for detecting memory size. Replace CONFIG_SYS_SDRAM_BASE with KSEG1, and make dram_init() always do memory size detection in any stage. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
* mips: mtmips: select SYSRESET for mt7628 onlyWeijie Gao2021-01-242-1/+1
| | | | | | | | Currently only mt7628 needs the sysreset driver, do not select it for mt7620. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
* mips: mtmips: move mt7628 related Kconfig into mt7628 subdirectoryWeijie Gao2021-01-242-52/+54
| | | | | | | | | | | This patch is a preparation for add a new soc fot mtmips. Move all mt7628 related Kconfig (boards and UART selection) into mt7628 subdirectory and make sure the top directory of mtmips contains only selection for SoCs. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
* mips: dts: switch to board defines for dtb for mtmipsWeijie Gao2021-01-241-3/+2
| | | | | | | | | | | | | Previous the dts files for gardena-smart-gateway-mt7688 and linkit-smart-7688 are set to be built when mtmips is selected. This can lead to a compilation error if another soc is added to this arch with different dtsi files. So it's better to build the dtb only if their board is selected. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
* common: board_r: Drop arch-specific ifdefs around initr_trapOvidiu Panait2021-01-151-1/+8
| | | | | | | | | | | | In order to remove the arch-specific ifdefs around initr_trap, introduce arch_initr_trap weak initcall. Implementations for ppc/m68k/mips have been moved to arch/<arch>/lib/traps.c Default implementation is a nop stub. Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* Merge tag 'dm-pull-5jan21' of git://git.denx.de/u-boot-dm into nextTom Rini2021-01-051-1/+1
|\ | | | | | | | | | | | | | | | | Driver model: make some udevice fields private Driver model: Rename U_BOOT_DEVICE et al. dtoc: Tidy up and add more tests ns16550 code clean-up x86 and sandbox minor fixes for of-platdata dtoc prepration for adding build-time instantiation
| * dm: Rename DM_GET_DRIVER() to DM_DRIVER_GET()Simon Glass2021-01-051-1/+1
| | | | | | | | | | | | | | | | In the spirit of using the same base name for all of these related macros, rename this to have the operation at the end. This is not widely used so the impact is fairly small. Signed-off-by: Simon Glass <sjg@chromium.org>
* | spi: dw: Add SoC-specific compatible stringsSean Anderson2020-12-182-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds SoC-specific compatible strings to all users of the designware spi device. This will allow for the correct driver to be selected for each device. Where it is publicly documented, a compatible string for the specific device version has also been added. Devices without publicly-documented device versions include MSCC SoCs, and Arc Socs. All compatible strings except those for SoCFPGAs and some of the versioned strings have been taken from Linux. Since SSI_MAX_XFER_SIZE is determined at runtime, this is not strictly necessary. However, it is a good cleanup and brings things closer to Linux. Signed-off-by: Sean Anderson <seanga2@gmail.com> Tested-by Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
* | mips: octeon: tools: Add update_octeon_header toolStefan Roese2020-11-302-222/+172
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a tool to update or insert an Octeon specific header into the U-Boot image. This is needed e.g. for booting via SPI NOR, eMMC and NAND. While working on this, move enum cvmx_board_types_enum and cvmx_board_type_to_string() to cvmx-bootloader.h and remove the unreferenced (unsupported) board definition. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Aaron Williams <awilliams@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* | mips: octeon: bootoctlinux: Use gd->ram_size instead of ram_get_info()Stefan Roese2020-11-301-18/+3
| | | | | | | | | | | | | | | | | | | | | | | | Using ram_get_info() is complicated and does not work after relocation. Now that gd->ram_size holds the full RAM size, let's use it instead and remove the ram_get_size logic completely. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Aaron Williams <awilliams@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* | mips: octeon: Report full DDR size in dram_init() to gd->ram_sizeStefan Roese2020-11-301-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | With this patch, gd->ram_size now holds to full RAM size detected by the DDR init code. It introduces the get_effective_memsize() function to report the maximum usable RAM size in U-Boot to the system instead. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Aaron Williams <awilliams@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* | mips: start.S: Add Octeon boot header compatibilityStefan Roese2020-11-301-2/+8
|/ | | | | | | | | | | | | | | | | Octeon has a specific boot header, when booted via SPI NOR, NAND or MMC. Here the only 2 instructions are allowed in the first few bytes of the image. And these instructions need to be one branch and a nop. This patch adds the necessary nop after the nop, to that the common MIPS image is compatible with this Octeon header. The tool to patch the Octeon boot header into the image will be send in a follow-up patch. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Aaron Williams <awilliams@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* mips: octeon: Add bootoctlinux commandAaron Williams2020-10-073-0/+716
| | | | | | | | | | | | Octeon needs a platform specific cmd to boot the Linux kernel, as specific parameters need to be passed and special handling for the multiple cores (SMP) is needed. Co-developed-by: Stefan Roese <sr@denx.de> Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de> [use gd->ram_base instead of gd->bd->bi_memstart] Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* mips: octeon: Add bootmem supportAaron Williams2020-10-073-0/+1994
| | | | | | | | This is needed for Linux booting, as the memory infos need to be passed in this bootmem format to the Linux kernel. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
* mips: octeon: Add coremask supportAaron Williams2020-10-073-0/+1119
| | | | | | | This patch adds the coremask handling functions. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
* mips: octeon: Add header cvmx-bootinfo.hAaron Williams2020-10-071-0/+350
| | | | | | | | Add header to handle bootinfo support, needed for Octeon Linux kernel booting. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
* mips: octeon: Add header cvmx-fuse.hAaron Williams2020-10-071-0/+71
| | | | | | | Add header to handle Octeon fuse access. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
* mips: octeon: Add header octeon-feature.hAaron Williams2020-10-071-0/+442
| | | | | | | | This header includes the Octeon feature detection used in many Octeon drivers. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
* mips: octeon: Add header cvmx-regs.hAaron Williams2020-10-071-0/+144
| | | | | | | This header includes common register defines and accessor functions. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
* mips: octeon: lowlevel_init.S: Add NMI handling code for SMP Linux bootingStefan Roese2020-10-071-0/+76
| | | | | | | | | | | | | This patch adds the necessary lowlevel init code, to enable SMP Linux booting. This code will be used with the platform specific Octeon Linux boot command "bootoctlinux", which starts a configurable number of cores into Linux. Additionally some erratas and lowlevel register initializations are copied from the original Cavium / Marvell U-Boot source code, enabling booting into the Linux kernel. Signed-off-by: Stefan Roese <sr@denx.de>
* mips: octeon: octeon-model.h: Enable inclusion from assembler filesStefan Roese2020-10-071-0/+4
| | | | | | | Add the #ifdef __ASSEMBLY__ checks to enable inclusion of this header from assembler files. Signed-off-by: Stefan Roese <sr@denx.de>
* mips: octeon: Add USB DT nodesStefan Roese2020-10-072-0/+84
| | | | | | | Add the USB device tree nodes to the Octeon dts/dtsi files. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* mips: octeon: cache.c: Flush all pending writes in flush_dcache_range()Stefan Roese2020-10-071-6/+6
| | | | | | | | As noticed while working on the USB xHCI support, Octeon needs to flush all pending writes so that the values are present in the memory. Add this "syncw" instruction (twice) to flush_dcache_range(). Signed-off-by: Stefan Roese <sr@denx.de>
* mips: octeon: Add mangle-port.hStefan Roese2020-10-071-0/+56
| | | | | | | | | Import platform specific mangle-port.h header, allowing a area specific swapping, which is needed on Octeon for USB & PCI areas. Imported from Linux v5.7. Signed-off-by: Stefan Roese <sr@denx.de>
* mips: octeon: cpu.c: Add table for selective swappingStefan Roese2020-10-071-0/+21
| | | | | | | | | | Import octeon_should_swizzle_table[] which is needed for the area specific swapping. It will be used by the platform specific mangle-port.h header. Imported from Linux v5.7. Signed-off-by: Stefan Roese <sr@denx.de>
* mips: octeon: dram.c: Add RAM driver supportStefan Roese2020-10-071-8/+64
| | | | | | | | | This patch adds the initialization call for the Octeon RAM driver to the Octeon platforms code. So if enabled via Kconfig, the DDR driver will be called and the RAM will be configured and used. If the RAM driver is not enabled, the L2 cache is still used as RAM. Signed-off-by: Stefan Roese <sr@denx.de>
* mips: octeon: Add octeon_ddr.h headerAaron Williams2020-10-071-0/+982
| | | | | | | | This header will be used by the DDR driver (lmc). Its ported from the 2013 Cavium / Marvell U-Boot repository. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
* mips: octeon Add cvmx/cvmx-lmcx-defs.h headerAaron Williams2020-10-071-0/+4574
| | | | | | | | This header will be used by the DDR driver (lmc). Its ported from the 2013 Cavium / Marvell U-Boot repository. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
generated by cgit (git 2.34.1) at 2025-09-01 23:19:47 +0000