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* mips: octeon: Add misc cvmx-helper header filesAaron Williams2021-04-2324-0/+5498
| | | | | | | | | Import misc cvmx-helper header files from 2013 U-Boot. They will be used by the later added drivers to support PCIe and networking on the MIPS Octeon II / III platforms. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
* mmc: octeontx_hsmmc: Add support for MIPS OcteonStefan Roese2021-04-221-0/+614
| | | | | | | | | | | | | | | | | | | Until now, the Octeontx MMC driver did only support the ARM Octeon TX/Tx2 platforms. This patch adds support for the MIPS Octeon platform to this driver. Here a short summary of the changes: - Enable driver compilation for MIPS Octeon, including the MMC related header file - Reorder header inclusion - Switch to using the clk framework to get the input clock - Remove some functions for MIPS Octeon, as some registers don't exist here Signed-off-by: Stefan Roese <sr@denx.de> Cc: Peng Fan <peng.fan@nxp.com> Cc: Aaron Williams <awilliams@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* common: Drop asm/global_data.h from common headerSimon Glass2021-02-021-0/+1
| | | | | | | | | | | | Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
* mips: octeon: tools: Add update_octeon_header toolStefan Roese2020-11-302-222/+172
| | | | | | | | | | | | | | | Add a tool to update or insert an Octeon specific header into the U-Boot image. This is needed e.g. for booting via SPI NOR, eMMC and NAND. While working on this, move enum cvmx_board_types_enum and cvmx_board_type_to_string() to cvmx-bootloader.h and remove the unreferenced (unsupported) board definition. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Aaron Williams <awilliams@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* mips: octeon: bootoctlinux: Use gd->ram_size instead of ram_get_info()Stefan Roese2020-11-301-18/+3
| | | | | | | | | | | | Using ram_get_info() is complicated and does not work after relocation. Now that gd->ram_size holds the full RAM size, let's use it instead and remove the ram_get_size logic completely. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Aaron Williams <awilliams@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* mips: octeon: Report full DDR size in dram_init() to gd->ram_sizeStefan Roese2020-11-301-1/+6
| | | | | | | | | | | | With this patch, gd->ram_size now holds to full RAM size detected by the DDR init code. It introduces the get_effective_memsize() function to report the maximum usable RAM size in U-Boot to the system instead. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Aaron Williams <awilliams@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* mips: octeon: Add bootoctlinux commandAaron Williams2020-10-073-0/+716
| | | | | | | | | | | | Octeon needs a platform specific cmd to boot the Linux kernel, as specific parameters need to be passed and special handling for the multiple cores (SMP) is needed. Co-developed-by: Stefan Roese <sr@denx.de> Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de> [use gd->ram_base instead of gd->bd->bi_memstart] Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* mips: octeon: Add bootmem supportAaron Williams2020-10-073-0/+1994
| | | | | | | | This is needed for Linux booting, as the memory infos need to be passed in this bootmem format to the Linux kernel. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
* mips: octeon: Add coremask supportAaron Williams2020-10-073-0/+1119
| | | | | | | This patch adds the coremask handling functions. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
* mips: octeon: Add header cvmx-bootinfo.hAaron Williams2020-10-071-0/+350
| | | | | | | | Add header to handle bootinfo support, needed for Octeon Linux kernel booting. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
* mips: octeon: Add header cvmx-fuse.hAaron Williams2020-10-071-0/+71
| | | | | | | Add header to handle Octeon fuse access. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
* mips: octeon: Add header octeon-feature.hAaron Williams2020-10-071-0/+442
| | | | | | | | This header includes the Octeon feature detection used in many Octeon drivers. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
* mips: octeon: Add header cvmx-regs.hAaron Williams2020-10-071-0/+144
| | | | | | | This header includes common register defines and accessor functions. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
* mips: octeon: lowlevel_init.S: Add NMI handling code for SMP Linux bootingStefan Roese2020-10-071-0/+76
| | | | | | | | | | | | | This patch adds the necessary lowlevel init code, to enable SMP Linux booting. This code will be used with the platform specific Octeon Linux boot command "bootoctlinux", which starts a configurable number of cores into Linux. Additionally some erratas and lowlevel register initializations are copied from the original Cavium / Marvell U-Boot source code, enabling booting into the Linux kernel. Signed-off-by: Stefan Roese <sr@denx.de>
* mips: octeon: octeon-model.h: Enable inclusion from assembler filesStefan Roese2020-10-071-0/+4
| | | | | | | Add the #ifdef __ASSEMBLY__ checks to enable inclusion of this header from assembler files. Signed-off-by: Stefan Roese <sr@denx.de>
* mips: octeon: cache.c: Flush all pending writes in flush_dcache_range()Stefan Roese2020-10-071-6/+6
| | | | | | | | As noticed while working on the USB xHCI support, Octeon needs to flush all pending writes so that the values are present in the memory. Add this "syncw" instruction (twice) to flush_dcache_range(). Signed-off-by: Stefan Roese <sr@denx.de>
* mips: octeon: Add mangle-port.hStefan Roese2020-10-071-0/+56
| | | | | | | | | Import platform specific mangle-port.h header, allowing a area specific swapping, which is needed on Octeon for USB & PCI areas. Imported from Linux v5.7. Signed-off-by: Stefan Roese <sr@denx.de>
* mips: octeon: cpu.c: Add table for selective swappingStefan Roese2020-10-071-0/+21
| | | | | | | | | | Import octeon_should_swizzle_table[] which is needed for the area specific swapping. It will be used by the platform specific mangle-port.h header. Imported from Linux v5.7. Signed-off-by: Stefan Roese <sr@denx.de>
* mips: octeon: dram.c: Add RAM driver supportStefan Roese2020-10-071-8/+64
| | | | | | | | | This patch adds the initialization call for the Octeon RAM driver to the Octeon platforms code. So if enabled via Kconfig, the DDR driver will be called and the RAM will be configured and used. If the RAM driver is not enabled, the L2 cache is still used as RAM. Signed-off-by: Stefan Roese <sr@denx.de>
* mips: octeon: Add octeon_ddr.h headerAaron Williams2020-10-071-0/+982
| | | | | | | | This header will be used by the DDR driver (lmc). Its ported from the 2013 Cavium / Marvell U-Boot repository. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
* mips: octeon Add cvmx/cvmx-lmcx-defs.h headerAaron Williams2020-10-071-0/+4574
| | | | | | | | This header will be used by the DDR driver (lmc). Its ported from the 2013 Cavium / Marvell U-Boot repository. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
* mips: octeon: Add octeon-model.h headerAaron Williams2020-10-071-0/+313
| | | | | | | | This header is used by the upcoming DDR driver and potentially by other drivers ported from the 2013 Cavium / Marvell U-Boot repository. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
* mips: octeon: Add minimal Octeon 3 EBB7304 EVK supportStefan Roese2020-07-181-0/+14
| | | | | | | | | | | | | | | This patch adds very basic minimal support for the Marvell Octeon 3 CN73xx based EBB7304 EVK. Please note that the basic Octeon port does not support DDR3/4 initialization yet. To still use U-Boot on with this port, the L2 cache (4MiB) is used as RAM. This way, U-Boot can boot to the prompt on this board. Supported devices: - UART - reset - CFI parallel NOR flash Signed-off-by: Stefan Roese <sr@denx.de>
* mips: octeon: use mips_mach_early_init() to copy to L2 cacheStefan Roese2020-07-181-0/+50
| | | | | | | | | | | | | This patch adds the code to copy itself from bootrom location to a different location (TEXT_BASE) to the Octeon platform. Its used in this case to copy the complete U-Boot image into L2 cache, which greatly improves the bootup time - especially in regard to the very long and complex DDR4 init code. The Kconfig symbol CONFIG_MIPS_MACH_EARLY_INIT is enabled with this patch for Octeon. Signed-off-by: Stefan Roese <sr@denx.de>
* mips: octeon: Initial minimal support for the Marvell Octeon SoCAaron Williams2020-07-1810-0/+266
This patch adds very basic support for the Octeon III SoCs. Only CFI parallel NOR flash and UART is supported for now. Please note that the basic Octeon port does not include the DDR3/4 initialization yet. This will be added in some follow-up patches later. To still use U-Boot on with this port, the L2 cache (4MiB on Octeon III CN73xx) is used as RAM. This way, U-Boot can boot to the prompt on such boards. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
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