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* treewide: Convert macro and uses of __section(foo) to __section("foo")Marek Behún2021-05-2419-45/+46
| | | | | | | | | | | | | | | | | This commit does the same thing as Linux commit 33def8498fdd. Use a more generic form for __section that requires quotes to avoid complications with clang and gcc differences. Remove the quote operator # from compiler_attributes.h __section macro. Convert all unquoted __section(foo) uses to quoted __section("foo"). Also convert __attribute__((section("foo"))) uses to __section("foo") even if the __attribute__ has multiple list entry forms. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* arm: mvebu: armada-3720-uDPU.dts: Change back to phy-mode "2500base-x"Stefan Roese2021-05-201-2/+2
| | | | | | | | | | | | | With commit 8678776df6f5 (arm: mvebu: armada-3720-uDPU: fix PHY mode definition to sgmii-2500) the PHY mode was switch to "sgmii-2500", even when this is functionally incorrect since "2500base-x" was not supported in U-Boot at that time. As this mode is now supported (at least present in the headers), this patch moves back to the orinal version. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Jakov Petrina <jakov.petrina@sartura.hr> Cc: Vladimir Vid <vladimir.vid@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr>
* arm64: zynqmp: Add description for SOM/Kria boardsMichal Simek2021-05-197-0/+1109
| | | | | | | | | | | | The patch contains several DT files for SOM platform. Carrier card is sck-kv (KV260) revA/B. SMK-K26 is description for starter kit which doesn't have EMMC populated. And SM-K26 is full som with EMMC. Files are divided in this way to make sure that SOM can be plugged to different carrier card and all peripherals on SOM (or defined by a spec) can be used by U-Boot. Full DT for SOM+CC can be merged together as overlays. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* arm64: zynqmp: Add psgtr DT descriptionsMichal Simek2021-05-1910-1/+79
| | | | | | | | | Mainline kernel has psgtr driver that's why it is good to add description to DT files. Some boards are just missing description for USB3 and sata. zc1751-dc1 and p-a2197 are also missing clock descriptions for input clocks. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* arm64: zynqmp: Add pinctrl descriptionMichal Simek2021-05-1911-1/+2470
| | | | | | | ZynqMP pinctrl Linux driver has been merged to 5.13-rc1 kernel. Based on it DT files can be extended by pinctrl configurations. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* arm64: zynqmp: Add zynqmp firmware specific DT nodesT Karthik Reddy2021-05-192-0/+80
| | | | | | | Probe zynqmp firmware driver by adding zynqmp firmware, power & ipi mailbox device tree nodes for mini emmc. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
* arm64: zynqmp: Add missing mio-bank properties to sdhciMichal Simek2021-05-191-0/+1
| | | | | | | | | Add missing xlnx,mio-bank property to sdhci node. Also add properties with 0 value to have it listed in case that files are copied to different projects where default case doesn't need to be handled in the same way. That's why explicitly list them too. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* arm64: zynqmp: Remove comment about clock chipsMichal Simek2021-05-192-10/+10
| | | | | | These comments weren't push to mainline that's why remove them. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* arm64: zynqmp: Add 'i2c-mux-idle-disconnect' propertyRaviteja Narayanam2021-05-193-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | I2C muxes that have the slave devices with same address are falling into the below problem. VCK190 system controller (SC) - zynqmp-e-a2197-00-revA.dts I2C1 (0xff030000) -> Mux1 (@0x74) -> Channel 3 -> 0x50 I2C1 (0xff030000) -> Mux2 (@0x75) -> Channel 0 -> 0x50 1. SC accesses I2C1 - Mux1 (0x74) - Channel 3 and then 2. SC accesses I2C1 - Mux2 (0x75) - Channel 0. Now it results in 2 slave devices with same address (0x50) on the I2C bus, making the communication un-reliable. When ' i2c-mux-idle-disconnect' is in DT, after '1', the Mux channel output is disconnected, making none of the channels available to the I2C1. So, there is no question of having the same addressed slave (0x50) present on the bus when we are doing '2'. Same pattern is seen in below two boards also. ZCU208 - zynqmp-zcu208-revA.dts ZCU216 - zynqmp-zcu216-revA.dts Signed-off-by: Raviteja Narayanam <raviteja.narayanam@xilinx.com>
* arm64: zynqmp: Add label to all GPIO lines for VCK190 SCSaeed Nowshadi2021-05-191-7/+7
| | | | | | | | | | | | Add label to GPIO lines so the user-level applications can find any line without knowing its physical path on System Controller on VCK190/VMK180. These labels are describing EMIO gpio connection which depends on PL which we normally don't describe but that's only way to go for now. Lately this should be done out of this source code. Signed-off-by: Saeed Nowshadi <saeed.nowshadi@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* arm64: zynqmp: Add 'silabs,skip-recall' to DDR DIMM si570 clk nodeSaeed Nowshadi2021-05-191-1/+2
| | | | | | | | The 'silabs,skip-recall' property prevents interruption in operation of the clock while the driver is being probed. Without this property, the DDR DIMM clk can cause a failure during Versal's boot. Signed-off-by: Saeed Nowshadi <saeed.nowshadi@xilinx.com>
* arm64: zynqmp: Add missing silabs,skip-recall for si570 ref clk nodesMichal Simek2021-05-195-3/+8
| | | | | | | | | All si570 which are used for ps reference clock generation should contain silabs,skip-recall property not to cause break on ps clock. On Versal boards this will cause hang on Versal cpu when it is booted at the same time with SC. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* arm: octeontx2: Add dtsi/dts files for Octeon TX2 CN913x DBKonstantin Porotchkin2021-05-1611-0/+1004
| | | | | | | | | This patch adds the dtsi/dts files needed to support the Marvell Octeon TX2 CN913x DB. This is only the base port with not all interfaces supported fully. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
* arm64: mvebu: extend the mmio regionGrzegorz Jaszczyk2021-05-162-2/+4
| | | | | | | | | Some of the setups including cn9130 opens mmio window starting from 0xc0000000, reflect it in the u-boot code. Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Signed-off-by: Kostya Porotchkin <kostap@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
* arm64: mvebu: a8k: move firmware related definitions to fw infoGrzegorz Jaszczyk2021-05-161-0/+3
| | | | | Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Signed-off-by: Stefan Roese <sr@denx.de>
* arm64: mvebu: do not map firmware RT service regionGrzegorz Jaszczyk2021-05-162-1/+24
| | | | | | | | | | | | | | There is region left by ATF, which needs to remain in memory to provide RT services. To prevent overwriting it by u-boot, do not provide any mapping for this memory region, so any attempt to access it will trigger synchronous exception. Update sr 2021-04-12: Don't update armada3700/cpu.c mmu table, as this has specific changes included in mainline. Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Signed-off-by: Stefan Roese <sr@denx.de>
* arm64: mvebu: a8k: align memory regionsjinghua2021-05-161-55/+7
| | | | | | | | 1. RAM: base address 0x0 size 2Gbytes 2. MMIO: base address 0xf0000000 size 1Gbytes Signed-off-by: Ofir Fedida <ofedida@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
* Merge https://source.denx.de/u-boot/custodians/u-boot-shTom Rini2021-05-141-0/+1
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| * ARM: renesas: Scrub duplicate memory nodes from DT on Gen3Marek Vasut2021-05-121-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Scrub duplicate /memory@* node entries here. Some R-Car DTs might contain multiple /memory@* nodes, however fdt_fixup_memory_banks() either generates single /memory node or updates the first /memory node. Any remaining memory nodes are thus potential duplicates. However, it is not possible to delete all the memory nodes right away, since some of those might not be DRAM memory nodes, but some sort of other memory. Thus, delete only the memory nodes which are in the R-Car3 DBSC ranges. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
* | ARM: dts: add missing -u-boot.dtsi to enable HDMI on Beelink GTKing/King-ProNeil Armstrong2021-05-142-0/+14
| | | | | | | | | | | | | | This lacks the right u-boot specific DT include to make HDMI work. Reported-by: B1oHazard <ty3uk@mail.ua> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* | am335x: add support for cape detect functionalityKory Maincent2021-05-131-0/+1
| | | | | | | | | | | | | | Update the Kconfig and the board file to make the am335x board compatible with cape detection. Signed-off-by: Kory Maincent <kory.maincent@bootlin.com>
* | arm: am335x: add support for i2c2 busKory Maincent2021-05-131-0/+1
| | | | | | | | | | | | | | | | | | The am335x from BeagleBone use i2c EEPROM to detect capes. The memory is wired to i2c bus 2 therefore it need to be enabled. Add i2c2 clock, pinmux description and pinmux enable function. Signed-off-by: Kory Maincent <kory.maincent@bootlin.com>
* | arm: sunxi: add support for DIP detection to CHIP boardKory Maincent2021-05-131-0/+9
| | | | | | | | | | | | | | | | | | | | Add the extension_board_scan specific function to scan the information of the EEPROM on one-wire and fill the extension struct. Add the Kconfig symbol to enable the needs to detect DIPs. Signed-off-by: Kory Maincent <kory.maincent@bootlin.com> Reviewed-by: Maxime Ripard <maxime@cerno.tech> Acked-by: Andre Przywara <andre.przywara@arm.com>
* | am57xx: add support for cape detect functionalityKory Maincent2021-05-131-0/+1
| | | | | | | | | | | | | | This commit enables using the extension board detection mechanism on AM57xx based platforms. Signed-off-by: Kory Maincent <kory.maincent@bootlin.com>
* | Merge tag 'ti-v2021.07-rc3' of ↵Tom Rini2021-05-1222-4/+8922
|\ \ | |/ |/| | | | | | | | | | | https://source.denx.de/u-boot/custodians/u-boot-ti - Initial support for AM64 EVM and SK - K3 DDR driver unification for J7 and AM64 platforms. - Minor fixes for TI clock driver
| * ARM: dts: k3-am642-sk: Add ethernet related DT nodesVignesh Raghavendra2021-05-122-0/+78
| | | | | | | | | | | | | | Add CPSW related nodes for AM642 SK. There are two CPSW ports on the board but U-Boot supports only the first port. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
| * ARM: dts: k3-am64-main: Add CPSW DT nodesVignesh Raghavendra2021-05-124-0/+185
| | | | | | | | | | | | | | | | | | AM64 as CPSW3G IP with 2 external ports. Add DT entries for the same (based on kernel DT). Disable second port as its by default set to ICSS usage on EVM. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
| * arm: dts: am642-r5-sk: Add r5 specific dtsLokesh Vutla2021-05-123-1/+2337
| | | | | | | | | | | | | | Add R5 specific dts for AM64 SK Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
| * arm: dts: am642-sk: Add initial sk dtsLokesh Vutla2021-05-123-1/+183
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | AM642 StarterKit (SK) board is a low cost, small form factor board designed for TI’s AM642 SoC. It supports the following interfaces: * 2 GB LPDDR4 RAM * x2 Gigabit Ethernet interfaces capable of working in switch and MAC mode * x1 USB 3.0 Type-A port * x1 UHS-1 capable µSD card slot * 2.4/5 GHz WLAN + Bluetooth 4.2 through WL1837 * 512 Mbit OSPI flash * x2 UART through UART-USB bridge * XDS110 for onboard JTAG debug using USB * Temperature sensors, user push buttons and LEDs * 40-pin Raspberry Pi compatible GPIO header * 24-pin header for peripherals in MCU island (I2C, UART, SPI, IO) * 54-pin header for Programmable Realtime Unit (PRU) IO pins * Interface for remote automation. Includes: * power measurement and reset control * boot mode change Add basic support for AM642 SK. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * arm: dts: am642-evm: Add I2C nodesLokesh Vutla2021-05-123-0/+64
| | | | | | | | | | | | Add I2C nodes for AM64 and enable pinmux for i2c0 for reading eeprom data. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * arm: dts: k3-am642-r5-evm: Do not use power-domains for I2CLokesh Vutla2021-05-121-0/+5
| | | | | | | | | | | | | | I2C EEPROM will be probed before SYSFW is available. So drop the power-domains property for I2C. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * arm: dts: k3-am64-evm: Make chip id available before pre-relocLokesh Vutla2021-05-121-0/+7
| | | | | | | | | | | | | | Chipid will be needed for SoC detection for all stages of U-Boot. So make it u-boot,dm-spl Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * arm: am64x: Add support for selecting DT based on EEPROMLokesh Vutla2021-05-121-0/+26
| | | | | | | | | | | | | | Enable support for selecting DTB within SPL based on EEPROM. This will help to use single defconfig for both EVM and SK Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * board: ti: am64x: Add support for reading eeprom dataLokesh Vutla2021-05-121-0/+3
| | | | | | | | | | | | | | | | | | | | I2C EEPROM data contains the board name and its revision. Add support for: - Reading EEPROM data and store a copy at end of SRAM - Updating env variable with relevant board info - Printing board info during boot. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * arm: dts: k3-am642-r5-evm: Add GPIO DDR VTT regulatorNishanth Menon2021-05-121-0/+28
| | | | | | | | | | | | | | Add DDR VTT regulator. Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
| * arm: dts: k3-am64-main: Add GPIO nodesNishanth Menon2021-05-121-0/+44
| | | | | | | | | | | | | | Add main domain GPIO nodes. Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
| * arm: mach-k3: am642: Add support for triggering ddr init from SPLDave Gerlach2021-05-121-0/+6
| | | | | | | | | | | | | | | | In SPL, DDR should be made available by the end of board_init_f() so that apis in board_init_r() can use ddr. Adding support for triggering DDR initialization from board_init_f(). Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
| * arm: dts: k3-am642: Add ddr nodeDave Gerlach2021-05-123-0/+4394
| | | | | | | | | | | | | | | | | | Introduce ddr node for am642 needed for all ddr configurations. Also, introduce the 1600MTs DDR4 configuration that is supported on the am642-evm. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
| * arm: dts: k3-am642: Add r5 specific dt supportDave Gerlach2021-05-123-1/+229
| | | | | | | | | | | | Add initial support for dt that runs on r5. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
| * arm: dts: k3-am642: Add initial support for EVMDave Gerlach2021-05-122-0/+247
| | | | | | | | | | | | | | | | | | | | The AM642 EValuation Module (EVM) is a board that provides access to various peripherals available on the AM642 SoC, such as PCIe, USB 2.0, CPSW Ethernet, ADC, and more. Add basic support. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
| * arm: dts: ti: Add Support for AM642 SoCDave Gerlach2021-05-124-0/+649
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The AM642 SoC belongs to the K3 Multicore SoC architecture platform, providing advanced system integration to enable applications such as Motor Drives, PLC, Remote IO and IoT Gateways. Some highlights of this SoC are: * Dual Cortex-A53s in a single cluster, two clusters of dual Cortex-R5F MCUs, and a single Cortex-M4F. * Two Gigabit Industrial Communication Subsystems (ICSSG). * Integrated Ethernet switch supporting up to a total of two external ports. * PCIe-GEN2x1L, USB3/USB2, 2xCAN-FD, eMMC and SD, UFS, OSPI memory controller, QSPI, I2C, eCAP/eQEP, ePWM, ADC, among other peripherals. * Centralized System Controller for Security, Power, and Resource Management (DMSC). See AM64X Technical Reference Manual (SPRUIM2, Nov 2020) for further details: https://www.ti.com/lit/pdf/spruim2 Introduce basic support for the AM642 SoC to enable SD/MMC boot. Introduce a limited set of MAIN domain peripherals under cbass_main and a set of MCU domain peripherals under cbass_mcu. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
| * board: ti: am64x: Add board support for am64x evmDave Gerlach2021-05-121-0/+1
| | | | | | | | | | | | Add board specific initialization for am64x based boards. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
| * armv8: mach-k3: am642: Add custom MMU supportKeerthy2021-05-121-0/+41
| | | | | | | | | | | | | | | | | | | | | | | | Change the memory attributes for the DDR regions used by the remote processors on AM65x so that the cores can see and execute the proper code. A separate table based on the previous K3 SoCs is introduced since the number of remote processors and their DDR usage is different between the SoC families. Signed-off-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
| * arm: mach-k3: am642: Shut down R5 core after ATF startup on A53Suman Anna2021-05-121-0/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The AM642 SoCs use the Main R5FSS0 as a boot processor, and runs the R5 SPL that performs the initialization of the System Controller processor and starting the Arm Trusted Firmware (ATF) on the Arm Cortex A53 cluster. The Core0 serves as this boot processor and is parked in WFE after all the initialization. Core1 does not directly participate in the boot flow, and is simply parked in a WFI. Power down these R5 cores (and the associated RTI timer resources that were indirectly powered up) after starting up ATF on A53 by using the appropriate SYSFW API in release_resources_for_core_shutdown(). This allows these Main R5F cores to be further controlled from the A53 to run regular applications. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
| * arm: mach-k3: am642: Use mmc start and stop callbacksDave Gerlach2021-05-121-1/+33
| | | | | | | | | | | | | | To avoid any glitches on MMC clock line, make use of pm per and post callbacks when loading sysfw. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
| * arm: mach-k3: am642: Load SYSFW binary and config from boot mediaDave Gerlach2021-05-121-0/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | Use the System Firmware (SYSFW) loader framework to load and start the SYSFW as part of the AM642 early initialization sequence. Also make use of existing logic to detect if ROM has already loaded sysfw and avoided attempting to reload and instead just prepare to use already running firmware. While at it also initialize the MAIN_UART1 pinmux as it is used by SYSFW to print diagnostic messages. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
| * arm: mach-k3: am642: Store boot info from ROMDave Gerlach2021-05-122-0/+23
| | | | | | | | | | | | | | | | | | | | For AM642, ROM supports loading system firmware directly from boot image. ROM passes information about the number of images that are loaded to bootloader at a specific address that is temporary. Add support for storing this information somewhere permanent before it gets corrupted. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
| * arm: mach-k3: am642: Unlock all applicable control MMR registersDave Gerlach2021-05-122-4/+22
| | | | | | | | | | | | | | To access various control MMR functionality the registers need to be unlocked. Do that for all control MMR regions in the MAIN domain. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
| * arm: mach-k3: am642: Add support for boot device detectionKeerthy2021-05-125-0/+198
| | | | | | | | | | | | | | | | | | | | | | | | | | AM642 allows for booting from primary or backup boot media. Both media can be chosen individually based on switch settings. ROM looks for a valid image in primary boot media, if not found then looks in backup boot media. In order to pass this boot media information to boot loader, ROM stores a value at a particular address. Add support for reading this information and determining the boot media correctly. Signed-off-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
| * arm: mach-k3: Add basic support for AM642 SoC definitionDave Gerlach2021-05-123-4/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The AM642 SoC belongs to the K3 Multicore SoC architecture platform, providing advanced system integration to enable applications such as Motor Drives, PLC, Remote IO and IoT Gateways. Some highlights of this SoC are: * Dual Cortex-A53s in a single cluster, two clusters of dual Cortex-R5F MCUs, and a single Cortex-M4F. * Two Gigabit Industrial Communication Subsystems (ICSSG). * Integrated Ethernet switch supporting up to a total of two external ports. * PCIe-GEN2x1L, USB3/USB2, 2xCAN-FD, eMMC and SD, UFS, OSPI memory controller, QSPI, I2C, eCAP/eQEP, ePWM, ADC, among other peripherals. * Centralized System Controller for Security, Power, and Resource Management (DMSC). See AM64X Technical Reference Manual (SPRUIM2, Nov 2020) for further details: https://www.ti.com/lit/pdf/spruim2 Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
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