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* Merge branch 'master' of git://git.denx.de/u-boot-imxTom Rini2018-09-0420-23/+1738
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| * imx: mx7: add system suspend/resume supportAnson Huang2018-09-043-3/+515
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds system suspend/resume support, when linux kernel enters deep sleep mode, SoC will go into below mode: - CA7 platform goes into STOP mode; - SoC goes into DSM mode; - DDR goes into self-refresh mode; - CPU0/SCU will be powered down. When wake up event arrives: - SoC DSM mdoe exits; - CA7 platform exit STOP mode, SCU/CPU0 power up; - Invalidate L1 cache; - DDR exit self-refresh mode; - Do secure monitor mode related initialization; - Jump to linux kernel resume entry. Belwo is the log of 1 iteration of system suspend/resume: [ 338.824862] PM: suspend entry (deep) [ 338.828853] PM: Syncing filesystems ... done. [ 338.834433] Freezing user space processes ... (elapsed 0.001 seconds) done. [ 338.842939] OOM killer disabled. [ 338.846182] Freezing remaining freezable tasks ... (elapsed 0.001 seconds) done. [ 338.869717] PM: suspend devices took 0.010 seconds [ 338.877846] Disabling non-boot CPUs ... [ 338.960301] Retrying again to check for CPU kill [ 338.964953] CPU1 killed. [ 338.968104] Enabling non-boot CPUs ... [ 338.973598] CPU1 is up [ 339.267155] mmc1: queuing unknown CIS tuple 0x80 (2 bytes) [ 339.275833] mmc1: queuing unknown CIS tuple 0x80 (7 bytes) [ 339.284158] mmc1: queuing unknown CIS tuple 0x80 (6 bytes) [ 339.385065] PM: resume devices took 0.400 seconds [ 339.389836] OOM killer enabled. [ 339.392986] Restarting tasks ... done. [ 339.398990] PM: suspend exit The resume entry function has to initialize stack pointer before calling C code, otherwise there will be an external abort occur, in additional, invalidate L1 cache must be done in secure section as well, so this patch also adds assembly code back and keep it as simple as possible. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Acked-by: Stefan Agner <stefan@agner.ch> Tested-by: Stefan Agner <stefan@agner.ch>
| * imx: mx7: add gpc initialization for low power modeAnson Huang2018-09-041-0/+103
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add i.MX7D GPC initialization for low power mode support like system suspend/resume from linux kernel: - Pending IOMUXC IRQ to workaround GPC state machine issue; - Mask all GPC interrupts for M4/C0/C1; - Configure SCU timing; - Configure time slot ack; - Configure C0/C1 power up/down timing; - Configure wakeup source mechanism; - Disable DSM/RBC related settings. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
| * imx: mx7: psci: improve cpu hotplug flowAnson Huang2018-09-041-2/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch improves cpu hotplug, previous cpu_off implementation is NOT safe, a CPU can NOT power down itself in runtime, it will cause system bus hang due to pending transaction. So need to use other online CPU to kill it when it is ready for killed. Here use SRC parameter register and a magic number of ~0 as handshake for killing a offline CPU, when the online CPU checks the psci_affinity_info, it will help kill the offline CPU according to the magic number stored in SRC parameter register. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
| * watchdog: mx25: use the imx_watchdog driver for mx25Martin Kaiser2018-09-041-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The existing imx_watchdog driver is compatible with mx25 chipsets. Add a WDOG1_BASE_ADDR define for the base address and enable the driver in watchdog's Makefile. To use the driver, a board must define CONFIG_IMX_WATCHDOG and CONFIG_HW_WATCHDOG. This fixes an issue when booting an mx25 chip via usb/serial. In this case, the boot rom will always enable the watchdog. If u-boot is running in interactive mode and the watchdog is not serviced, the system is rebooted when the watchdog expires. Signed-off-by: Martin Kaiser <martin@kaiser.cx> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
| * dts: imx6ul_evk: Add DTS files for 14x14 EVK and 9x9 EVK boardsYe Li2018-09-045-1/+921
| | | | | | | | | | | | | | | | | | | | Add the board DTS files for 14x14 EVK and 9x9 EVK. They are necessary for converting to use u-boot DM driver. Two -u-boot.dtsi are added to modify compatible string of SPI flash device to "spi-flash". Signed-off-by: Ye Li <ye.li@nxp.com>
| * dts: imx6ul: Update alias to support DMYe Li2018-09-041-6/+7
| | | | | | | | | | | | | | Add spi0 alias for qspi for enabling DM SPI. Change usb alias for usbotg1 and usbotg2 for enabling DM USB Signed-off-by: Ye Li <ye.li@nxp.com>
| * imx: imx7d-sdb: Add DM QSPI supportYe Li2018-09-046-6/+91
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On iMX7D SabreSD board, the QSPI has pins conflict with EPDC (default). To use QSPI, users have to rework the board (de-populate R388-R391, R396-R399 populate R392-R395, R299, R300). So we add new DTS file and new defconfig dedicated for QSPI. Other changes to support the DM QSPI: - Add QSPI node and alias spi0. - Modify spi4 (spi-gpio) node and add alias spi5 for it to avoid req conflict - Add EPDC node in imx7d.dtsi and disable it in imx7d-sdb-qspi.dts to align with kernel and also present the conflict. - Add -u-boot.dtsi to modify compatible string of mx25l51245g@0 to "spi-flash" - Remove iomux settings of qspi in board codes which is not needed for DM driver. Signed-off-by: Ye Li <ye.li@nxp.com>
| * imx: imx6sx-sabreauto: convert to use DM QSPI driverYe Li2018-09-042-0/+56
| | | | | | | | | | | | | | | | | | | | | | To support DM QSPI driver: - Add -u-boot.dtsi to modify n25q256a@0 and n25q256a@1 compatible string to "spi-flash" and add "num-cs" property. - Enable DM SPI and DM SPI FLASH configurations - Remove iomux settings of qspi1 in board codes which is not needed for DM driver. Signed-off-by: Ye Li <ye.li@nxp.com>
| * imx: imx6sx-sdb: Enable DM QSPI driverYe Li2018-09-042-5/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | To support DM QSPI driver - Add spi0 and spi1 alias for qspi1 and qspi2. - Add -u-boot.dtsi to modify n25q256a@0 and n25q256a@1 compatible string to "spi-flash" and add "num-cs" property. - Enable DM SPI/QSPI relavent configurations - Remove iomux settings of qspi2 in board codes which is not needed for DM driver. - Add sf default settings. So running "sf probe" can detect the flash Signed-off-by: Ye Li <ye.li@nxp.com>
* | rockchip: dts: fix unnecessary '-cells' warningKever Yang2018-08-298-18/+0
|/ | | | | | | | | Fix warning below: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* cmd: ubi: change 'default y' for SUNXI to 'imply' in KconfigMasahiro Yamada2018-08-261-0/+1
| | | | | | | | It is not preferred to put SUNXI-specific code in the common place. Change it to 'imply' property of ARCH_SUNXI. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini2018-08-2411-67/+55
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| * ARM: dts: socfpga: Add missing NAND resetMarek Vasut2018-08-241-0/+1
| | | | | | | | | | | | | | | | | | | | The NAND reset is missing from DT, so the reset manager cannot unreset the NAND. Add the missing DT reset entry. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
| * ARM: dts: socfpga: Drop ad-hoc UART clock frequency encoding from DTMarek Vasut2018-08-241-1/+0
| | | | | | | | | | | | | | | | | | | | The UART clock frequency can be obtained from the clock framework by the ns16550 driver, so drop this redundant DT node. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
| * ARM: socfpga: Convert Arria10 to timer frameworkMarek Vasut2018-08-241-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | Switch the Arria10 from ad-hoc hardcoded timer to timer framework and the DW APB timer driver. This allows the A10 to extract timer information, like timer rate, from clock framework and thus DT instead of having it hardcoded in U-Boot configuration files. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
| * ARM: dts: socfpga: Flag timer clock as pre-relocMarek Vasut2018-08-242-12/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | Flag timer clock as DM pre-reloc, so that a timer driver can be used and it can extract information about it's clock rate using the clock framework. This patch also moves some of the pre-reloc flags into the core dtsi file, this is because the timer is not board specific, but rather is used on all boards. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
| * ARM: socfpga: Reorder Arria10 SPLMarek Vasut2018-08-246-44/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Arria10 SPL is a complete mess of calls to functions which are called in the wrong context and it is surprise it works at all. This patch tries to clean that mess up by shuffling the function calls around and moving the calls into the correct context. Due to the delicate nature of the reordering, this is done in one huge patch. The following changes happen in this patch: - Security policy init and NIC301 happens first in board_init_f() - The clock init happens very early in board_init_f() in SPL only - arch_early_init_r() only registers the FPGA, just like on Gen5 - arch_early_init_r() is never called from any _f() function - Dedicated FPGA pins are inited in board_init_f() as on Gen5 Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
| * arm: socfpga: stratix10: Fix mailbox urgent command with urgent registerLey Foon Tan2018-08-241-8/+7
| | | | | | | | | | | | | | | | According to mailbox spec, software should send urgent command with urgent register instead of COUT location. This patch write urgent command index to urgent register. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
| * arm: socfpga: stratix10: Enable EMAC to FPGA bridge based on handoffLey Foon Tan2018-08-241-1/+1
| | | | | | | | | | | | | | | | | | | | Code checking and setting EMAC use fpga is in populate_sysmgr_fpgaintf_module(). So, call to sysmgr_pinmux_init() instead of populate_sysmgr_pinmux(). In sysmgr_pinmux_init(), it will call to both populate_sysmgr_pinmux() and populate_sysmgr_fpgaintf_module(). Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini2018-08-242-2/+2
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| * | dm: convert device_get_global_by_of_offset() to device_get_global_by_ofnode()Jean-Jacques Hiblot2018-08-212-2/+2
| | | | | | | | | | | | | | | | | | | | | Also add device_find_global_by_ofnode() that also find a device based on the OF node, but doesn't probe the device. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
* | | board: arm: bcmstb: Declare get_ticks in timer.hThomas Fitzsimmons2018-08-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | In an earlier proposed patch, bcmstb.c implemented timer_read_counter, but it was updated to implement get_ticks instead. This patch updates the declaration in timer.h accordingly. Signed-off-by: Thomas Fitzsimmons <fitzsim@fitzsim.org>
* | | Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini2018-08-231-1/+1
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| * | armv8: fsl-layerscape: Update README.falcon for compressionYork Sun2018-08-231-1/+1
| | | | | | | | | | | | | | | | | | | | | Update README.falcon to use "none" for compression property for ramdisk image to avoid being uncompressed upon loading. Signed-off-by: York Sun <york.sun@nxp.com>
* | | ARM: tegra: avoid more operations in non-secure worldStephen Warren2018-08-212-8/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A secure monitor that runs before U-Boot, and hence causes U-Boot to run in non-secure world, must implement a few operations that U-Boot otherwise implements when running in secure world. Fix U-Boot to skip these operations when running in non-secure world. In particular: - The secure monitor must provide the LP0 resume code and own LP0 configuration in order to maintain security, so must initialize all the PMC scratch registers used by the boot ROM during LP0 resume. Consequently, U-Boot should not attempt to clear those registers, since the register accesses will fail or cause an error. - The secure monitor owns system security, and so is responsible for configuring security-related items such as the VPR. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | | arm: tegra: Restore host1x/dc dm-pre-reloc propertiesNicolas Chauvet2018-08-211-0/+10
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since commit f2faffecb016, tegra: Convert to use binman the dm-pre-reloc properties are removed. This leads U-Boot not to enable the display on paz00 This patch restore the dm-pre-reloc properties allowing the bootloader to output to the display panel v4: - Spell project name as appropriate v3: - Fix few typos v2: - Add more characters to commit hash Signed-off-by: Nicolas Chauvet <kwizart@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-sunxiTom Rini2018-08-2011-117/+2631
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| * sunxi: fix sid base address macro name for H6Icenowy Zheng2018-08-201-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | In the current H6 CPU memory space code, the SUNXI in the macro name of the SID address base is wrongly spelled as SNUXI, which leads to SID readout not working. Fix this macro name. Fixes: 55f6b1c351c9 ("sunxi: add basic memory map definitions of H6 SoC") Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * sunxi: A64: fix default DRAM_ODT_EN symbolAndre Przywara2018-08-131-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | "default" lines in Kconfig are processed in order, the first hit will stop considering subsequent lines. In the case of the DRAM_ODT_EN symbol that means that everything following the first two lines will never be checked: ------------ config DRAM_ODT_EN bool "sunxi dram odt enable" default n if !MACH_SUN8I_A23 default y if MACH_SUN8I_A23 default y if MACH_SUN8I_R40 default y if MACH_SUN50I ------------ Assuming that the "default y" for the A64 and the R40 were a deliberate choice, fix the Kconfig stanza to take this into account. Also remove the now redundant lines from the respective defconfigs. Signed-off-by: Andre Przywara <andre.przywara@arm.com> [jagan: droped 'default n' on original change] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> # A64, R40 Tested-by: Chen-Yu Tsai <wens@csie.org> # A23
| * ARM: dts: sun8i: Update R40/V40 dts(i) files from Linux-v4.18-rc3Jagan Teki2018-08-133-35/+486
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update all R40/V40 devicetree dtsi and dtsi files from Linux-v4.18-rc3 with below commit: R40: commit c36fd5a48bd20820855e3e91a89297eeaa31836e Author: Chen-Yu Tsai <wens@csie.org> Date: Wed May 2 00:12:25 2018 +0800 ARM: dts: sun8i: r40: bananapi-m2-ultra: Enable GMAC ethernet controller V40: commit c5f0bb472795170ab5c33be12e29ce7465fb31ed Author: Icenowy Zheng <icenowy@aosc.io> Date: Fri Apr 6 22:03:44 2018 +0800 ARM: sun8i: v40: enable USB host ports for Banana Pi M2 Berry Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> # BPI-M2-Ultra, BPI-M2-Berry
| * ARM: dts: sun8i: Update A83T dts(i) files from Linux-v4.18-rc3Jagan Teki2018-08-136-80/+2144
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update all A83T devicetree dtsi and dtsi files from Linux-v4.18-rc3 with below commit: commit 221cb9fd2ee3042689fe0e6613d0f34eb46a5af6 Author: Mylène Josserand <mylene.josserand@bootlin.com> Date: Fri May 4 21:05:44 2018 +0200 ARM: dts: sun8i: Add enable-method for SMP support for the A83T SoC Note: bananapi-m3 and cubietruck-plus board dts files has usb_otg enabled in U-Boot which were not present in Linux. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
* | Convert CONFIG_MII et al to KconfigAdam Ford2018-08-172-2/+0
| | | | | | | | | | | | | | | | | | | | This converts the following to Kconfig: CONFIG_MII CONFIG_DRIVER_TI_EMAC Signed-off-by: Adam Ford <aford173@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-shTom Rini2018-08-171-0/+2
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| * | ARM: rmobile: Enable USB PHY on Gen2Marek Vasut2018-08-141-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | Enable support for USB PHY on the R-Car Gen2. This allows for both of the USB host ports to be used on such boards. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* | | Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini2018-08-1727-618/+244
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| * | | arm: socfpga: Fix SYSMGR_FPGAINTF_EMACx bit maskLey Foon Tan2018-08-151-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | Bitmask for EMAC should be bit-0, EMAC1 bit-8 and EMAC2 bit-16. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
| * | | ARM: socfpga: clk: Convert to clock frameworkMarek Vasut2018-08-132-218/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use clock framework functions to fetch clock information now that there is a clock driver for Arria10, instead of custom coded register parsing. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
| * | | ARM: dts: socfpga: Add u-boot,dm-pre-reloc to necessary clock nodesMarek Vasut2018-08-133-0/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the pre-reloc DT markers to clock nodes needed in SPL and early U-Boot stages. This is required to let the Arria10 clock driver start early and provide clock information for UART and SDMMC. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
| * | | ARM: socfpga: clk: Drop unused variables on Arria10Marek Vasut2018-08-131-17/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The variables removed in this patch are never used, they are only ever assigned and then waste precious memory. Drop both the assignment and the variables. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
| * | | ARM: socfpga: clk: Make L4SP and MMC clock calculation Gen5 onlyMarek Vasut2018-08-131-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The L4SP and MMC clock precalculation is specific to Gen5, it is not needed on Arria10/Stratix10. Isolate it to Gen5 until there is a proper clock driver for Gen5, at which point this will go away completely. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
| * | | ARM: socfpga: clk: Obtain handoff base clock via DMMarek Vasut2018-08-132-12/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Bind fixed clock driver to the base clock instantiated in the handoff DT and use DM clock framework to get their clock rate. This replaces the ad-hoc DT parsing present thus far. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
| * | | ARM: socfpga: Remove adhoc ethernet reset and configurationMarek Vasut2018-08-133-50/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove ad-hoc ethernet syscon registers configuration and reset support. Reset is now handled by the reset framework and the syscon registers are set in the dwmac_socfpga.c driver. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
| * | | ARM: socfpga: Zap unused reset codeMarek Vasut2018-08-132-126/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove code from the reset manager that is never called. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
| * | | ARM: socfpga: Zap all the UART handling complexityMarek Vasut2018-08-135-149/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The UART reset handling is now done via reset framework using the SoCFPGA reset driver. The UART console assignment is done using the DM and console framework. Nuke all this comlexity, since it is just duplicating the same functionality, badly. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org>
| * | | ARM: socfpga: Enable DM I2C framework on A10Marek Vasut2018-08-131-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable the DM I2C framework on Arria10, so that the DM capable Designware I2C driver can handle the reset via DM reset framework. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
| * | | ARM: socfpga: Enable DM reset framework on A10Marek Vasut2018-08-131-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable the DM reset framework and DM reset driver on Arria10 both in U-Boot and in SPL. This lets U-Boot parse reset control from DT. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
| * | | ARM: dts: socfpga: Add i2c alias to A10 SoCDKMarek Vasut2018-08-131-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The A10 SoCDK is missing the I2C bus alias, so DM I2C cannot assign the I2C bus a bus number. Add the missing alias. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
| * | | ARM: dts: socfpga: Add missing I2C resetsMarek Vasut2018-08-131-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The I2Cx resets are missing from DT, so the reset manager cannot control them. Add the missing DT reset entries. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
| * | | ARM: dts: socfpga: Fix Arria10 GMAC resetsMarek Vasut2018-08-131-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the GMAC0,1 OCP resets, which must also be ungated for those GMACs to work and add GMAC2 reset and OCP resets which were missing altogether. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
generated by cgit (git 2.34.1) at 2024-09-20 01:27:41 +0000