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* | | armv8: make SPL exception vectors optionalAndre Przywara2018-08-033-4/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Even though the exception vector table is a fundamental part of the ARM architecture, U-Boot mostly does not make real use of it, except when crash dumping. But having it in takes up quite some space, partly due to the architectural alignment requirement of 2KB. Since we don't take special care of that, the compiler adds a more or less random amount of padding space, which increases the image size quite a bit, especially for the SPL. On a typical Allwinner build this is around 1.5KB of padding, plus 1KB for the vector table (mostly padding space again), then some extra code to do the actual handling. This amounts to almost 10% of the maximum image size, which is quite a lot for a pure debugging feature. Add a Kconfig symbol to allow the exception vector table to be left out of the build for the SPL. For now this is "default y" for everyone, but specific defconfigs, platforms or .config files can opt out here at will, to mitigate the code size pressure we see for some SPLs. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* | | armv8: Reduce exception handling codeAndre Przywara2018-08-031-50/+82
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The arm64 exception handling code is quite big, mostly due to architectural alignment requirements. Each exception entry spans 32 instructions, which sounds generous, but is too small to fit all of the save/branch/restore code in there. So at the moment we use only four instructions, branching into shared save and restore routines. To not leave the space for those remaining 28 instructions wasted, let's split the save and restore routines and stuff them into the gaps. This saves about 250 bytes of code, which is helpful for those tight SPLs. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* | | Merge git://git.denx.de/u-boot-dmTom Rini2018-08-032-4/+4
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| * | | binman: Rename 'position' to 'offset'Simon Glass2018-08-012-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | After some thought, I believe there is an unfortunate naming flaw in binman. Entries have a position and size, but now that we support hierarchical sections it is unclear whether a position should be an absolute position within the image, or a relative position within its parent section. At present 'position' actually means the relative position. This indicates a need for an 'image position' for code that wants to find the location of an entry without having to do calculations back through parents to discover this image position. A better name for the current 'position' or 'pos' is 'offset'. It is not always an absolute position, but it is always an offset from its parent offset. It is unfortunate to rename this concept now, 18 months after binman was introduced. However I believe it is the right thing to do. The impact is mostly limited to binman itself and a few changes to in-tree users to binman: tegra sunxi x86 The change makes old binman definitions (e.g. downstream or out-of-tree) incompatible if they use the 'pos = <...>' property. Later work will adjust binman to generate an error when it is used. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | | ARM: tegra: align carveout sizeStephen Warren2018-08-011-1/+1
|/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Align the size of the carveout region to 2M. This ensures that the size can be accurately represented by an LPAE page table that uses sections. This solves a bug (hang at boot time soon after printing the DRAM size) that only shows up when the following two commits are merged together: d32e86bde8a3 ARM: HYP/non-sec: enable ARMV7_LPAE if HYP mode is supported 6e584e633d10 ARM: tegra: avoid using secure carveout RAM Cc: Mark Kettenis <kettenis@openbsd.org> Cc: Alexander Graf <agraf@suse.de> Acked-by: Tom Warren <twarren@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* / / dm: Fix CMD_DM enablingMichal Simek2018-07-311-1/+1
|/ / | | | | | | | | | | | | | | | | | | The patch "dm: Change CMD_DM enabling" (sha1: 08a00cba06a7e608ae65e3d7ea225cf8c639429d) was incorrectly updated and PICO_IMX7D is missing imply CMD_DM and WARP7 has it twice. This patch is fixing it. Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | Merge tag 'signed-efi-next' of git://github.com/agraf/u-bootTom Rini2018-07-306-42/+62
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Patch queue for efi - 2018-07-25 Highlights this time: - Many small fixes to improve spec compatibility (found by SCT) - Almost enough to run with sandbox target - GetTime() improvements - Enable EFI_LOADER and HYP entry on ARMv7 with NONSEC=y
| * | efi_loader: Rename sections to allow for implicit dataAlexander Graf2018-07-254-41/+59
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some times gcc may generate data that is then used within code that may be part of an efi runtime section. That data could be jump tables, constants or strings. In order to make sure we catch these, we need to ensure that gcc emits them into a section that we can relocate together with all the other efi runtime bits. This only works if the -ffunction-sections and -fdata-sections flags are passed and the efi runtime functions are in a section that starts with ".text". Up to now we had all efi runtime bits in sections that did not interfere with the normal section naming scheme, but this forces us to do so. Hence we need to move the efi_loader text/data/rodata sections before the global *(.text*) catch-all section. With this patch in place, we should hopefully have an easier time to extend the efi runtime functionality in the future. Signed-off-by: Alexander Graf <agraf@suse.de> [agraf: Fix x86_64 breakage]
| * | ARM: HYP/non-sec: enable ARMV7_LPAE if HYP mode is supportedMark Kettenis2018-07-251-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ARMV7_LPAE is required in order to enable the MMU in HYP mode. And we really want to enable the MMU in HYP mode such that we can enable the the caches. Otherwise U-Boot code (such as the EFI implementation) that runs in HYP mode will run at a snils pace. Signed-off-by: Mark Kettenis <kettenis@openbsd.org> Signed-off-by: Alexander Graf <agraf@suse.de>
| * | ARM: HYP/non-sec: migrate stackMark Kettenis2018-07-251-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current code that switches into HYP mode doesn't bother to set up a stack for HYP mode. This doesn't work for EFI applications as they expect a usable stack. Fix this by migrating the stack pointer from SP_svc to SP_hyp while in Monitor mode. This restores the stack pointer when we drop into HYP mode. Signed-off-by: Mark Kettenis <kettenis@openbsd.org> Signed-off-by: Alexander Graf <agraf@suse.de>
* | | Kconfig: Sort bool, default, select and imply optionsMichal Simek2018-07-3014-65/+66
| | | | | | | | | | | | | | | | | | | | | | | | | | | Another round of sorting Kconfig entries aplhabetically. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Alexey Brodkin <abrodkin@synopsys.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
* | | dm: Change CMD_DM enablingMichal Simek2018-07-3010-0/+102
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CMD_DM is used for debug purpose and it shouldn't be enabled by default via Kconfig. Unfortunately this is in the tree for quite a long time that's why solution is to use imply DM for all targets which are enabling DM. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
* | | Kconfig: Sort bool, default, select and imply optionsMichal Simek2018-07-309-270/+270
| | | | | | | | | | | | | | | | | | | | | | | | Fix Kconfig bool, default, select and imply options to be alphabetically sorted. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | Kconfig: Replace spaces with tabs and missing newlineMichal Simek2018-07-302-12/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | Trivial Kconfig cleanup. Use tabs instead of spaces and every Kconfig entry should be separated by newline. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
* | | Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini2018-07-278-86/+41
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| * | | armv8: ls1046ardb: Add falcon mode for for QSPI bootYork Sun2018-07-262-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A new defconfig is introduced to support SPL boot from QSPI NOR flash. This is to support falcon mode for faster booting into Linux. Signed-off-by: York Sun <york.sun@nxp.com>
| * | | armv8: layerscape: spl: Initialize QSPI AHB for QSPI bootYork Sun2018-07-262-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | To get full access of QSPI space, initialize AHB interface. Signed-off-by: York Sun <york.sun@nxp.com>
| * | | armv8: dts: fsl-ls1012a: add sata node supportYuantian Tang2018-07-264-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | One ls1012a, there is one SATA 3.0 advanced host controller interface which is a high-performance SATA solution that delivers comprehensive and fully-compliant generation 3 (1.5 Gb/s - 6.0 Gb/s) serial ATA capabilities, in accordance with the serial ATA revision 3.0 of Serial ATA International Organization. Add sata node to support this feature. Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | armv8: fsl: remove sata supportYuantian Tang2018-07-262-86/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove the old implementation in order to enable DM for sata. Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | armv8: layerscape: Enabled I-cache for SPL bootYork Sun2018-07-261-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable I-cache for SPL boot to boost performance. Earlier MMU was enabled only for LS2080A and has since been dropped by commit f539c8a4a7a5 ("armv8: ls2080a: Drop early MMU for SPL build"). Signed-off-by: York Sun <york.sun@nxp.com>
* | | | Merge branch 'master' of git://git.denx.de/u-boot-tegraTom Rini2018-07-268-33/+56
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| * | | | tegra: beaver/apalis: Fix DTC warningTom Warren2018-07-262-6/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix warning when compiling tegra30-beaver/-apalis.dts with latest DTC: "Warning (avoid_unnecessary_addr_size): /pci/pch@1f,0: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property" Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | | ARM: tegra: avoid using secure carveout RAMStephen Warren2018-07-261-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If a secure carveout exists, U-Boot cannot use that memory. Fix carveout_size() to reflect this, and hence transitively fix usable_ram_size_below_4g() and board_get_usable_ram_top(). This change ensures that when U-Boot copies the secure monitor code to install it, the copy target is not in-use for U-Boot code/data. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | | ARM: PSCI: Enable the PSCI nodeStephen Warren2018-07-261-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When fixing up the DT to report PSCI support, explicitly enable the node. DTs may ship with the node disabled in case a PSCI implementation is not present, and expect any PSCI implementation to enable the node if they are actually present. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | | ARM: PSCI: Support PSCI v0.2Stephen Warren2018-07-261-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enhance the PSCI DT editing code to allow setting a PSCI v0.2 compatible value in the DT. The CONFIG_ option is added to the whitelist to match the existing PSCI_1_0 option. While not adding new options to Kconfig isn't ideal, I figure it's better to keep related options together. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | | ARM: define MON_MODEStephen Warren2018-07-261-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a MON_MODE define for ARM's monitor mode. This can be used later by a secure monitor to avoid hard-coding mode IDs. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | | ARM: tegra: implement RAM repairBibek Basu2018-07-262-2/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | RAM repair has a few pre-requisites: 1) PMIC power supply (rail) enabled. 2) PMC CRAIL power partition powered. 3) Fuse clock active (it's the default). 4) PLLP reshift branch enabled (it's the default, when PLLP is active). RAM repair also only need run whenever specific partitions are powered (main SoC and CCPLEX respectively); RAM repair does not need to be triggered when any other partition changes state. start_cpu() needs to be re-ordered slightly to match these requirements. Note that C0NC and CE0 aren't required for RAM repair to operate, but they also do no harm, so the entire of powerup_cpus() is moved rather than splitting it up. The call to remove_cpu_resets() is moved last to ensure that all other actions complete before releasing reset; since the PMC power partitions are now enabled early, releasing reset is what causes the CPUs to start executing code, and RAM repair must complete before the CPU boots. Note that this commit is the result of squashing a numbmer of commits in NVIDIA's downstream L4T branch, hence the multiple signoffs below. Signed-off-by: Bibek Basu <bbasu@nvidia.com> Signed-off-by: Sandipan Patra <spatra@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | | Revert "tegra: Introduce SRAM repair on tegra124"Stephen Warren2018-07-262-31/+1
| | |_|/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 701b7b1d2cf657d435d2bd6caf43d0247d37220d. It will be immediately replaced by a different implementation that is more complete and runs are more targetted times. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | | | Merge branch 'master' of git://git.denx.de/u-boot-netTom Rini2018-07-261-1/+1
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| * | | arm: Prevent redefinition error in fsl-layerscapeJoe Hershberger2018-07-261-1/+1
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | The include/phy.h will start including dm.h, which pulls in linux/compat.h after the attempted redefinition in arch/arm/include/asm/armv8/mmu.h, so move this include to allow redefinition. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini2018-07-264-4/+19
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| * | | ARM: dts: socfpga: Adjust NAND register layout on Arria10Marek Vasut2018-07-251-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adjust the NAND register size on Arria10 to reflect reality. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org>
| * | | ARM: socfpga: Init missing security policies on A10Marek Vasut2018-07-251-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Arria10 requires proper configuration of the NOC firewall, otherwise the access to certain areas of the LWHPS bridge fails in Linux. Add the missing setup. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org>
| * | | ARM: socfpga: Assure correct CPACR configurationMarek Vasut2018-07-251-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make sure the ARM CPACR register is zeroed out, this is mandatory on Arria10. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org>
| * | | arm: socfpga: Fixes: Rename CONFIG_SPL_RESET_SUPPORT to CONFIG_SPL_DM_RESETLey Foon Tan2018-07-251-1/+1
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | Commit bfc6bae8fa1f2d8a9c51548767b02f1a1e0ffe52 This commit rename CONFIG_SPL_RESET_SUPPORT to CONFIG_SPL_DM_RESET. Update with new CONFIG name and enable CONFIG_SPL_DM_RESET when CONFIG_DM_RESET is enabled. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Acked-by: Marek Vasut <marex@denx.de>
* | | Merge branch 'master' of git://git.denx.de/u-boot-shTom Rini2018-07-261-0/+4
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| * | ARM: rmobile: gen2: Enable ACTLR[0] (Enable invalidates of BTB) to ↵Marek Vasut2018-07-251-0/+4
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | facilitate CVE_2017-5715 WA in OS Enable CVE_2017_5715 mitigation on CPU0 on R-Car H2, M2W, M2N, V2H, which all contain Cortex-A15 cores. R-Car E2 contains only Cortex-A7 cores and is not affected. Without this enabled, Linux kernel reports: CPU0: Spectre v2: firmware did not set auxiliary control register IBE bit, system vulnerable With this enabled, Linux kernel reports: CPU0: Spectre v2: using ICIALLU workaround NOTE: This by itself does not enable the workaround for other CPUs than CPU0 and may require additional kernel patches for the other CPUs in SMP configurations. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nishanth Menon <nm@ti.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* | ARM: uniphier: enable distro bootMasahiro Yamada2018-07-252-4/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Switch to the distro boot for UniPhier platform. - Remove the environment vairalbes used to load images from raw block devices. - Keep the command to download images via tftp. This will be useful to boot the kernel when no valid kernel image is ready yet in the file system. - Use root.cpio.gz instead of root.cpio.uboot because we always know the file size of the init ramdisk; it is loaded via either a file system or network. - Rename fit_addr_r to kernel_addr_r, which the distro command checks to get the load address of FIT image. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | ARM: uniphier: support fdt_fixup_mtdpartsMasahiro Yamada2018-07-251-0/+8
| | | | | | | | | | | | | | Propagate the "mtdparts" environment variable to the DT passed in to OS. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | ARM: uniphier: split ft_board_setup() out to a separate fileMasahiro Yamada2018-07-255-36/+58
| | | | | | | | | | | | Prepare to add more fdt fixup code. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | ARM: uniphier: clean-up ft_board_setup()Masahiro Yamada2018-07-251-3/+3
|/ | | | | | | The 'bd' is passed in ft_board_setup() as the second argument. Replace 'gd->bd' with 'bd'. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: DTS: am3517-evm-u-boot: Mark MMC1 with cd-invertedAdam Ford2018-07-231-0/+4
| | | | | | | | | In order to use the device tree for MMC, the card-detect pin needs to be inverted. This patch places this into the am3517-evm-u-boot.dtsi file to keep the main DTS and DTSI files clean and in-sync with Linux Signed-off-by: Adam Ford <aford173@gmail.com>
* ARM: dts: am3517-evm-uboot: Add reg-shift for UARTAdam Ford2018-07-231-0/+12
| | | | | | | | | With the resync of the omap3.dtsi file, the reg-shift was removed so it breaks the UART. Adding the reg-shift into the am3517-evm-u-boot.dtsi keeps the reg-shift for U-Boot, but keeps the dts/dtsi files clean from Linux. Signed-off-by: Adam Ford <aford173@gmail.com>
* ARM: DTS: Resync Logic PD SOM-LV 37xx devkit with Linux 4.18-RC4Adam Ford2018-07-233-255/+323
| | | | | | | There have been some significant changes to the DM37 SOM-LV device tree. This patch re-syncs it with Linux. Signed-off-by: Adam Ford <aford173@gmail.com>
* ARM: DTS: Resync LogicPD-Torpedo-37xx-devkit with Linux 4.18-RC4Adam Ford2018-07-233-426/+475
| | | | | | | There have been some refactoring of the DTS files for the Logic PD DM37 Torpedo. This patch re-sync's the DTS files with Linux Signed-off-by: Adam Ford <aford173@gmail.com>
* ARM: dts: Resync OMAP3 and omap36xx with Linux 4.18-RC4Adam Ford2018-07-232-18/+49
| | | | | | | | There have been several minor changes to the OMAP3.dtsi, so this patch re-syncs it with Linux. An addition include/dt-binding was also brought with it. Signed-off-by: Adam Ford <aford173@gmail.com>
* ARM: DTS: Resync am3517-evm.dts with Linux 4.18-rc4Adam Ford2018-07-233-2/+377
| | | | | | | | Several changes have been made to the AM3517-evm and the underlying am3517.dtsi file. This patch re-sync's the DTS and DTSI files with Linux. Signed-off-by: Adam Ford <aford173@gmail.com>
* mx25: fix the offset between the USB ports' registersMartin Kaiser2018-07-231-1/+6
| | | | | | | | | | | | | | | | | | The USBOH module on imx25 chips contains two USB controllers which are called USB OTG Controller and USB Host Controller. Each one has its EHCI root hub. The OTG Controller's EHCI registers start at offset 0, the Host Controller's registers start at offset 0x400. We set CONFIG_MXC_USB_PORT=0 to select the OTG Controller and 1 for the Host Controller. Therefore, IMX_USB_PORT_OFFSET must be 0x400. Using this setting, the Host Controller starts working on my imx25 board. Please note that the imx25 reference manual claims that the Host Controller's registers start at 0x200. This is not correct. The Linux Kernel uses the correct offset 0x400 in imx25.dtsi. Signed-off-by: Martin Kaiser <martin@kaiser.cx> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
* imx: i.mx6q: imx6q_logic: Migrate to SPL and enable SDPAdam Ford2018-07-231-1/+2
| | | | | | | | | | | Since the vast majority of i.MX6 boards are migrating to SPL, this patch converts im6q_logic to SPL and enables the SDP for loading SPL and u-boot.img over USB. The Falcon mode only supports NAND flash as of now due to limited space/RAM, but all i.MX6D/Q SOM's from Logic PD have internal NAND from which to boot. Signed-off-by: Adam Ford <aford173@gmail.com>
* pico-imx7d: Add SPL supportFabio Estevam2018-07-231-0/+1
| | | | | | | | | | | | | | | | | | | Convert pico-imx7d to SPL support. There are two variants of pico-imx7d SOMs: - One with 512MB of RAM - One with 1GB of RAM The 512MB module contains two Hynix H5TC2G63GFR-PBA. The 1GB module contains two Hynix H5TC4G63GFR-PBA. The RAM size is determined in runtime by reading GPIO1_12. While at it, also add USB Serial Download mode support as it is very helpful for loading SPL and u-boot.img via imx_usb_loader. Signed-off-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
generated by cgit (git 2.34.1) at 2024-09-20 15:44:25 +0000