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* arm: stm32mp1: deploy spl in root folderPatrick Delaunay2019-01-291-2/+5
| | | | | | | | | Update generation of spl binaries - continue to generate all SPL files in spl sub-directory - copy in root folder the needed file for user (YOCTO, buildroot): u-boot-spl.stm32 Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
* linker: Modify linker scripts to be more genericTom Rini2019-01-2614-50/+23
| | | | | | | | | | | | | | | | | | | | | | | | | Make use of "IMAGE_MAX_SIZE" and "IMAGE_TEXT_BASE" rather than CONFIG_SPL_MAX_SIZE and CONFIG_SPL_TEXT_BASE. This lets us re-use the same script for both SPL and TPL. Add logic to scripts/Makefile.spl to pass in the right value when preprocessing the script. Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Jagan Teki <jagan@openedev.com> Cc: Maxime Ripard <maxime.ripard@bootlin.com> Cc: Andreas Bießmann <andreas@biessmann.org> Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Cc: Michal Simek <monstr@monstr.eu> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: York Sun <york.sun@nxp.com> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Heiko Schocher <hs@denx.de> Cc: Adam Ford <aford173@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Tested-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Tested-by: Adam Ford <aford173@gmail.com> #da850evm & omap3_logic_somlv Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
* rockchip: Add TPL_MAX_SIZE for RK3288Tom Rini2019-01-261-0/+3
| | | | | | | | | Per Kever Yang, 32768 is a reasonable max size for TPL on RK3288. Cc: Kever Yang <kever.yang@rock-chips.com> Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* ARM: mach-omap2: Kconfig: Allow OMAP5 devices to set entry pointAndrew F. Davis2019-01-262-15/+15
| | | | | | | | | | | Like AM33xx and AM43xx, DRA7xx and AM57xx devices may need to have an non-standard boot address in memory. This may be due to the device being a high security variant, which place the Initial SoftWare (ISW) after certificates and secure software. Allow these devices to set this from Kconfig. Signed-off-by: Andrew F. Davis <afd@ti.com>
* spl: Kconfig: Drop the _SUPPORT postfix from SPL_DFUAndrew F. Davis2019-01-262-2/+2
| | | | | | | | | | The symbol CONFIG_SPL_DFU_SUPPORT in SPL build has the same meaning as CONFIG_DFU in regular U-Boot. Drop the _SUPPORT to allow for cleaner use in code. Signed-off-by: Andrew F. Davis <afd@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Lukasz Majewski <lukma@denx.de>
* arm64: dt: poplar: add optee nodeIgor Opaniuk2019-01-261-0/+7
| | | | | | | | | | As Poplar supports running TF-A with OP-TEE as BL32 payload, add op-tee node in DT, which enables usage of OP-TEE driver (which provides an interface for requesting services from OP-TEE). Signed-off-by: Igor Opaniuk <igor.opaniuk@linaro.org> Reviewed-by: Simon Glass <sjg@chromium.org>
* poplar: clean up board level mmc initialization codeShawn Guo2019-01-252-13/+0
| | | | | | | | We have converted mmc to driver model on Poplar. So let's clean up board level mmc initialization code. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
* poplar: sync up device tree with kernel 4.20Shawn Guo2019-01-253-15/+372
| | | | | | | It adds missing pinctrl headers, updates clock header and sync up Poplar device tree with kernel 4.20 release. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* dts: 820c: Add pinctrl node and uart muxRamon Fried2019-01-252-8/+31
| | | | | | | | * Add pinctrl node for TLMM and add mux request for uart node. * Rename uart to the actual board uart port. * Fix indentendation of sdhc2 node. Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
* arm: mach-snapdragon: pinctrl: clarify gpio disable bitRamon Fried2019-01-251-2/+2
| | | | | | | The TLMM_GPIO_ENABLE bit is actually use to disable the GPIO. change it to TLMM_GPIO_DISABLE so it's clearer. Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
* arm: mach-snapdragon: add pinctrl driver for db820cRamon Fried2019-01-254-3/+61
| | | | | | | Add pinctrl driver for Dragonboard820c, currently with only one mux func to initialize pins for serial console. Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
* arm: mach-snapdragon: db820c: Actually init PLL for serialRamon Fried2019-01-252-0/+43
| | | | | | | The PLL for the UART was not set, and relied on previous initializtion made by LK. add the appropriate initialization. Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
* arm: stm32mp1: deploy spl in root folderSean Nyekjær2019-01-251-3/+3
| | | | | | | | Deploy u-boot-spl.stm32 binary in u-boot root folder like the rest of the boards. This makes it more streamlined when building in Yocto, Buildroot etc.. Signed-off-by: Sean Nyekjaer <sean.nyekjaer@prevas.dk>
* Merge branch 'master' of git://git.denx.de/u-boot-sunxiTom Rini2019-01-2410-471/+1461
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| * arm: sunxi: Enable CLK, RESETJagan Teki2019-01-181-0/+1
| | | | | | | | | | | | | | | | | | CLK and DM_RESET drivers are now available for all of the Allwinner platforms, so enable them in arch/arm/Kconfig Enabling CLK will select DM_RESET by default. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * ARM: dts: sun8i: Update A80 dts(i) from Linux-v4.18-rc3Jagan Teki2019-01-184-471/+1080
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update all A80 devicetree dtsi and dtsi files from Linux-v4.18-rc3 with below commits. arch/arm/boot/dts/sun9i-a80*: commit 190e3138f9577885691540dca59c2f07540bde04 Merge: cafc87023b0d a7affb13b271 Author: Arnd Bergmann <arnd@arndb.de> Date: Tue Mar 27 14:58:00 2018 +0200 Merge tag 'sunxi-h3-h5-for-4.17' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into next/dt include/dt-bindings/*/sun9i-a80-*: commit 783ab76ae553abc23f80ef7511052d055697531b Author: Chen-Yu Tsai <wens@csie.org> Date: Sat Jan 28 20:22:36 2017 +0800 clk: sunxi-ng: Add A80 Display Engine CCU Note: sun9i-a80-cx-a99.dts is updated only uart0, since the same dts is not available in Linux. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * reset: Add Allwinner RESET driverJagan Teki2019-01-181-1/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add common reset driver for all Allwinner SoC's. Since CLK and RESET share common DT compatible, it is CLK driver job is to bind the reset driver. So add CLK bind call on respective SoC driver by passing ccu map descriptor so-that reset deassert, deassert operations held based on ccu reset table defined from CLK driver. Select DM_RESET via CLK_SUNXI, this make hidden section of RESET since CLK and RESET share common DT compatible and code. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
| * clk: Add Allwinner A64 CLK driverJagan Teki2019-01-181-0/+65
| | | | | | | | | | | | | | | | | | | | | | Add initial clock driver for Allwinner A64. Implement USB clock enable and disable functions for OHCI, EHCI, OTG and USBPHY gate and clock registers via ccu clk gate table. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
| * board: sun50i-h5: Add Emlid Neutis N5 supportAleksandr Aleksandrov2019-01-183-0/+281
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Emlid Neutis N5 is a SoM based on Allwinner H5, has a WiFi & BT module, DDR3 RAM and eMMC. - add neutis-devboard target to dtb makefile - add dtsi file for Neutis N5 needs - add config file for Neutis N5 Dev board Signed-off-by: Aleksandr Aleksandrov <aleksandr.aleksandrov@emlid.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> [jagan: update proper commit head] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * sunxi: board: Add i2c initialization for sun50iStefan Mavrodiev2019-01-181-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To use TWI0/1/2 the user can select CONFIG_I2C#_ENABLE. However even the controller is enabled, the mux for the pins are not set. This patch follows the existing mux method. Since the pads are different, separate check is added for each i2c. Tested with A64-SOM204 board. Signed-off-by: Stefan Mavrodiev <stefan@olimex.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
* | ARM: zynq: Remove unused GEM addressesMichal Simek2019-01-241-2/+0
| | | | | | | | | | | | | | With DM in place there is no need to have GEM addresses in headers. None is using them. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | arm64: zynqmp: Remove unused GEM addressesMichal Simek2019-01-241-5/+0
| | | | | | | | | | | | | | With DM in place there is no need to have GEM addresses in headers. None is using them. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | zynq: Kconfig: extend the bootstrap malloc() poolAnton Gerasimov2019-01-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Most of the memory is being consumed by device binding code, more space needed for other data structures. Z-turn board has already hit the limit, others may follow soon. Measuring only the memory consumed in device_bind_common, I've got the following results (in decimal): root_driver: 108 mod_exp_sw: 108 amba: 120 serial@e0000000 aka uart0: 112 serial@e0001000 aka uart1: 88 spi@e000d000 aka qspi: 120 sdhci@e0100000 aka mmc0: 455 sdhci@e0100000.blk: 208 slcr@f8000000: 96 clkc@100: 72 (total) 1487 = 0x5cf of 0x600 Signed-off-by: Anton Gerasimov <tossel@gmail.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | topic-miamiplus: Run CPU at 800MHz for speedgrade-2Mike Looijmans2019-01-241-0/+9
| | | | | | | | | | | | | | | | The miamiplus contains a speedgrade-2 device, which may run the CPU at 800MHz. Change the PLL setting to 800MHz, and adapt the setpoints in the devicetree. Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | arm64: zynqmp: Move SoC sources to mach-zynqmpMichal Simek2019-01-2418-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Similar changes was done for Zynq in past and this patch just follow this pattern to separate cpu code from SoC code. Move arch/arm/cpu/armv8/zynqmp/* -> arch/arm/mach-zynqmp/* And also fix references to these files. Based on "ARM: zynq: move SoC sources to mach-zynq" (sha1: 0107f2403669f764ab726d0d404e35bb9447bbcc) Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | arm64: zynqmp: Setup proper SPI dependencyMichal Simek2019-01-241-0/+2
| | | | | | | | | | | | Select DM_SPI/DM_SPI_FLASH for the whole SoC. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM: zynqmp_r5: Setup DM_ETH/MMC if NET/MMC is enabledMichal Simek2019-01-241-0/+2
| | | | | | | | | | | | Setup proper ETH/MMC dependency for the whole platform. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | arm64: zynqmp: Setup DM_ETH/MMC if NET/MMC is enabledMichal Simek2019-01-241-0/+2
| | | | | | | | | | | | Setup proper ETH/MMC dependency for the whole platform. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | arm64: versal: Setup DM_ETH/MMC if NET/MMC is enabledMichal Simek2019-01-241-0/+2
| | | | | | | | | | | | Setup proper ETH/MMC dependency for the whole platform. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | arm64: zynqmp: Fix mmc node names to be in sync with kernelSiva Durga Prasad Paladugu2019-01-241-2/+2
| | | | | | | | | | | | | | | | | | | | | | This patches renames sd nodes in dts to be in line with kernel. This patch also modifies the references for the same in code. It checks mmc first to have no time penalty for new DT node names based on left-to-right expression evaluation. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | arm64: zynqmp: Do not protect zynqmp_pmufw_version()Michal Simek2019-01-241-3/+1
| | | | | | | | | | | | | | | | | | There is hard dependency for CLK_ZYNQMP to have zynqmp_pmufw_version() but also FPGA code is calling this function which is possible to use without actual CLK_ZYNQMP firmware driver to be enabled. This patch enables the case where only fixed-clock CLK setup is used. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM: mvebu: add support for Allied Telesis x530Chris Packham2019-01-217-1/+539
| | | | | | | | | | | | | | | | | | | | | | This is a range of stackable network switches. The SoC is Armada-385 and there are a number of variants with differing network port configurations. The DP variants are intended for a harsher operating environment so they use a different i2c mux and fit industrial-temp parts. Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
* | arm64: dts: marvell: armada-ap806: reserve PSCI areaHeinrich Schuchardt2019-01-211-0/+11
| | | | | | | | | | | | | | | | | | | | The memory area [0x4000000-0x4200000[ is occupied by the PSCI firmware. Any attempt to access it from U-Boot leads to an immediate crash. So let's make the same memory reservation as the vendor device tree. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Stefan Roese <sr@denx.de>
* | arm: mvebu: turris_mox: Support 1 GB version of Turris MoxMarek Behún2019-01-211-2/+2
| | | | | | | | | | | | | | | | Use get_ram_size to determine if the RAM size on Turris Mox is 512 MiB or 1 GiB. Signed-off-by: Marek Behún <marek.behun@nic.cz> Signed-off-by: Stefan Roese <sr@denx.de>
* | arm: mvebu: dts: Fix Turris Mox device treeMarek Behún2019-01-211-1/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DTC issues a warning because #address-cells and #size-cells properties are not set in the mdio node. Also add ethernet1 alias. Also add RTC node. Also fix USB3 regulator startup delay time. Also fix PCI Express SERDES speed to 5 GHz (this is only cosmetic, the speed value is not used byt the comphy driver for PCI Express, but should be 5 GHz nonetheless). Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
* | arm: mvebu: turris_mox: Check and configure modulesMarek Behún2019-01-211-0/+11
| | | | | | | | | | | | | | | | Check if Mox modules are connected in supported mode, then configure the MDIO addresses of switch modules. Signed-off-by: Marek Behún <marek.behun@nic.cz> Signed-off-by: Stefan Roese <sr@denx.de>
* | ARM: mvebu: sync Armada-38x dts with Linux 4.20Chris Packham2019-01-216-289/+237
| | | | | | | | | | | | | | | | | | | | | | Sync the Armada-38x device tree files with Linux 4.20-rc5. The changes not taken are new compatible strings for the uart and nand flash controller. The nand binding is best updated if/when the mtd/nand infrastructure is updated. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
* | Merge tag 'fsl-qoriq-for-v2019.04-rc1' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2019-01-1811-28/+53
|\ \ | | | | | | | | | | | | | | | | | | Add TFA boot flow for more boards Add TFA boot defconfig for ls1088a and ls2088a. Add dts fixup for PCIe endpoint and root complex.
| * | armv7: dts: ls1021a: Remove aliases property name warningRajesh Bhagat2019-01-173-11/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | Remove aliases property name warning while compilation: Warning (alias_paths): /aliases: aliases property name must include only lowercase and '-' Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8: fsl-layerscape: properly configure qdma ICIDLaurentiu Tudor2019-01-172-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8: ls1043a: correct the PCIe INTx fixupHou Zhiqiang2019-01-171-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | On LS1043A rev1.0 there are 4 interrupt pins for INTx, and on rev1.1 there is only 1 for INTx, so the current fixup is inverse of the fact. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8: ls1043a: add SVR definitions for 23x23 package siliconHou Zhiqiang2019-01-172-0/+5
| | | | | | | | | | | | | | | | | | | | | LS1043A/LS1023A 23x23 package silicon has different SVR:VAR_PER. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8: ls2088ardb: Add TFABOOT supportRajesh Bhagat2019-01-172-7/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | TFABOOT support includes: - ls2088ardb_tfa_defconfig to be loaded by trusted firmware - environment address and size changes for TFABOOT - define BOOTCOMMAND for TFABOOT - remove EL3 specific erratas for TFABOOT Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8: ls1088ardb: Add TFABOOT supportPankit Garg2019-01-171-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | TFABOOT support includes: - ls1088ardb_tfa_defconfig to be loaded by trusted firmware - environment address and size changes for TFABOOT - MC address changes for TFABOOT - define BOOTCOMMAND for TFABOOT - ifc chip select changes for TFABOOT Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8: fsl-layerscape: fixes for TFABOOT frameworkRajesh Bhagat2019-01-172-2/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fixes for TFABOOT framework - update eMMC bootsrc to SD_MMC - Increase buffer size for mcinitcmd from 256 to 512 - Fix mcinitcmd and bootcmd for Secure Boot Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | | arm: dts: am335x-pdu001: Sync with Linux 5.0-rc2Felix Brack2019-01-181-8/+17
| | | | | | | | | | | | | | | | | | This patch synchronizes the PDU001 board DTS file with the one used by Linux 5.0-rc2. Signed-off-by: Felix Brack <fb@ltec.ch>
* | | arm: Kconfig: spelling fixesChris Packham2019-01-181-5/+5
| | | | | | | | | | | | Signed-off-by: Chris Packham <judge.packham@gmail.com>
* | | mach-snapdragon: db410: pinctrl: fix pin countRamon Fried2019-01-181-3/+3
| | | | | | | | | | | | | | | | | | | | | Pin count in APQ8016 was wrong, fix that. Fixes: ad97051b7ff6 ("mach-snapdragon: Introduce pinctrl driver") Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
* | | dts: db410: fix indentationRamon Fried2019-01-181-1/+1
| |/ |/| | | | | Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
* | arm: bootm: fix sp detection at end of address rangeSimon Goldschmidt2019-01-161-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes 'arch_lmb_reserve()' for ARM that tries to detect in which DRAM bank 'sp' is in. This code failed if a bank was at the end of physical address range (i.e. size + length overflowed to 0). To fix this, calculate 'bank_end' as 'size + length - 1' so that such banks end at 0xffffffff, not 0. Fixes: 15751403b6 ("ARM: bootm: don't assume sp is in DRAM bank 0") Reported-by: Frank Wunderlich <frank-w@public-files.de> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
generated by cgit (git 2.34.1) at 2025-02-10 19:50:45 +0000