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| * mips: octeon: octeon_ebb7304_defconfig: Enable MMC supportStefan Roese2021-04-221-1/+7
| | | | | | | | | | | | | | | | | | Enable MMC support including the regulator support on Octeon EBB7304. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Aaron Williams <awilliams@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * mips: octeon: mrvl,octeon_ebb7304.dts: Add MMC DT nodeStefan Roese2021-04-221-0/+57
| | | | | | | | | | | | | | | | | | | | Add the MMC DT node to the Octeon EBB7304 DT file including the regulator node for the MMC power supply. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Aaron Williams <awilliams@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * mips: octeon: mrvl,cn73xx.dtsi: Add MMC DT nodeStefan Roese2021-04-221-0/+27
| | | | | | | | | | | | | | | | | | Add the MMC DT node to the Octeon CN73xx dtsi file. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Aaron Williams <awilliams@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * mmc: octeontx_hsmmc: Add support for MIPS OcteonStefan Roese2021-04-223-56/+763
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Until now, the Octeontx MMC driver did only support the ARM Octeon TX/Tx2 platforms. This patch adds support for the MIPS Octeon platform to this driver. Here a short summary of the changes: - Enable driver compilation for MIPS Octeon, including the MMC related header file - Reorder header inclusion - Switch to using the clk framework to get the input clock - Remove some functions for MIPS Octeon, as some registers don't exist here Signed-off-by: Stefan Roese <sr@denx.de> Cc: Peng Fan <peng.fan@nxp.com> Cc: Aaron Williams <awilliams@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * mips: mt7628: fix the displayed DDR type of mt7628Weijie Gao2021-04-221-0/+3
| | | | | | | | | | | | | | | | | | | | The MT7688KN is a multi-chip package with 8MiB DDR1 KGD. So the DDR type from bootstrap register must be ignored, and always be assumed as DDR1. This patch fixes the displayed DDR type of mt7628. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> Reviewed-by: Stefan Roese <sr@denx.de>
| * mips: mt7628: fix ddr_type for MT7688KNWeijie Gao2021-04-221-3/+3
| | | | | | | | | | | | | | | | | | | | | | The MT7688KN is a multi-chip package with 8MiB DDR1 KGD. So the DDR type from bootstrap register must be ignored, and always be assumed as DDR1. This patch fixes an issue that mt7628_ddr_pad_ldo_config() may be passed with a wrong ddr_type in MT7688KN. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> Reviewed-by: Stefan Roese <sr@denx.de>
| * net: jr2: Fix Serdes6G configurationHoratiu Vultur2021-04-221-4/+23
| | | | | | | | | | | | | | | | | | | | Sometimes no traffic was getting out on the ports, the root cause was a wrong configuration of the Serdes6G, which is used on jr2 pcb111. This patch fixes this issue by applying the correct configuration. Fixes: 5e1d417bec92ac ("net: Add MSCC Jaguar2 network driver.") Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
| * net: jr2: Reset switchHoratiu Vultur2021-04-222-3/+19
| | | | | | | | | | | | | | Make sure to reset the switch core at probe time. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
* | Merge branch '2021-04-22-udoo_neo-update'Tom Rini2021-04-2210-195/+737
|\ \ | |/ |/| | | - Update the udoo_neo platform for DM support
| * ARM: imx: udoo_neo: Convert to ethernet DMPeter Robinson2021-04-203-69/+7
| | | | | | | | | | | | | | | | | | | | Convert the UDOO Neo to ethernet DM support. Signed-off-by: Peter Robinson <pbrobinson@gmail.com> Cc: Francesco Montefoschi <francesco.montefoschi@udoo.org> Cc: Breno Lima <breno.lima@nxp.com> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
| * ARM: imx: udoo_neo: convert to DM_MMCPeter Robinson2021-04-203-39/+8
| | | | | | | | | | | | | | | | | | | | Convert UDOO Neo to use DM MMC. Signed-off-by: Peter Robinson <pbrobinson@gmail.com> Cc: Francesco Montefoschi <francesco.montefoschi@udoo.org> Cc: Breno Lima <breno.lima@nxp.com> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
| * ARM: imx: udoo_neo: Enable OF_CONTROL and DM gpio/pin controlPeter Robinson2021-04-201-0/+8
| | | | | | | | | | | | | | | | | | | | | | Enable OF_CONTROL and DM for gpio and pin control support on the i.MX6SX based Udoo Neo. Signed-off-by: Peter Robinson <pbrobinson@gmail.com> Cc: Francesco Montefoschi <francesco.montefoschi@udoo.org> Cc: Breno Lima <breno.lima@nxp.com> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
| * ARM: board: udoo_neo: Import UDOO Neo dts filesPeter Robinson2021-04-206-87/+714
|/ | | | | | | | | | | | Import the i.MX6SX based UDOO Neo dts files from Linux 5.12-rc1 and sync the i.MX6SX pinfunc.h Signed-off-by: Peter Robinson <pbrobinson@gmail.com> Cc: Francesco Montefoschi <francesco.montefoschi@udoo.org> Cc: Breno Lima <breno.lima@nxp.com> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Fabio Estevam <festevam@gmail.com>
* Merge branch '2021-04-20-assorted-improvements'Tom Rini2021-04-2052-252/+878
|\ | | | | | | | | | | | | | | | | - ARM64 GIC fix, CONFIG_IRQ now moved to Kconfig - IDE, lz4 fixes - octeontx cleanups / enhancements - highbank DM migration - psci updates - Enable use of -fstack-protector
| * Add support for stack-protectorJoel Peshkin2021-04-2014-2/+105
| | | | | | | | | | | | | | | | | | | | Add support for stack protector for UBOOT, SPL, and TPL as well as new pytest for stackprotector Signed-off-by: Joel Peshkin <joel.peshkin@broadcom.com> Adjust UEFI build flags. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
| * x86: correct usage of CFLAGS_NON_EFIHeinrich Schuchardt2021-04-201-4/+6
| | | | | | | | | | | | | | | | | | | | The current usage of the variable CFLAGS_NON_EFI on the x86 architecture deviates from other architectures. Variable CFLAGS_NON_EFI is the list of compiler flags to be removed when building UEFI applications. It is not a list of flags to be added anywhere. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
| * test: fix test/dm/regmap.cHeinrich Schuchardt2021-04-201-4/+5
| | | | | | | | | | | | | | | | | | | | | | | | regmap_read() only fills the first two bytes of val. The last two bytes are random data from the stack. This means the test will fail randomly. For low endian systems we could simply initialize val to 0 and get correct results. But tests should not depend on endianness. So let's use a pointer conversion instead. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
| * toradex: configblock: fix module revision in config blockDenys Drozdov2021-04-201-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | U-boot might display wrong module revision information for modules with an assembly version 'K'. "cfgblock create" does not takes into account all revision digits from PID8. This fix takes into account all digits of PID8 to store module revision. Signed-off-by: Denys Drozdov <denys.drozdov@toradex.com> Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
| * doc: usage: add usage details for reset cmdIgor Opaniuk2021-04-202-0/+27
| | | | | | | | | | | | Add usage details for reset command. Signed-off-by: Igor Opaniuk <igor.opaniuk@foundries.io>
| * sysreset: provide type of reset in do_reset cmdIgor Opaniuk2021-04-202-2/+11
| | | | | | | | | | | | Add additional param for reset cmd, which provides type of reset. Signed-off-by: Igor Opaniuk <igor.opaniuk@foundries.io>
| * sysreset: psci: use psci driver exported functionsIgor Opaniuk2021-04-201-6/+2
| | | | | | | | | | | | | | Use psci driver exported functions for reset/poweroff, instead of invoking directly invoke_psci_fn. Signed-off-by: Igor Opaniuk <igor.opaniuk@foundries.io>
| * psci: add features/reset2 supportIgor Opaniuk2021-04-202-0/+71
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adds support for: * PSCI_FEATURES, which was introduced in PSCI 1.0. This provides API that allows discovering whether a specific PSCI function is implemented and its features. * SYSTEM_RESET2, which was introduced in PSCI 1.1, which extends existing SYSTEM_RESET. It provides support for vendor-specific resets, providing reset_type as an additional param. For additional details visit [1]. Implementations of some functions were borrowed from Linux PSCI driver code [2]. [1] https://developer.arm.com/documentation/den0022/latest/ [2] drivers/firmware/psci/psci.c Signed-off-by: Igor Opaniuk <igor.opaniuk@foundries.io>
| * psci: add v1.0/v1.1 definitions from LinuxIgor Opaniuk2021-04-201-0/+28
| | | | | | | | | | | | Sync and add PSCI API versions 1.0/1.1 definitions from Linux. Signed-off-by: Igor Opaniuk <igor.opaniuk@foundries.io>
| * sysinfo.h: Add re-inclusion guardTom Rini2021-04-201-0/+4
| | | | | | | | | | | | | | Add #ifndef __SYSINFO_H__ ... #endif to prevent re-inclusion of this file. Signed-off-by: Tom Rini <trini@konsulko.com>
| * arm: highbank: Update maintainershipAndre Przywara2021-04-201-1/+1
| | | | | | | | | | | | | | | | | | | | Rob does not have access to any Calxeda systems anymore, also has expressed a lack of interest in those systems in the past. I have multiple working Midway nodes under my desk in the office, so am happy to take over maintainership. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * arm: highbank: Do DRAM init from DTAndre Przywara2021-04-203-3/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | So far U-Boot was hard coding a (surely sufficient) memory size of 512 MB, even though all machines out there have at least 4GB of DRAM. Since U-Boot uses its memory knowledge to populate the EFI memory map, we are missing out here, at best losing everything beyond 4GB on Midway boxes (which typically come with 8GB of DRAM). Since the management processor populated the DT memory node already with the detected DRAM size and configuration, we use that to populate U-Boot's memory bank information, which is the base for the UEFI memory map. This finally allows us to get rid of the NR_DRAM_BANKS=0 hack, that we had in place to avoid U-Boot messing up the DT memory node before loading the kernel. Also, to cover the whole of memory, we need to enable PHYS_64BIT. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * arm: highbank: Remove artificial SDRAM sizeAndre Przywara2021-04-201-6/+0
| | | | | | | | | | | | | | | | | | | | | | | | So far we were defining a somewhat confusing PHYS_SDRAM_1_SIZE variable, which originally was only used for setting the memtest boundaries. This definition in highbank.h has been removed about a year ago (moved to Kconfig), so we also don't need the hard-coded size definition any longer. Get rid of the misleading memory size definition, which was actually wrong anyway (it's 4088 MB for those machines with just 4GB of DRAM). Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * net: calxedagmac: Convert to DM_ETHAndre Przywara2021-04-208-81/+137
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To squash that nasty warning message and make better use of the newly gained OF_CONTROL feature, let's convert the calxedagmac driver to the "new" driver model. The conversion is pretty straight forward, mostly just adjusting the use of the involved data structures. The only actual change is the required split of the receive routine into a receive and free_pkt part. Also this allows us to get rid of the hardcoded platform information and explicit init calls. This also uses the opportunity to wrap the code decoding the MMIO register base address, to make it safe for using PHYS_64BIT later. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
| * arm: highbank: Enable OF_CONTROLAndre Przywara2021-04-204-2/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All Calxeda machines are actually a poster book example of device tree usage: the DT is loaded from flash by the management processor into DRAM, the memory node is populated with the detected DRAM size and this DT is then handed over to the kernel. So it's a shame that U-Boot didn't participate in this chain, but fortunately this is easy to fix: Define CONFIG_OF_CONTROL and CONFIG_OF_BOARD, and provide a trivial function to tell U-Boot about the (fixed) location of the DTB in DRAM. Then enable DM_SERIAL, to let the PL011 driver pick up the UART platform data from the DT. Also define AHCI, to bring this driver into the driver model world as well. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * arm: highbank: Limit FDT and initrd load addressesAndre Przywara2021-04-201-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | So far on Highbank/Midway machines U-Boot only ever uses 512MB of DRAM, even though the machines have typically 4GB and 8GB, respectively. That means that so far we didn't need an extra limit for placing the DTB and initrd, as the 512MB are lower than the kernel's limit ("lowmem", typically 768MB). With U-Boot now needing to learn about the actual memory size (to correctly populate the EFI memory map), it might relocate fdt and initrd to the end of DRAM, which is out of reach of the kernel. So add limiting values to the fdt_high and initrd_high environment variables, to prevent U-Boot from using too high addresses. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * doc: device-tree-bindings: regulator: anatop regulatorYing-Chun Liu (PaulLiu)2021-04-201-0/+45
| | | | | | | | | | | | | | | | | | | | | | Document the bindings for fsl,anatop-regulator Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org> Reviewed-by: Sean Anderson <sean.anderson@seco.com> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Peng Fan <peng.fan@nxp.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
| * power: regulator: add driver for ANATOP regulatorYing-Chun Liu (PaulLiu)2021-04-203-0/+289
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Anatop is an integrated regulator inside i.MX6 SoC. There are 3 digital regulators which controls PU, CORE (ARM), and SOC. And 3 analog regulators which controls 1P1, 2P5, 3P0 (USB). This patch adds the Anatop regulator driver. Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org> Reviewed-by: Sean Anderson <sean.anderson@seco.com> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Peng Fan <peng.fan@nxp.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
| * cmd: CONFIG_CMD_MMC depends on CONFIG_MMCHeinrich Schuchardt2021-04-201-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Trying to compile with CONFIG_CMD_MMC=y and CONFIG_MMC=n leads to errors: riscv64-linux-gnu-ld.bfd: cmd/built-in.o: in function `do_mmcops': cmd/mmc.c:984: undefined reference to `get_mmc_num' riscv64-linux-gnu-ld.bfd: cmd/built-in.o: in function `do_mmc_setdsr': cmd/mmc.c:873: undefined reference to `find_mmc_device' Add missing dependency. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
| * net: octeontx: smi: fix mii probeTim Harvey2021-04-201-0/+2
| | | | | | | | | | | | | | | | | | The fdt node offset is apparently not set properly when probed causing no MDIO busses to be found. Fix this by obtaining the offset. Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Stefan Roese <sr@denx.de>
| * drivers: ata: ahci: update max id if it is more than available portsSuneel Garapati2021-04-201-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | After check for maximum between max id and available ports, also check if available port count is less than max id and update. In the case of the CN8030 OcteonTX SoC max_id needs to be reduced to the number of ports found otherwise the following occurs on a scan: GW6404-B> scsi scan scanning bus for devices... Target spinup took 0 ms. AHCI 0001.0300 32 slots 1 ports 6 Gbps 0x1 impl SATA mode flags: 64bit ncq ilck stag pm led clo only pmp fbss pio slum part ccc apst Device 0: (0:0) Vendor: ATA Prod.: SanDisk SD8SFAT0 Rev: Z233 Type: Hard Disk Capacity: 61057.3 MB = 59.6 GB (125045424 x 512) "Synchronous Abort" handler, esr 0x96000006 elr: 000000000052f824 lr : 000000000052fa10 (reloc) elr: 000000007fee9824 lr : 000000007fee9a10 x0 : 0000000000000001 x1 : 0000000000000001 x2 : 000000007bea3528 x3 : 000000007bea3580 x4 : 0000000000000200 x5 : 0000000000000000 x6 : 0000000000000002 x7 : 000000007bea3540 x8 : 00000000fffffff8 x9 : 0000000000000008 x10: 00000000000186a0 x11: 000000000000000d x12: 0000000000000006 x13: 000000000001869f x14: 0000000000000007 x15: 00000000ffffffff x16: 000000007ff439a5 x17: 000000007ff5730c x18: 000000007bea9de0 x19: 000000007ff7a580 x20: 000000007bec79f8 x21: 0000000000000000 x22: 000000007bea3580 x23: 0000000000000000 x24: 0000000000000000 x25: 000000007bec7a00 x26: 00000000ffffffc0 x27: 000000007bec79d0 x28: 000000007beb51c0 x29: 000000007bea3480 Code: 91246800 940130c2 12800000 1400004f (b9402ae0) Resetting CPU ... Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Reviewed-by: Stefan Roese <sr@denx.de>
| * drivers: net: octeontx: fix QSGMIITim Harvey2021-04-201-13/+7
| | | | | | | | | | | | | | Revert a change that occured between the Marvell SDK-10.1.1.0 and SDK-10.3.1.1 which broke QSMII phy support. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
| * arm: octeontx: enable WDT_SBSATim Harvey2021-04-201-0/+1
| | | | | | | | | | | | | | The OcteonTX uses ARM's SBSA Watchdog device Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Stefan Roese <sr@denx.de>
| * arm: octeontx: support generic distro configTim Harvey2021-04-201-5/+26
| | | | | | | | | | | | | | Support Generic Distro Default config Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Stefan Roese <sr@denx.de>
| * arm: octeontx: move CONFIG_SUPPORT_RAW_INITRD to configsTim Harvey2021-04-203-2/+2
| | | | | | | | | | | | | | | | Move CONFIG_SUPPORT_RAW_INITRD out of the octeontx_common header and into the defconfig files. Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Stefan Roese <sr@denx.de>
| * lz4: Fix unaligned accessesKarl Beldan2021-04-201-3/+12
| | | | | | | | Signed-off-by: Karl Beldan <karl.beldan+oss@gmail.com>
| * Fix IDE commands issued, fix endian issues, fix non MMIOReinoud Zandijk2021-04-202-110/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fixes IDE issues found on the Malta board under Qemu: 1) DMA implied commands were sent to the controller in stead of the PIO variants. The rest of the code is DMA free and written for PIO operation. 2) direct pointer access was used to read and write the registers instead of the inb/inw/outb/outw functions/macros. Registers don't have to be memory mapped and ATA_CURR_BASE() does not have to return an offset from address zero. 3) Endian isues in ide_ident() and reading/writing data in general. Names were corrupted and sizes misreported. Tested malta_defconfig and maltael_defconfig to work again in Qemu. Signed-off-by: Reinoud Zandijk <reinoud@NetBSD.org> Tested-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
| * sandbox: enable IRQ using select for sandbox architectureWasim Khan2021-04-205-4/+1
| | | | | | | | | | | | | | | | Enable IRQ using select for sandbox architecture. Signed-off-by: Wasim Khan <wasim.khan@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * arch: Kconfig: enable IRQ using select for x86 architectureWasim Khan2021-04-201-1/+1
| | | | | | | | | | | | | | | | | | | | use 'select' to enable IRQ as it does not have architecture specific dependency. Signed-off-by: Wasim Khan <wasim.khan@nxp.com> Reviewed-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * arch: arm: update Kconfig to select IRQ when GIC_V3_ITS is enabledWasim Khan2021-04-201-0/+1
| | | | | | | | | | | | | | | | | | | | GIC_V3_ITS uses UCLASS_IRQ driver. Update Kconfig to select IRQ when GIC_V3_ITS is enabled. Signed-off-by: Wasim Khan <wasim.khan@nxp.com> Reviewed-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Vladimir Oltean <vladimir.oltean@nxp.com>
| * misc: make CONFIG_IRQ selectable for all platformsWasim Khan2021-04-201-3/+2
| | | | | | | | | | | | | | | | | | UCLASS_IRQ driver is not Intel specific. Make CONFIG_IRQ selectable for all platforms. Signed-off-by: Wasim Khan <wasim.khan@nxp.com> Tested-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * arm64: gic-v3-its: Clear the Pending table before enabling LPIsHou Zhiqiang2021-04-201-1/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The GICv3 RM requires "The first 1KB of memory for the LPI Pending tables must contain only zeros on initial allocation, and this must be visible to the Redistributors, or else the effect is UNPREDICTABLE". And as the following statement, we here clear the whole Pending tables instead of the first 1KB. "An LPI Pending table that contains only zeros, including in the first 1KB, indicates that there are no pending LPIs. The first 1KB of the LPI Pending table is IMPLEMENTATION DEFINED. However, if the first 1KB of the LPI Pending table and the rest of the table contain only zeros, this must indicate that there are no pending LPIs." And there isn't any pending LPI under U-Boot, so it's unnecessary to load the contents of the Pending table during the enablement, then set the GICR_PENDBASER.PTZ flag. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Tested-by: Vladimir Oltean <vladimir.oltean@nxp.com> # NXP LS1028A Reviewed-by: Wasim Khan <wasim.khan@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * boards: amlogic: update documentation for PCIe supportNeil Armstrong2021-04-201-0/+2
| | | | | | | | Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
| * configs: meson64: add NVME boot targetNeil Armstrong2021-04-201-0/+7
| | | | | | | | | | | | Let's add a boot target for NVMe so we can do a full boot over NVMe. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
| * configs: khadas-vim3: enable PCIe and NVMeNeil Armstrong2021-04-202-0/+10
| | | | | | | | | | | | | | Now we have PCIe, let's also enable NVMe to access an eventual NVMe SSDs connected on the M.2 slot. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
| * arm: dts: meson-khadas-vim3: enable PCIe in U-bootNeil Armstrong2021-04-201-0/+4
| | | | | | | | | | | | | | Enable PCIe by default in u-boot, this should eventually be made dynamic in the runtime board config depending on the MCU configuration. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
generated by cgit (git 2.34.1) at 2025-09-28 14:45:15 +0000