summaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
...
| * arm: mach-k3: am642: Add support for boot device detectionKeerthy2021-05-125-0/+198
| | | | | | | | | | | | | | | | | | | | | | | | | | AM642 allows for booting from primary or backup boot media. Both media can be chosen individually based on switch settings. ROM looks for a valid image in primary boot media, if not found then looks in backup boot media. In order to pass this boot media information to boot loader, ROM stores a value at a particular address. Add support for reading this information and determining the boot media correctly. Signed-off-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
| * arm: mach-k3: Add basic support for AM642 SoC definitionDave Gerlach2021-05-123-4/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The AM642 SoC belongs to the K3 Multicore SoC architecture platform, providing advanced system integration to enable applications such as Motor Drives, PLC, Remote IO and IoT Gateways. Some highlights of this SoC are: * Dual Cortex-A53s in a single cluster, two clusters of dual Cortex-R5F MCUs, and a single Cortex-M4F. * Two Gigabit Industrial Communication Subsystems (ICSSG). * Integrated Ethernet switch supporting up to a total of two external ports. * PCIe-GEN2x1L, USB3/USB2, 2xCAN-FD, eMMC and SD, UFS, OSPI memory controller, QSPI, I2C, eCAP/eQEP, ePWM, ADC, among other peripherals. * Centralized System Controller for Security, Power, and Resource Management (DMSC). See AM64X Technical Reference Manual (SPRUIM2, Nov 2020) for further details: https://www.ti.com/lit/pdf/spruim2 Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
| * Revert "fdt: translate address if #size-cells = <0>"Dario Binacchi2021-05-129-141/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit d64b9cdcd475eb7f07b49741ded87e24dae4a5fc. As pointed by [1] and [2], the reverted patch made every DT 'reg' property translatable. What the patch was trying to fix was fixed in a different way from previously submitted patches which instead of correcting the generic address translation function fixed the issue with appropriate platform code. [1] https://patchwork.ozlabs.org/project/uboot/patch/1614324949-61314-1-git-send-email-bmeng.cn@gmail.com/ [2] https://lore.kernel.org/linux-clk/20210402192054.7934-1-dariobin@libero.it/T/ Signed-off-by: Dario Binacchi <dariobin@libero.it> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * clk: ti: am3-dpll: use custom API for memory accessDario Binacchi2021-05-121-33/+53
| | | | | | | | | | | | | | | | | | | | Using the custom TI functions required not only replacing common memory access functions but also rewriting the routines used to set bypass and lock states. As for readl() and writel(), they also required the address of the register to be accessed, a parameter that is hidden by the TI clk module. Signed-off-by: Dario Binacchi <dariobin@libero.it>
| * clk: ti: gate: use custom API for memory accessDario Binacchi2021-05-121-11/+12
| | | | | | | | | | | | | | Replaces the common memory access functions used by the driver with the ones exported from the TI clk module. Signed-off-by: Dario Binacchi <dariobin@libero.it>
| * clk: ti: change clk_ti_latch() signatureDario Binacchi2021-05-124-24/+28
| | | | | | | | | | | | | | | | | | The clock access functions exported by the clk header use the struct clk_ti_reg parameter to get the address of the register. This must also apply to clk_ti_latch(). Changes to TI's clk-mux and clk-divider drivers prevented the patch from generating compile errors. Signed-off-by: Dario Binacchi <dariobin@libero.it>
| * clk: ti: add custom API for memory accessDario Binacchi2021-05-122-0/+98
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As pointed by [1] and [2], commit d64b9cdcd4 ("fdt: translate address if #size-cells = <0>") is wrong: - It makes every 'reg' DT property translatable. It changes the address translation so that for an I2C 'reg' address you'll get back as reg the I2C controller address + reg value. - The quirk must be fixed with platform code. The clk_ti_get_reg_addr() is the platform code able to make the correct address translation for the AM33xx clocks registers. Its implementation was inspired by the Linux Kernel code. [1] https://patchwork.ozlabs.org/project/uboot/patch/1614324949-61314-1-git-send-email-bmeng.cn@gmail.com/ [2] https://lore.kernel.org/linux-clk/20210402192054.7934-1-dariobin@libero.it/T/ Signed-off-by: Dario Binacchi <dariobin@libero.it>
* | Merge tag 'u-boot-imx-20210502' of ↵Tom Rini2021-05-1179-260/+16163
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-imx u-boot-imx-20210502 ------------------- - mx6: fixes for Ventana - local fixes from maintainer - imx7d: Ronetix's iMX7-CM - imx8: Ronetix iMX8MQ-CM Engicam i.Core MX8M Compulab iot-gate-imx8 - Fixes i.MX8 documentation - Fixes phy usage with fec
| * | ARM:imx:imx8mq-cm: Add support for Ronetix iMX8MQ-CMIlko Iliev2021-05-0214-5/+3041
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Supported peripherals: Ethernet, eMMC, Serial. U-Boot SPL 2021.04-00911-g5fa1e2ffeb-dirty (Apr 23 2021 - 09:11:14 +0200) Normal Boot Trying to boot from MMC2 U-Boot 2021.04-00911-g5fa1e2ffeb-dirty (Apr 23 2021 - 09:11:14 +0200) CPU: Freescale i.MX8MQ rev2.1 at 1000 MHz Reset cause: POR Model: Ronetix iMX8M-CM SoM DRAM: 1 GiB WDT: Started with servicing (60s timeout) MMC: FSL_SDHC: 0, FSL_SDHC: 1 Loading Environment from MMC... OK In: serial Out: serial Err: serial Net: Warning: ethernet@30be0000 (eth0) using random MAC address - 42:0d:e7:78:da:53 eth0: ethernet@30be0000 Hit any key to stop autoboot: 0 u-boot=> Signed-off-by: Ilko Iliev <iliev@ronetix.at>
| * | imx: Add support for Ronetix's iMX7-CM boardIlko Iliev2021-05-0212-0/+974
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Console boot log: U-Boot SPL 2021.04-00836-ga6232e065d-dirty (Apr 16 2021 - 15:16:35 +0200) Trying to boot from MMC1 U-Boot 2021.04-00836-ga6232e065d-dirty (Apr 16 2021 - 15:16:35 +0200) CPU: Freescale i.MX7D rev1.3 1000 MHz (running at 792 MHz) CPU: Commercial temperature grade (0C to 95C) at 44C Reset cause: POR Model: Ronetix iMX7-CM Board Board: iMX7-CM DRAM: 512 MiB PMIC: PFUZE3000 DEV_ID=0x30 REV_ID=0x11 MMC: FSL_SDHC: 0, FSL_SDHC: 2 Loading Environment from MMC... OK In: serial Out: serial Err: serial Net: Warning: ethernet@30be0000 (eth0) using random MAC address - fe:be:37:01:5a:3f eth0: ethernet@30be0000 Hit any key to stop autoboot: 0 Signed-off-by: Ilko Iliev <iliev@ronetix.at>
| * | pci: imx: disable imx6sdl LTSSM upon driver removeTim Harvey2021-05-021-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit 6ecbe1375671 ("drivers: pci: imx: add imx_pcie_remove function") attempted to resolve an issue caused by MX6QDL not having a proper intneral PCIe core reset and thus hanging during kernel init if the bootloader had enabled PCI. The issue exists for IMX6Q, IMX6D, IXM6S, and IMX6DL. Fix the case for IMX6S and IMX6DL getting missed. This fixes IMX6S and IMX6DL with PCI enabled in U-Boot booting for Linux v4.11+. Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Fabio Estevam <festevam@gmail.com>
| * | imx: mkimage_fit_atf: fix file size reportingTim Harvey2021-05-021-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | instead using ls and awk to determine file size use stat instead. This fixes an invalid size reporting for user or group names that have spaces in them. This adds a dependency on the stat application which is part of the coreutils package which also includes ls. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
| * | imx: imx8: Update README with somewhat correct firmware versionsPriit Laes2021-05-021-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current setup instructions for i.MX8QM MEK board include somewhat conflicting instructions, so here's an attempt to fix it. After trying both sets of firmwares, I can conclude that both of them fail to work: - no boot at all with imx-sc-firmware-0.7 / firmware-imx-7.6 - partial success with imx-sc-firmware-1.1 / firmware-imx-8.0: U-Boot 2021.04-rc3-00135-ge0669a43c8 (Mar 08 2021 - 16:49:08 +0200) CPU: NXP i.MX8QM RevB A53 at 1200 MHz Model: Freescale i.MX8QM MEK Board: iMX8QM MEK mu_hal_receivemsg timeout Build: SCFW 65afe5f6, SECO-FW 65afe5f6, ATF a-20190 mu_hal_receivemsg timeout sc_misc_get_boot_dev: res:16 Boot: SD0 DRAM: mu_hal_sendmsg timeout sc_rm_is_memreg_owned: mr:0 res:21 ... Signed-off-by: Priit Laes <priit.laes@paf.com>
| * | arm: imx8m: add support for Compulab iot-gate-imx8 (imx8mm-cl-iot-gate)Ying-Chun Liu (PaulLiu)2021-05-0216-0/+8289
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add initial support for Compulab iot-gate-imx8 board (imx8mm-cl-iot-gate). The initial support includes: - MMC - eMMC - I2C - FEC - Serial console Signed-off-by: Kirill Kapranov <kirill.kapranov@compulab.co.il> Signed-off-by: Uri Mashiach <uri.mashiach@compulab.co.il> Signed-off-by: Valentin Raevsky <valentin@compulab.co.il> Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org> Cc: Peter Robinson <pbrobinson@gmail.com>
| * | arm: dts: add imx8mm-cl-iot-gate dts fileYing-Chun Liu (PaulLiu)2021-05-023-0/+810
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add board dts for imx8mm-cl-iot-gate Signed-off-by: Kirill Kapranov <kirill.kapranov@compulab.co.il> Signed-off-by: Uri Mashiach <uri.mashiach@compulab.co.il> Signed-off-by: Valentin Raevsky <valentin@compulab.co.il> Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org> Cc: Peter Robinson <pbrobinson@gmail.com>
| * | net: fec: Only unregister MII bus if we registered itSean Anderson2021-05-021-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If we fail to probe for whatever reason, we cannot unregister/free the MII bus unless we registered it with fec_get_miibus. This fixes FECs sharing an MDIO bus from destroying it, preventing the other FEC from using it. Fixes: 6a895d039b ("net: Update eQos driver and FEC driver to use eth phy interfaces") Signed-off-by: Sean Anderson <sean.anderson@seco.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
| * | net: fec: Don't use disabled physSean Anderson2021-05-021-6/+9
| | | | | | | | | | | | | | | | | | | | | If a phy is disabled, don't use it. This matches Linux's behavior. Signed-off-by: Sean Anderson <sean.anderson@seco.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
| * | pci: pci-uclass: Add board_pci_fixup_dev for DM_PCITim Harvey2021-05-022-0/+14
| | | | | | | | | | | | | | | | | | | | | Add a board_pci_fixup_dev weak function to allow PCI device fixups during enumeration. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
| * | pci: Update the highest subordinate bus number for bridge setupMasami Hiramatsu2021-05-021-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update the highest subordinate bus number after probing the devices under the bus for setting up the bridge correctly. The commit 42f3663a3f67 ("pci: Update to use new sequence numbers") removed this but it is required if a PCIe bridge is under the bus. Fixes: 42f3663a3f67 ("pci: Update to use new sequence numbers") Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
| * | arm: dts: imx6qdl-gw552x.dtsi: fix VBUS supplyTim Harvey2021-05-021-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove the invalid 'regulator-always-on' property to resolve: starting USB... Bus usb@2184000: Error enabling VBUS supply (ret=-13) probe failed, error -13 Bus usb@2184200: USB EHCI 1.00 Signed-off-by: Tim Harvey <tharvey@gateworks.com>
| * | imx: ventana: add delay before reading EEPROMTim Harvey2021-05-021-0/+1
| | | | | | | | | | | | | | | | | | fixes: d863d054397a ("imx: ventana: convert U-Boot to OF_CONTROL using FIT image") Signed-off-by: Tim Harvey <tharvey@gateworks.com>
| * | board: imx8mm: Add Engicam i.Core MX8M Mini C.TOUCH 2.0Jagan Teki2021-05-026-0/+232
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Engicam C.TOUCH 2.0 is an EDIMM compliant general purpose Carrier board. Genaral features: - Ethernet 10/100 - Wifi/BT - USB Type A/OTG - Audio Out - CAN - LVDS panel connector i.Core MX8M Mini is an EDIMM SoM based on NXP i.MX8M Mini from Engicam. i.Core MX8M Mini needs to mount on top of this Carrier board for creating complete i.Core MX8M Mini C.TOUCH 2.0 board. Linux dts commit details: commit <a142252061ff> ("arm64: dts: imx8mm: Add Engicam i.Core MX8M Mini C.TOUCH 2.0") Add support for it. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * | board: imx8mm: Add Engicam i.Core MX8M Mini EDIMM2.2 Starter KitJagan Teki2021-05-0213-0/+2427
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Engicam EDIMM2.2 Starter Kit is an EDIMM 2.2 Form Factor Capacitive Evaluation Board. Genaral features: - LCD 7" C.Touch - microSD slot - Ethernet 1Gb - Wifi/BT - 2x LVDS Full HD interfaces - 3x USB 2.0 - 1x USB 3.0 - HDMI Out - Mini PCIe - MIPI CSI - 2x CAN - Audio Out i.Core MX8M Mini is an EDIMM SoM based on NXP i.MX8M Mini from Engicam. i.Core MX8M Mini needs to mount on top of this Evaluation board for creating complete i.Core MX8M Mini EDIMM2.2 Starter Kit. Linux dts commit details: commit <051c08eea682> ("arm64: dts: imx8mm: Add Engicam i.Core MX8M Mini EDIMM2.2 Starter Kit") Add support for it. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * | arm64: dts: imx8mm: Add Engicam i.Core MX8M Mini SoMJagan Teki2021-05-021-0/+232
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | i.Core MX8M Mini is an EDIMM SoM based on NXP i.MX8M Mini from Engicam. General features: - NXP i.MX8M Mini - Up to 2GB LDDR4 - 8/16GB eMMC - Gigabit Ethernet - USB 2.0 Host/OTG - PCIe Gen2 interface - I2S - MIPI DSI to LVDS - rest of i.MX8M Mini features i.Core MX8M Mini needs to mount on top of Engicam baseboards for creating complete platform solutions. Linux dts commit details: commit <470d6dad5ddd> ("arm64: dts: imx8mm: Add Engicam i.Core MX8M Mini SoM") Add support for it. Signed-off-by: Matteo Lisi <matteo.lisi@engicam.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * | arm64: dts: imx8mm: Add common -u-boot.dtsiJagan Teki2021-05-027-209/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | /soc@0 aips1 aips2 aips3 clk iomuxc osc_24m are common node enablements across imx8mm platform for dm-spi, dm-pre-reloc stages. Move them into common dtsi, imx8mm-u-boot.dtsi Cc: Tim Harvey <tharvey@gateworks.com> Cc: Adam Ford <aford173@gmail.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Teresa Remmet <t.remmet@phytec.de> Cc: Igor Opaniuk <igor.opaniuk@toradex.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * | include: configs: ge: avoid shell on boot failureIan Ray2021-05-022-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | Prevent shell access on boot failure by entering an infinite loop. Signed-off-by: Ian Ray <ian.ray@ge.com> Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
| * | include: configs: ge: simplify default boot commandIan Ray2021-05-022-14/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | Minor cosmetic changes to unify `CONFIG_EXTRA_ENV_SETTINGS' indentation between Bx50v3 and PPD to make comparison and review easier and simplify the default boot command. Signed-off-by: Ian Ray Ian Ray <ian.ray@ge.com> Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
| * | include: configs: ge: bx50v3: drop USB bootIan Ray2021-05-021-5/+0
| | | | | | | | | | | | | | | | | | | | | Remove unsupported USB boot. Signed-off-by: Ian Ray <ian.ray@ge.com> Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
| * | configs: ge: use non-persistent environmentIan Ray2021-05-022-2/+2
| | | | | | | | | | | | | | | | | | | | | Disable the unused persistent environment. Signed-off-by: Ian Ray <ian.ray@ge.com> Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
| * | configs: ge: bx50v3: adjust watchdog periodIan Ray2021-05-021-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Increase watchdog period, in order to accomodate recent kernel size and configuration changes. Signed-off-by: Ian Ray <ian.ray@ge.com> Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
| * | board: ge: bx50v3: add phy reset GPIOSebastian Reichel2021-05-021-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add PHY's reset GPIO, so that U-Boot does a PHY hard reset. This is needed, since the PHY might become unresponsive if watchdog reboots the system while a transaction is ongoing. The reset GPIO is added to the U-Boot specific DT files, since the kernel does not setup the reserved registers correctly after resetting the PHY and thus must not reset it. Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
| * | board: ge: bx50v3: fix crystal bitSebastian Reichel2021-05-021-0/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | The DA9063 enables the CRYSTAL bit by default, but there is no crystal populated on the BA16 system on module. Without explicitly clearing the CRYSTAL bit the system runs unstable and sometimes reboots unexpectedly. Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
| * | Makefile: Fix generation of flash.bin u-boot.itb with binmanMarek Vasut2021-05-021-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In case binman is enabled, the u-boot.itb is generated using this tool and there is no direct u-boot.itb target, but instead the binman tool must be invoked. Add support for this case. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
* | | configs: Resync with savedefconfigTom Rini2021-05-11538-545/+0
| | | | | | | | | | | | | | | | | | Rsync all defconfig files using moveconfig.py Signed-off-by: Tom Rini <trini@konsulko.com>
* | | Merge branch 'finish-DM_MMC-migration'Tom Rini2021-05-1125-373/+29
|\ \ \ | |_|/ |/| | | | | | | | | | | - Complete the migration to LIBATA requiring BLK to be enabled. - Complete the migration to DM_MMC being required for non-SPL/TPL U-Boot.
| * | DM: DM_MMC migration is now mandatory for non-SPLTom Rini2021-05-1114-3/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | As it has been now two years past the migration deadline, it is required to have migrated. Remove the check from the Makefile and rework some of the Kconfig logic slightly to get the functional dependencies of DM_MMC / BLK right in both the SPL and non-SPL case. Signed-off-by: Tom Rini <trini@konsulko.com>
| * | ata: Make LIBATA means AHCI is enabled mandatory.Tom Rini2021-05-112-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | The migration deadline for having LIBATA mean that AHCI is also enabled was v2019.07. As that has long since passed, adjust the Kconfig dependencies. Signed-off-by: Tom Rini <trini@konsulko.com>
| * | boards: Disable CMD_SATA on platforms that no longer have a SATA driver enabledTom Rini2021-05-113-14/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | There are a number of platforms that depend on a SATA driver that has been converted to require AHCI but the platforms themselves are behind on other migrations that would make it trivial to enable AHCI. Disable SATA in these cases. Signed-off-by: Tom Rini <trini@konsulko.com>
| * | ppc: Remove some SECURE_BOOT defconfigsTom Rini2021-05-117-353/+1
|/ / | | | | | | | | | | | | | | | | | | | | These specific configs are missing a number of migrations. In addition, they are blocking completion of the now-expired DM_MMC migration as it requires enabling BLK. Cc: Priyanka Jain <priyanka.jain@nxp.com> Cc: Ruchika Gupta <ruchika.gupta@nxp.com> Cc: Sumit Garg <sumit.garg@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com>
* | Prepare v2021.07-rc2Tom Rini2021-05-101-1/+1
| | | | | | | | Signed-off-by: Tom Rini <trini@konsulko.com>
* | Merge https://source.denx.de/u-boot/custodians/u-boot-x86Tom Rini2021-05-104-29/+76
|\ \ | | | | | | | | | | | | - x86: correct regwidth prompt in cbsysinfo - virtio: convert README.virtio to reST
| * | MAINTAINERS: Add an entry for VirtIOBin Meng2021-05-101-0/+12
| | | | | | | | | | | | | | | | | | | | | This was missed when VirtIO support was initially brought to U-Boot back in 2018. Add an entry for it and list myself as the maintainer. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
| * | doc: develop: Convert README.virtio to reSTBin Meng2021-05-102-28/+63
| | | | | | | | | | | | | | | | | | | | | This converts the existing README.virtio to reST, and puts it under the develop/driver-model/ directory. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: Correct regwidth prompt in cbsysinfoSimon Glass2021-05-101-1/+1
|/ / | | | | | | | | | | | | This should be 'regwidth', not 'baud'. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | Merge https://source.denx.de/u-boot/custodians/u-boot-riscvTom Rini2021-05-076-2/+51
|\ \
| * | cmd/exception: support ebreak exception on RISC-VHeinrich Schuchardt2021-05-052-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | The ebreak instruction should generate a breakpoint exception. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
| * | atcspi200: Add timeout mechanism in spi_xfer()Dylan Jhong2021-05-051-2/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | Adding timeout mechanism to avoid spi driver from stucking in the while loop in __atcspi200_spi_xfer(). Signed-off-by: Dylan Jhong <dylan@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
| * | riscv: cpu: fu740: clear feature disable CSRGreen Wan2021-05-051-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Clear feature disable CSR to turn on all features of hart. The detail is specified at section, 'SiFive Feature Disable CSR', in user manual https://sifive.cdn.prismic.io/sifive/aee0dd4c-d156-496e-a6c4-db0cf54bbe68_sifive_U74MC_rtl_full_20G1.03.00_manual.pdf Signed-off-by: Green Wan <green.wan@sifive.com> Reviewed-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
| * | riscv: cpu: Add callback to init each coreGreen Wan2021-05-052-0/+15
| |/ | | | | | | | | | | | | | | | | | | | | Add a callback harts_early_init() to start.S to allow different riscv hart perform setup code for each hart as early as possible. Since all the harts enter the callback, they must be able to run the same setup. Signed-off-by: Green Wan <green.wan@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | Merge branch '2021-05-06-misc-updates'Tom Rini2021-05-0630-36/+516
|\ \ | |/ |/| | | | | | | | | | | - Allow for boards to update bootargs before booting the OS (helpful in some forms of secure boot). - Enhance GPT write support. - gpio-sysinfo updates - Allow env to be appended from dtb
generated by cgit (git 2.34.1) at 2025-09-04 09:03:07 +0000