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| * | | | clk: rockchip: rk3399: Set 400MHz ddr clockJagan Teki2019-07-211-0/+4
| * | | | clk: rockchip: rk3399: Set 50MHz ddr clockJagan Teki2019-07-211-0/+4
| * | | | rockchip: dts: rk3399: Add u-boot, dm-pre-reloc for pmuJagan Teki2019-07-211-0/+4
| * | | | rockchip: rk3399: syscon: Add pmu supportJagan Teki2019-07-211-0/+8
| * | | | arm: include: rockchip: Add rk3399 pmu fileJagan Teki2019-07-211-0/+72
| * | | | ram: rk3399: Add LPPDR4 mr detectionJagan Teki2019-07-211-0/+226
| * | | | ram: rk3399: Handle data training via opsJagan Teki2019-07-211-10/+33
| * | | | ram: rk3399: Simplify data training first argumentJagan Teki2019-07-211-5/+4
| * | | | ram: rk3399: Update lpddr4 vref_mode_acJagan Teki2019-07-201-1/+2
| * | | | ram: rk3399: Update lpddr4 mode_sel based on io settingsJagan Teki2019-07-201-2/+5
| * | | | ram: rk3399: Update lpddr4 vref based on io settingsJagan Teki2019-07-201-5/+14
| * | | | ram: rk3399: Get lpddr4 tsel_rd_en from io settingsJagan Teki2019-07-201-2/+6
| * | | | ram: rk3399: Configure soc odt supportJagan Teki2019-07-201-1/+48
| * | | | ram: rk3399: Add tsel control clock driveJagan Teki2019-07-201-2/+14
| * | | | ram: sdram: Configure lpddr4 tsel rd, wr based on IO settingsJagan Teki2019-07-201-6/+36
| * | | | ram: rk3399: Add IO settingsJagan Teki2019-07-201-0/+104
| * | | | ram: rk3399: Don't disable dfi dram clk for lpddr4, rank 1Jagan Teki2019-07-201-2/+12
| * | | | ram: rk3399: Configure tsel write ca for lpddr4Jagan Teki2019-07-201-3/+12
| * | | | ram: rk3399: Map chipselect for lpddr4Jagan Teki2019-07-201-0/+10
| * | | | ram: rk3399: Configure PHY RX_CM_INPUT for lpddr4Jagan Teki2019-07-201-0/+22
| * | | | ram: rk3399: Configure SLEWP_EN, SLEWN_EN for lpddr4Jagan Teki2019-07-201-0/+21
| * | | | ram: rk3399: Configure BOOSTP_EN, BOOSTN_EN for lpddr4Jagan Teki2019-07-201-0/+24
| * | | | ram: rk3399: Configure PHY_898, PHY_919 for lpddr4Jagan Teki2019-07-201-0/+5
| * | | | ram: rk3399: Avoid two channel ZQ Cal Start at the same timeJagan Teki2019-07-201-0/+14
| * | | | ram: rk3399: Don't wait for PLL lock in lpddr4Jagan Teki2019-07-201-10/+16
| * | | | ram: rk3399: Move mode_sel assignmentJagan Teki2019-07-201-9/+3
| * | | | ram: rk3399: Add lpddr4 rank mask for wdql trainingJagan Teki2019-07-201-1/+4
| * | | | ram: rk3399: Add lpddr4 rank mask for ca trainingJagan Teki2019-07-201-1/+4
| * | | | ram: rockchip: Kconfig: Add RK3399 LPDDR4 entryJagan Teki2019-07-201-0/+7
| * | | | ram: rk3399: Configure phy IO in ds odtJagan Teki2019-07-201-165/+162
| * | | | ram: rk3399: Add DdrModeJagan Teki2019-07-202-2/+17
| * | | | ram: rk3399: Add ddrtimingC0Jagan Teki2019-07-202-2/+12
| * | | | ram: rk3399: Add ddr version enc macroJagan Teki2019-07-202-0/+3
| * | | | ram: rk3399: Introduce sys_reg3 for more capacity infoJagan Teki2019-07-202-6/+24
| * | | | ram: rk3399: Rename sys_reg with sys_reg2Jagan Teki2019-07-201-13/+13
| * | | | ram: rk3399: Simply existing dram enc macroJagan Teki2019-07-202-19/+27
| * | | | ram: rk3399: Enable sdram debug functionsJagan Teki2019-07-201-0/+5
| * | | | ram: rk3399: Add rank detection supportJagan Teki2019-07-201-22/+100
| * | | | ram: rk3399: Compute stride for 1 channel aJagan Teki2019-07-191-0/+4
| * | | | ram: rk3399: Compute stride for 2 channelsJagan Teki2019-07-191-1/+70
| * | | | ram: rk3399: debug: Add sdram_print_strideJagan Teki2019-07-192-0/+34
| * | | | ram: rockchip: debug: Get the cs capacityJagan Teki2019-07-191-1/+45
| * | | | ram: rockchip: debug: Add sdram_print_ddr_infoJagan Teki2019-07-192-0/+47
| * | | | ram: rockchip: Add debug sdram driverJagan Teki2019-07-194-0/+53
| * | | | debug_uart: Add printdecJagan Teki2019-07-191-0/+19
| * | | | ram: rockchip: Add initial KconfigJagan Teki2019-07-193-1/+19
| * | | | ram: rk3399: Add pctl start supportJagan Teki2019-07-191-20/+55
| * | | | ram: rk3399: Move pwrup_srefresh_exit to dram_infoJagan Teki2019-07-191-6/+7
| * | | | ram: rk3399: Add phy pctrl reset supportJagan Teki2019-07-191-0/+29
| * | | | ram: rk3399: Use rank mask in wdql data trainingJagan Teki2019-07-191-1/+7
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