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* mips: octeon: cpu.c: Add table for selective swappingStefan Roese2020-10-071-0/+21
| | | | | | | | | | Import octeon_should_swizzle_table[] which is needed for the area specific swapping. It will be used by the platform specific mangle-port.h header. Imported from Linux v5.7. Signed-off-by: Stefan Roese <sr@denx.de>
* usb: xhci: octeon: Add DWC3 glue layer for OcteonStefan Roese2020-10-073-0/+403
| | | | | | | | | | This patch adds the glue layer for the MIPS Octeon SoCs. It's ported mainly from the Linux code. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Marek Vasut <marex@denx.de>
* usb: xhci: xhci_bulk_tx: Don't "BUG" when comparing addressesStefan Roese2020-10-071-2/+0
| | | | | | | | | | | | | | Octeon uses mapped addresses for virtual and physical memory. It's not that easy to calculate the resulting addresses here. So let's remove this BUG_ON() completely, as it's not really helpful. Please also note, that BUG_ON() is not recommended any more in the Linux kernel. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Marek Vasut <marex@denx.de>
* usb: xhci: xhci-dwc3.c: Use dev_remap_addr() instead of dev_get_addr()Stefan Roese2020-10-071-1/+1
| | | | | | | | | | | On MIPS platforms, mapping of the base address is needed. This patch switches from dev_get_addr() to dev_remap_addr() to get the mapped base address of the xHCI controller. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Marek Vasut <marex@denx.de>
* mips: octeon: octeon_ebb7304: Add DDR4 supportStefan Roese2020-10-074-7/+479
| | | | | | | | | | | This patch adds the board specific configuration (struct) for the Octeon 3 EBB7304 EVK. This struct is ported from the 2013er Cavium / Marvell U-Boot repository. Also, the Octeon RAM driver is enabled in the board defconfig for its usage. Tested with one and two DIMMs on the EBB7304 EVK (8 & 16 GiB). Signed-off-by: Stefan Roese <sr@denx.de>
* mips: octeon: dram.c: Add RAM driver supportStefan Roese2020-10-071-8/+64
| | | | | | | | | This patch adds the initialization call for the Octeon RAM driver to the Octeon platforms code. So if enabled via Kconfig, the DDR driver will be called and the RAM will be configured and used. If the RAM driver is not enabled, the L2 cache is still used as RAM. Signed-off-by: Stefan Roese <sr@denx.de>
* ram: octeon: Add MIPS Octeon3 DDR4 support (part 3/3)Aaron Williams2020-10-075-0/+435
| | | | | | | | | | | | This Octeon 3 DDR driver is ported from the 2013 Cavium / Marvell U-Boot repository. It currently supports DDR4 on Octeon 3. It can be later extended to support also DDR3 and Octeon 2 platforms. Part 3 includes the DIMM SPD handling code and the Kconfig / Makefile integration. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
* ram: octeon: Add MIPS Octeon3 DDR4 support (part 2/3)Aaron Williams2020-10-071-0/+11030
| | | | | | | | | | | This Octeon 3 DDR driver is ported from the 2013 Cavium / Marvell U-Boot repository. It currently supports DDR4 on Octeon 3. It can be later extended to support also DDR3 and Octeon 2 platforms. Part 2 includes the very complex Octeon 3 DDR4 configuration Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
* ram: octeon: Add MIPS Octeon3 DDR4 support (part 1/3)Aaron Williams2020-10-071-0/+2728
| | | | | | | | | | | | This Octeon 3 DDR driver is ported from the 2013 Cavium / Marvell U-Boot repository. It currently supports DDR4 on Octeon 3. It can be later extended to support also DDR3 and Octeon 2 platforms. Part 1 adds the base U-Boot RAM driver, which will be instantiated by the DT based probing. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
* mips: octeon: Add octeon_ddr.h headerAaron Williams2020-10-071-0/+982
| | | | | | | | This header will be used by the DDR driver (lmc). Its ported from the 2013 Cavium / Marvell U-Boot repository. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
* mips: octeon Add cvmx/cvmx-lmcx-defs.h headerAaron Williams2020-10-071-0/+4574
| | | | | | | | This header will be used by the DDR driver (lmc). Its ported from the 2013 Cavium / Marvell U-Boot repository. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
* mips: octeon: Add octeon-model.h headerAaron Williams2020-10-071-0/+313
| | | | | | | | This header is used by the upcoming DDR driver and potentially by other drivers ported from the 2013 Cavium / Marvell U-Boot repository. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
* mips: octeon: dts: mrvl, cn73xx.dtsi: Add memory controller DT nodeStefan Roese2020-10-071-0/+17
| | | | | | | | This patch adds the memory controller (LMC) DT node to the Octeon 3 dtsi file. It also adds the L2C DT node, as this is referenced by the DDR driver. Signed-off-by: Stefan Roese <sr@denx.de>
* Merge tag 'efi-2021-01-rc1' of ↵Tom Rini2020-10-069-52/+122
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-efi Pull request for UEFI sub-system for efi-2021-01-rc1 The following bugs in the UEFI system are resolved: * illegal free in EFI_LOAD_FILE2_PROTOCOL implementation * incorrect documentation of EFI_LOAD_FILE2_PROTOCOL implementation * output of CRC32 as decimal instead hexadecimal in unit test * use EfiReservedMemoryType for no-map reserved memory * avoid unnecessary resets in UEFI unit tests * call EFI bootmgr even without having /EFI/boot
| * efi_loader: consider no-map property of reserved memoryHeinrich Schuchardt2020-10-061-6/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The device tree may contain a /reserved-memory node. The no-map property of the sub-nodes signals if the memory may be accessed by the UEFI payload or not. In the EBBR specification (https://github.com/arm-software/ebbr) the modeling of the reserved memory has been clarified. If a reserved memory node in the device tree has the no-map property map, create a EfiReservedMemoryType memory map entry else use EfiBootServicesData. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
| * efi_loader: QEMU CONFIG_EFI_GRUB_ARM32_WORKAROUND=nHeinrich Schuchardt2020-10-062-1/+1
| | | | | | | | | | | | | | | | | | | | CONFIG_EFI_GRUB_ARM32 is only needed for architectures with caches that are not managed via CP15 (or for some outdated buggy versions of GRUB). It makes more sense to disable the setting per architecture than per defconfig. Move QEMU's CONFIG_EFI_GRUB_ARM32_WORKAROUND=n from defconfig to Kconfig. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
| * efi: Fix typo in documentationSean Anderson2020-10-061-1/+1
| | | | | | | | | | | | | | There is an extra space. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
| * distro_bootcmd: call EFI bootmgr even without having /EFI/bootMichael Walle2020-10-061-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, the EFI bootmgr is only called if there is a EFI binary inside the path for removable media is found, i.e. /EFI/boot/. This doesn't make sense. It is the duty of the bootmgr to find out the path and name of the EFI binary to boot. It should be called even if there is no /EFI/boot directory. Thus, call the bootmgr before we try to boot the EFI binary inside the removable media path. Also remove the ${fdtcontroladdr} parameter because the fallback is handled in cmd/bootefi.c and that already takes care of correct settings if the board has ACPI and thus no device tree at all. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
| * efi_selftest: avoid unnecessary resetHeinrich Schuchardt2020-10-061-0/+31
| | | | | | | | | | | | | | When we do not execute a test requiring ExitBootServices do not reset the system after testing. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
| * efi_selftest: print CRC32 of initrd as hexadecimalHeinrich Schuchardt2020-10-061-1/+1
| | | | | | | | | | | | | | | | Print the CRC32 loaded via the EFI_LOAD_FILE2_PROTOCOL as a hexadecimal number. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
| * efi_selftest: enable printing hexadecimal numbersHeinrich Schuchardt2020-10-061-13/+22
| | | | | | | | | | | | Add code to use %x in efi_st_print(). Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
| * efi_loader: illegal free in EFI_LOAD_FILE2_PROTOCOLHeinrich Schuchardt2020-10-061-8/+9
| | | | | | | | | | | | | | | | strsep() changes the address that its first argument points to. We cannot use the changed address as argument of free(). Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
| * efi_loader: description EFI_LOAD_FILE2_PROTOCOLHeinrich Schuchardt2020-10-061-19/+23
| | | | | | | | | | | | | | | | | | U-Boot offers a EFI_LOAD_FILE2_PROTOCOL which the Linux EFI stub can use to load an initial RAM disk. Update the function comments of the implementation. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
* | Merge tag 'u-boot-amlogic-20201005' of ↵Tom Rini2020-10-0663-397/+2315
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic - generate unique mac address from SoC serial on S400 board - Add USB support for GXL and AXG SoCs - Update Gadget code to use the new GXL and AXG USB glue driver - Add a VIM3 board support to add dynamic PCIe enable in OS DT - Fix AXG pinmux with requesting GPIOs - Add missing GPIOA_18 for AXG pinctrl - Add Amlogic PWM driver
| * pwm: Add driver for Amlogic Meson PWM controllerNeil Armstrong2020-10-053-0/+536
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds the driver for the PWM controller found in the Amlogic SoCs. This PWM is only a set of Gates, Dividers and Counters: PWM output is achieved by calculating a clock that permits calculating two periods (low and high). The counter then has to be set to switch after N cycles for the first half period. The hardware has no "polarity" setting. This driver reverses the period cycles (the low length is inverted with the high length) for PWM_POLARITY_INVERSED. Disabling the PWM stops the output immediately (without waiting for the current period to complete first). Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
| * pinctrl: meson-axg: add missing GPIOA_18Neil Armstrong2020-10-051-0/+1
| | | | | | | | | | | | Add the missing GPIOA_18 from the missing EE gpio list. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
| * pinctrl: meson-axg-pmx: fix gpio requestNeil Armstrong2020-10-051-1/+4
| | | | | | | | | | | | | | | | The AXG pmx driver gpio request offset needs the pin base to have the correct pin number. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Mark Kettenis <kettenis@openbsd.org>
| * board: amlogic: vim3: add support for dynamic PCIe enableNeil Armstrong2020-10-056-0/+258
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The VIM3 on-board MCU can mux the PCIe/USB3.0 shared differential lines using a FUSB340TMX USB 3.1 SuperSpeed Data Switch between an USB3.0 Type A connector and a M.2 Key M slot. The PHY driving these differential lines is shared between the USB3.0 controller and the PCIe Controller, thus only a single controller can use it. This adds this dynamic switching right before booting Linux and the configuration steps in the boards documentation. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Kevin Hilman <khilman@baylibre.com> Tested-by: Kevin Hilman <khilman@baylibre.com> [narmstrong: fixed warning by replacing min() by min_t()]
| * configs: vim3: use the vim3 board supportNeil Armstrong2020-10-052-2/+2
| | | | | | | | | | | | | | | | | | Use the newly added VIM3 board support instead of the generic W400. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Kevin Hilman <khilman@baylibre.com> Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
| * board: amlogic: add a vim3 specific board supportNeil Armstrong2020-10-054-4/+35
| | | | | | | | | | | | | | | | | | | | The VIM3 will need a specific code to enable PCIe if enabled in the MCU, thus add a specific board support for VIM3 & VIM3L. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Kevin Hilman <khilman@baylibre.com> Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
| * ARM: dts: sync amlogic G12A/SM1 DT from Linux 5.9-rc1Neil Armstrong2020-10-057-24/+385
| | | | | | | | | | | | | | | | | | | | This imports the G12A & SM1 SoC and boards DT changes from the Linux commit 9123e3a74ec7 ("Linux 5.9-rc1"). Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Kevin Hilman <khilman@baylibre.com> Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
| * configs: s400: enable USBNeil Armstrong2020-10-051-0/+15
| | | | | | | | | | | | Enable USB Host & Gadget on the Amlogic S400 board. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
| * ARM: dts: meson-axg: add USB nodes for S400Neil Armstrong2020-10-052-0/+74
| | | | | | | | | | | | | | | | Add the correcly architectured USB Glue node for Meson AXG and the S400 board in -u-boot.dtsi until support in upstream Linux then backported. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
| * arm: meson-axg: add board_usb_init()/cleanup() for USB gadgetNeil Armstrong2020-10-051-0/+128
| | | | | | | | | | | | | | Add the board_usb_init()/cleanup() for USB gadget for AXG based on the code for the G12A architecture. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
| * phy: meson-gxl-usb: depend on Meson AXG aswellNeil Armstrong2020-10-051-1/+1
| | | | | | | | | | | | Enable build of meson-gxl-usb PHY for the AXG architecture aswell. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
| * phy: meson-gxl: remove invalid USB3 PHY driverNeil Armstrong2020-10-053-221/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | The registers which are managed by the meson-gxl-usb3 PHY driver are actually "USB control" registers (which are "glue" registers which manage OTG detection and routing of the OTG capable port between the DWC2 peripheral-only controller and the DWC3 host-only controller). Drop the meson-gxl-usb3 PHY driver now that the dwc3-meson-gxl-usb driver supports the USB control registers on GXL and GXM SoCs (these were previously managed by the meson-gxl-usb3 PHY driver). Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
| * ARM: mach-meson: use new DWC3 glue for GXL & GXMNeil Armstrong2020-10-058-62/+79
| | | | | | | | | | | | | | Use the new Amlogic GXL/GXM USB Glue instead of the set of USB3 PHY and Simple DWC3 wrapper. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
| * usb: dwc3: add Amlogic GXL & GXL DWC3 GlueNeil Armstrong2020-10-054-0/+436
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The USB support was initialy done with a set of PHYs and dwc3-of-simple because the architecture of the USB complex was not understood correctly at the time (and proper documentation was missing...). But with the G12A family, the USB complex was correctly understood and implemented correctly. This adds a proper driver for the glue, based on the G12A one, but with enough changes to require a different driver in U-Boot. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
| * ARM: dts: sync amlogic AXG/GXL/GXM DT from Linux 5.8-rc1Neil Armstrong2020-10-0522-82/+358
| | | | | | | | | | | | | | | | | | This imports the AXG, GXL & GXM SoC and boards DT changes from the Linux commit b3a9e3b9622a ("Linux 5.8-rc1"). This change also removes GXL & GXM u-boot.dtsi hacks for USB gadget. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
| * board: s400: generate unique mac address from SoC serialNeil Armstrong2020-10-051-0/+2
| | | | | | | | | | | | Enable unique mac address generation from SoC serial on S400 board. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* | configs: Resync with savedefconfigTom Rini2020-10-0581-446/+290
| | | | | | | | | | | | Rsync all defconfig files using moveconfig.py Signed-off-by: Tom Rini <trini@konsulko.com>
* | Merge branch 'next'Tom Rini2020-10-05864-11226/+47331
|\ \ | |/ |/| | | | | | | | | Bring in the assorted changes that have been staged in the 'next' branch prior to release. Signed-off-by: Tom Rini <trini@konsulko.com>
| * Merge tag 'u-boot-atmel-2021.01-a' of ↵Tom Rini2020-10-0546-928/+6713
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-atmel into next First set of u-boot-atmel features for 2021.01 cycle: This feature set includes a new CPU driver for at91 family, new driver for PIT64B hardware timer, support for new at91 family SoC named sama7g5 which adds: clock support, including conversion of the clock tree to CCF; SoC support in mach-at91, pinctrl and mmc drivers update. The feature set also includes updates for mmc driver and some other minor fixes and features regarding building without the old Atmel PIT and the possibility to read a secondary MAC address from a second i2c EEPROM.
| | * cpu: at91: add driver for CPUClaudiu Beznea2020-10-053-0/+125
| | | | | | | | | | | | | | | | | | Add basic CPU driver use to retrieve information about CPU itself. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
| | * MAINTAINERS: add Microchip PIT64B timerClaudiu Beznea2020-09-281-0/+1
| | | | | | | | | | | | | | | | | | Add Microchip PIT64B timer. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
| | * timer: mchp-pit64b: add support for pit64bClaudiu Beznea2020-09-283-0/+117
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for Microchip PIT64B timer. The timer is 64 bit length and is used as a free running counter (in continuous mode with highest values for period registers). The clock feeding the timer would be no more than 12.5MHz. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
| | * mmc: atmel-sdhci: use mmc_of_parse to get the DT propertiesEugen Hristev2020-09-251-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | Call mmc_of_parse at probe time to fetch all the host properties from the DT. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
| | * mmc: atmel-sdhci: enable the required generic clockEugen Hristev2020-09-251-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | The second clock of the IP block (the generic clock), must be explicitly enabled. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> Reviewed-by: Peng Fan <pengfan@nxp.com>
| | * mmc: atmel-sdhci: do not check clk_set_rate return valueEugen Hristev2020-09-251-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | clk_set_rate will return rate in case of success and zero in case of error, however it can also return -ev, but it's an ulong function. To avoid any issues, disregard the return value of this call. In case this call actually fails, nothing much we can do anyway, but we can at least try with the previous values (or DT assigned-clocks) Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
| | * mmc: atmel-sdhci: add sama7g5-sdhci compatibility stringEugen Hristev2020-09-251-0/+1
| | | | | | | | | | | | | | | | | | | | | Add new compatibility string for matching sama7g5 product. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
generated by cgit (git 2.34.1) at 2025-05-21 06:00:13 +0000