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| | * | mx28evk: Add a target for SPI NOR bootFabio Estevam2014-06-171-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Introduce 'mx28evk_spi' target which will store the environment variables into SPI NOR, which is useful when booting from SPI NOR. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| | * | mx28evk: Fix warning when CONFIG_ENV_IS_IN_SPI_FLASH is selectedFabio Estevam2014-06-171-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When building a target with CONFIG_ENV_IS_IN_SPI_FLASH the following warning is seen: include/configs/mx28evk.h:73:0: warning: "CONFIG_ENV_SIZE" redefined [enabled by default] Protect the definition of CONFIG_ENV_SIZE to avoid the warning. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| | * | embestmx6boards: Fix the dtb file name for riotboardFabio Estevam2014-06-171-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The name of the dtb file used in the kernel is 'imx6dl-riotboard.dtb', so fix it accordingly. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Tested-by: Iain Paton <ipaton0@gmail.com>
| | * | embestmx6boards: Fix CONFIG_CONSOLE_DEVFabio Estevam2014-06-171-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | mars and riot boards use UART2 as console, so CONFIG_CONSOLE_DEV should point to 'ttymxc1' instead. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Tested-by: Iain Paton <ipaton0@gmail.com>
| | * | mx6: drop ARM errata 742230Shawn Guo2014-06-171-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit e9fd66defd7e (ARM: mx6: define CONFIG_ARM_ERRATA_742230) enables errata 742230 for imx6, because it helps remove one reboot issue. However, this errata does not really apply on imx6, because Cortex-A9 on imx6 is r2p10 while the errata only applies to revisions r1p0..r2p2. At a later time, commit f71cbfe3ca5d (ARM: Add workaround for Cortex-A9 errata 794072) adds support of errata 794072, which applies to all Cortex-A9 revisions. As the workaround for both errata are exactly same, it makes a lot more sense to select 794072 instead of 742230 for imx6. Since we already enable 794072 for imx6, it's time to drop errata 742230 to avoid confusion. Signed-off-by: Shawn Guo <shawn.guo@freescale.com> Acked-by: Nitin Garg <nitin.garg@freescale.com>
| | * | arm: mx5: Enable CONFIG_SYS_GENERIC_BOARD on M53EVKMarek Vasut2014-06-171-0/+1
| | | | | | | | | | | | | | | | Signed-off-by: Marek Vasut <marex@denx.de>
| | * | mx6: Fix definition of IOMUXC_GPR12_DEVICE_TYPE_RCFabio Estevam2014-06-171-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | mx6 reference manual incorrectly states that the DEVICE_TYPE field of IOMUXC_GPR12 register should be configured as '0010' for setting the PCI controller in RC mode. The correct value should be '0100' instead. This also aligns with the same value used in the mx6 pci kernel driver. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
| | * | MX25: fix build due to missing sys_proto.hStefano Babic2014-06-061-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | THe mx25 arch does not have a sys_proto.h file. Instead of creating a dummy file, the file is not included for this SOC. Signed-off-by: Stefano Babic <sbabic@denx.de>
| | * | mx25pdk: Add generic board supportFabio Estevam2014-06-061-0/+2
| | | | | | | | | | | | | | | | Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| | * | imx: sata: return failure if not IMX6Q/IMX6DTim Harvey2014-06-061-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The IMX6QUAD/DUAL have SATA, but the IMX6SOLO/DL do not. Return instead of configuring the SATA clock and GPR13 registers. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
| | * | dwc_ahsata: return failure for MX6 if not IMX6Q/IMX6DTim Harvey2014-06-061-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The IMX6QUAD/DUAL have SATA, but the IMX6SOLO/DL do not. Return failure instead of attempting a memory access that results in a data abort and reset. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
| | * | imx: ventana: switch to SPLTim Harvey2014-06-067-56/+498
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Switch to an SPL image. The SPL for Ventana does the following: - setup i2c and read the factory programmed EEPROM to obtain DRAM config and model for board-specific calibration data - configure DRAM per CPU/size/layout/devices/calibration - load u-boot.img from NAND and jump to it This allows for a single SPL+u-boot.img to replace the previous multiple boa configurations. Cc: Stefan Roese <sr@denx.de> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Andy Ng <andreas2025@gmail.com> Cc: Eric Nelson <eric.nelson@boundarydevices.com> Cc: Tapani Utriainen <tapani@technexion.com> Cc: Tom Rini <trini@ti.com> Signed-off-by: Tim Harvey <tharvey@gateworks.com>
| | * | imx: ventana: auto-configure for IMX6Q vs IMX6DLTim Harvey2014-06-061-186/+312
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | use the new iomux function and a macros to create a multi-dimensional array of iomux values without duplicating the defintions. Cc: Stefan Roese <sr@denx.de> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Andy Ng <andreas2025@gmail.com> Cc: Eric Nelson <eric.nelson@boundarydevices.com> Cc: Tapani Utriainen <tapani@technexion.com> Cc: Tom Rini <trini@ti.com> Signed-off-by: Tim Harvey <tharvey@gateworks.com>
| | * | imx: ventana: split read_eeprom into standalone fileTim Harvey2014-06-064-89/+102
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Split the read_eeprom function out so that it can be shared (ie with SPL) Cc: Stefan Roese <sr@denx.de> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Andy Ng <andreas2025@gmail.com> Cc: Eric Nelson <eric.nelson@boundarydevices.com> Cc: Tapani Utriainen <tapani@technexion.com> Cc: Tom Rini <trini@ti.com> Signed-off-by: Tim Harvey <tharvey@gateworks.com>
| | * | imx: iomux: add macros to setup iomux for multiple SoC typesTim Harvey2014-06-062-2/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Allow imx_iomux_v3_setup_multiple_pads to take a multi-cpu pad_list and add macros for declaring the pad_list that take into account the SoC types supported using CONFIG_MX6QDL (supports both the MX6Q and MX6DL iomux). Cc: Stefan Roese <sr@denx.de> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Andy Ng <andreas2025@gmail.com> Cc: Eric Nelson <eric.nelson@boundarydevices.com> Cc: Tapani Utriainen <tapani@technexion.com> Cc: Tom Rini <trini@ti.com> Signed-off-by: Tim Harvey <tharvey@gateworks.com>
| | * | mx6: add mmdc configuration for MX6Q/MX6DLTim Harvey2014-06-063-0/+563
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - add function for configuring iomux based on board-specific regs - add function for configuring mmdc based on board-specific and chip-specific data Cc: Stefan Roese <sr@denx.de> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Andy Ng <andreas2025@gmail.com> Cc: Eric Nelson <eric.nelson@boundarydevices.com> Cc: Tapani Utriainen <tapani@technexion.com> Cc: Tom Rini <trini@ti.com> Signed-off-by: Tim Harvey <tharvey@gateworks.com>
| | * | mx6: add structs for mmdc and ddr iomux registersTim Harvey2014-06-061-0/+159
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add memory-mapped structures for MMDC iomux and configuration. Note that whi the MMDC configuration registers are common between the IMX6DQ (IMX6DUAL/IMX6QUAD) and IMX6SDL (IMX6SOLO/IMX6DUALLITE) types the iomux registers differ. This requires two sets of structures. Add structures to describe DDR3 device information, system information (memory layout, etc), and MMDC calibration registers that can be used to configure the MMDC dynamically. We define these structures for SPL builds instead of including mx6q-ddr.h an mx6dl-ddr.h which use the same namespace and are only useful for imximage cf files. Cc: Stefan Roese <sr@denx.de> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Andy Ng <andreas2025@gmail.com> Cc: Eric Nelson <eric.nelson@boundarydevices.com> Cc: Tapani Utriainen <tapani@technexion.com> Cc: Tom Rini <trini@ti.com> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Acked-by: Nikita Kiryanov <nikita@compulab.co.il>
| | * | imx: add comments and remove unused struct fieldsTim Harvey2014-06-061-9/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add comment block for the imx_ddr_size function and remove the extra unused fields from struct esd_mmdc_regs which are also not common between IMX53 and IMX6. Cc: Stefan Roese <sr@denx.de> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Andy Ng <andreas2025@gmail.com> Cc: Eric Nelson <eric.nelson@boundarydevices.com> Cc: Tapani Utriainen <tapani@technexion.com> Cc: Tom Rini <trini@ti.com> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Acked-by: Stefano Babic <sbabic@denx.de> Acked-by: Nikita Kiryanov <nikita@compulab.co.il>
| | * | mx6: add boot device support for SPLTim Harvey2014-06-062-0/+82
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a common spl.c file to support boot device functions needed for SPL such as detecting the boot device. Cc: Stefan Roese <sr@denx.de> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Andy Ng <andreas2025@gmail.com> Cc: Eric Nelson <eric.nelson@boundarydevices.com> Cc: Tapani Utriainen <tapani@technexion.com> Cc: Tom Rini <trini@ti.com> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Acked-by: Nikita Kiryanov <nikita@compulab.co.il>
| | * | mx6: add common SPL configurationTim Harvey2014-06-061-0/+71
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a common header which can hopefully be shared amon imx6 SPL users Cc: Stefan Roese <sr@denx.de> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Andy Ng <andreas2025@gmail.com> Cc: Eric Nelson <eric.nelson@boundarydevices.com> Cc: Tapani Utriainen <tapani@technexion.com> Cc: Tom Rini <trini@ti.com> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Acked-by: Stefano Babic <sbabic@denx.de> Acked-by: Nikita Kiryanov <nikita@compulab.co.il>
| | * | spl: nand: add support for mxs nandTim Harvey2014-06-062-0/+232
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This utilizes existing mxs_nand support layer to provide a method to load an image off nand for SPL. The flash device will be detected in order to support multiple flash devices instead of having layout hard coded at build time. Cc: Stefan Roese <sr@denx.de> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Andy Ng <andreas2025@gmail.com> Cc: Eric Nelson <eric.nelson@boundarydevices.com> Cc: Tapani Utriainen <tapani@technexion.com> Cc: Tom Rini <trini@ti.com> Cc: Scott Wood <scottwood@freescale.com> Signed-off-by: Tim Harvey <tharvey@gateworks.com>
| | * | spl: consolidate arch/arm/include/asm/arch-*/spl.hMasahiro Yamada2014-06-0611-136/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | arch/arm/include/asm/spl.h requires all SoCs to have arch/arm/include/asm/arch-*/spl.h. But many of them just define BOOT_DEVICE_* macros. Those macros are used in the "switch (boot_device) { ... }" statement in common/spl/spl.c. So they should not be archtecture specific, but be described as a simpile enumeration. This commit merges most of arch/arm/include/asm/arch-*/spl.h into arch/arm/include/asm/spl.h. With a little more effort, arch-zynq/spl.h and arch-socfpga/spl.h will be merged, while I am not sure about OMAP and Exynos. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Tom Rini <trini@ti.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Andreas Bießmann <andreas.devel@googlemail.com> Cc: Stephen Warren <swarren@nvidia.com> Cc: Tom Warren <twarren@nvidia.com> CC: Stefano Babic <sbabic@denx.de> CC: Minkyu Kang <mk7.kang@samsung.com> Cc: Dinh Nguyen <dinguyen@altera.com> Acked-by: Andreas Bießmann <andreas.devel@googlemail.com> Acked-by: Michal Simek <monstr@monstr.eu> Acked-by: Stefano Babic <sbabic@denx.de> Acked-by: Stephen Warren <swarren@nvidia.com> Acked-by: Tim Harvey <tharvey@gateworks.com> Tested-by: Bo Shen <voice.shen@atmel.com> [on sama5d3xek board for at91 part] Acked-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stefano Babic <sbabic@denx.de> [applying Tim's i.MX6 patches] Acked-by: Tom Rini <trini@ti.com>
| | * | serial_mxc: disable new features of autobaud detectionEric Nelson2014-05-281-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Bit 7 of UCR3 is described in the i.MX3x/i.MX5x/i.MX6x reference manuals as follows: Autobaud Detection Not Improved-. Disables new features of autobaud detection (See Baud Rate Automatic Detection Protocol, for more details). 0 Autobaud detection new features selected 1 Keep old autobaud detection mechanism On at least i.MX6DQ, i.MX6DLS and i.MX53, the "new features" occasionally cause the receiver to get out of sync and continuously produce received characters of '\xff'. This patch disables the "new feature" on all boards, since there's no support for auto-baud in U-Boot on any of them. More details are available in this post on i.MX Community: https://community.freescale.com/message/403254 Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com> Tested-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
| | * | mx6sabred: Add PFUZE100 PMIC supportFabio Estevam2014-05-283-0/+100
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | mx6sabresd boards have a PFUZE100 PMIC connected to I2C2 bus. Add support for it Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| | * | mx6sabreauto: Add the mx6dual-lite variantFabio Estevam2014-05-283-0/+135
| | | | | | | | | | | | | | | | | | | | | | | | Tested by booting a mainline kernel via TFTP. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | | Merge branch 'u-boot-sh/rmobile' into 'u-boot-arm/master'Albert ARIBAUD2014-06-301-2/+0
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| | * | | arm: rmobile: lager: Remove NOR-Flash support from boards.cfgNobuhiro Iwamatsu2014-06-111-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Lager board has NOR-Flash function. But this is not used basically. SPI-ROM is used instead. NOR-Flash support code has been removed, but this remains in the boards.cfg. This commit removes config of NOR-Flash from boards.cfg. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| | * | | arm: rmobile: koelsch: Remove NOR-Flash support from boards.cfgNobuhiro Iwamatsu2014-06-111-1/+0
| | | |/ | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Koelsch board has NOR-Flash function. But this is not used basically. SPI-ROM is used instead. NOR-Flash support code has been removed, but this remains in the boards.cfg. This commit removes config of NOR-Flash from boards.cfg. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | | Merge branch 'u-boot-microblaze/zynq' into 'u-boot-arm/master'Albert ARIBAUD2014-06-251-0/+1
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| | * | | arm: zynq: fix a bug in Zynq linker scriptMasahiro Yamada2014-06-171-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 41623c91 moved exception handlers to ".vectores" section but it missed to adjust Zynq linker script. Zynq boards hang up after relocation because "_start" symbol does not point to the correct address and gd->relocaddr gets insane. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Cc: Michal Simek <monstr@monstr.eu> Tested-by: Michal Simek <monstr@monstr.eu> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | | Merge branch 'u-boot/master' into 'u-boot-arm/master'Albert ARIBAUD2014-06-25385-15624/+8705
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| * \ \ \ \ Merge branch 'u-boot-atmel/master' into 'u-boot-arm/master'Albert ARIBAUD2014-06-248-45/+110
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| | * | | | | arm: ethernut5: convert to generic boardTim Schendekehl2014-06-141-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable CONFIG_SYS_GENERIC_BOARD for the Ethernut 5 board. Signed-off-by: Tim Schendekehl <tim.schendekehl@egnite.de> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
| | * | | | | ARMv7: at91: enable ICache and DCache.Wu, Josh2014-06-141-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For at91 armv7 SoC (SAMA5D3x), only LCD and macb used DMA. Now as the lcd and macb driver already support dcache. So we can enable dcache now. Also we can enable icache without any problem. Signed-off-by: Josh Wu <josh.wu@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
| | * | | | | video: atmel_hlcdfb: enable dcache supportWu, Josh2014-06-141-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To support dcache, we need flush DMA descriptor buffer before enable lcd DMA. Also we need call lcd_set_flush_dcache(1) to make lcd driver flush the lcd buffer if there is any change. Cc: Anatolij Gustschin <agust@denx.de> Signed-off-by: Josh Wu <josh.wu@atmel.com> Acked-by: Anatolij Gustschin <agust@denx.de> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
| | * | | | | net: macb: enable dcache in macbWu, Josh2014-06-141-4/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add to code to flush the dcache after we writing in DMA buffer. Also we need invalidate the dcache before we check the status in the DMA buffer. Tested in SAMA5D3x-EK with gmac0. Tftp download speed shows in below: Disable DCache: 1.1 MiB/s Enable DCache: 1.6 MiB/s Increase speed with about 40%. The code should have no impact with the boards which are not enable_dcache(). Tested in AT91SAM9M10G45EK. Signed-off-by: Josh Wu <josh.wu@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
| | * | | | | macb: make checkpatch cleanAndreas Bießmann2014-06-141-27/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This also renames the CONFIG_SYS_MACB_xx defines. They are used just local and therefore don't need the CONFIG_SYS_ prefix. Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com> Reviewed-by: Josh Wu <josh.wu@atmel.com>
| | * | | | | avr32: migrate cache functionsAndreas Bießmann2014-06-144-16/+16
| | | |_|/ / | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Unfortunately the avr32 cache implementation has another API than the one described in common.h. Migrate the flush/invalidate dcache functions to the common API to be usable in device drivers. Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com> CC: Josh Wu <josh.wu@atmel.com>
| * / | | | arm: bcm281xx: Add CONFIG_SYS_GENERIC_BOARDSteve Rae2014-06-101-0/+1
| |/ / / / | | | | | | | | | | | | | | | | | | | | | | | | | convert to generic board Signed-off-by: Steve Rae <srae@broadcom.com>
| * | | | arm: fix a double-definition error of _start symbolMasahiro Yamada2014-06-091-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The symbol "_start" is defined twice in arch/arm/lib/vectors.S: around line 48 and line 54. If CONFIG_SYS_DV_NOR_BOOT_CFG is defined (as on calimain board), build fails: arch/arm/lib/vectors.S: Assembler messages: arch/arm/lib/vectors.S:54: Error: symbol `_start' is already defined make[1]: *** [arch/arm/lib/vectors.o] Error 1 make: *** [arch/arm/lib] Error 2 Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
| * | | | arm64: zero cntvoff_el2Mark Rutland2014-06-091-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently cntvoff_el2 is initialised with an arbitrary bag of bits derived from the initial value of cnthctl_el2 on the current CPU. This is somewhat odd and problematic as some of these bits are UNKNOWN at reset and may differ across CPUs (which may cause an OS at EL1 to observe time going backwards across CPUs). This patch instead initialises cntvoff_el2 with xzr, giving the register a consistent value of zero on all CPUs. Signed-off-by: Mark Rutland <mark.rutland@arm.com> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Cc: Scott Wood <scottwood@freescale.com> Cc: David Feng <fenghua@phytium.com.cn> Cc: Tom Rini <trini@ti.com> Acked-by: David.Feng <fenghua@phytium.com.cn>
| * | | | arm: vf610: Add QSPI support for VF610TWRChao Fu2014-06-095-5/+68
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add QSPI support for VF610TWR, such as clock and iomux. Signed-off-by: Alison Wang <Huan.Wang@freescale.com> Signed-off-by: Chao Fu <b44548@freescale.com>
| * | | | arm: imx: Add two macros for VF610 in IOMUX_PAD structureAlison Wang2014-06-091-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add PAD_CTL_DSE_150ohm and PAD_CTL_PUS_22K_UP for VF610 in IOMUX_PAD structure. Signed-off-by: Alison Wang <Huan.Wang@freescale.com>
| * | | | arm: vf610: Add QSPI driver supportAlison Wang2014-06-093-0/+610
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add Freescale QSPI driver support for VF610. Signed-off-by: Alison Wang <Huan.Wang@freescale.com> Signed-off-by: Chao Fu <b44548@freescale.com>
* | | | | Prepare v2014.07-rc4Tom Rini2014-07-021-1/+1
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Tom Rini <trini@ti.com>
* | | | | usb: ci_udc: use var name ep/ci_ep consistentlyStephen Warren2014-07-021-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Almost all of ci_udc.c uses variable name "ep" for a struct usb_ep and "ci_ep" for a struct ci_ep. This is nice and consistent, and helps people know what type a variable is without searching for the declaration. handle_ep_complete() doesn't do this, so fix it to be consistent. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | | | | USB: gadget: atmel: zero out allocated requestsStephen Warren2014-07-021-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A UDC's alloc_request method should zero out the newly allocated request. Ensure the Atmel driver does so. This issue was found by code inspection, following the investigation of an intermittent issue with ci_udc, which was tracked down to failing to zero out allocated requests following some of my changes. All other UDC drivers already zero out requests in one way or another. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | | | | usb: ci_udc: don't memalign() struct ci_req allocationsStephen Warren2014-07-021-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | struct ci_req is a purely software structure, and needs no specific memory alignment. Hence, allocate it with calloc() rather than memalign(). The use of memalign() was left-over from when struct ci_req was going to hold the aligned bounce buffer, but this is now dynamically allocated. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | | | | usb: ci_udc: remove controller.items arrayStephen Warren2014-07-022-6/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There's no need to store an array of QTD pointers in the controller. Since the calculation is so simple, just have ci_get_qtd() perform it at run-time, rather than pre-calculating everything. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | | | | usb: ci_udc: fix items array size/stride calculationStephen Warren2014-07-021-15/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 2 QTDs are allocated for each EP. The current allocation scheme aligns the first QTD in each pair, but simply adds the struct size to calculate the second QTD's address. This will result in a non-cache-aligned addresss IF the system's ARCH_DMA_MINALIGN is not 32 bytes (i.e. the size of struct ept_queue_item). Similarly, the original ilist_ent_sz calculation aligned the value to ARCH_DMA_MINALIGN but didn't take the USB HW's 32-byte alignment requirement into account. This doesn't cause a practical issue unless ARCH_DMA_MINALIGN < 32 (which I suspect is quite unlikely), but we may as well fix the code to be explicit, so it's obviously completely correct. The new value of ILIST_ENT_SZ takes all alignment requirements into account, so we can simplify ci_{flush,invalidate}_qtd() by simply using that macro rather than calling roundup(). Similarly, the calculation of controller.items[i] can be simplified, since each QTD is evenly spaced at its individual alignment requirement, rather than each pair being aligned, and entries within the pair being spaced apart only by structure size. Signed-off-by: Stephen Warren <swarren@nvidia.com>
generated by cgit (git 2.34.1) at 2024-06-30 23:09:43 +0000