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* clk: add APIs to get (optional) clock by name without a deviceChunfeng Yun2020-01-162-0/+68
| | | | | | | | | | | | Sometimes we may need get (optional) clock without a device, that means use ofnode. e.g. when the phy node has subnode, and there is no device created for subnode, in this case, we need these new APIs to get subnode's clock. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
* clk: check valid clock by clk_valid()Chunfeng Yun2020-01-161-8/+8
| | | | | | | | | | Add valid check for clk->dev, it's useful when get optional clock even when the clk point is valid, but its dev will be NULL. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
* clk: fix error check for devm_clk_get_optional()Chunfeng Yun2020-01-161-1/+1
| | | | | | | | | If skip all return error number, it may skip some real error cases, so only skip the error when the clock is not provided in DTS Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
* clk: mediatek: mt7629: add support for ssusbsysChunfeng Yun2020-01-161-0/+42
| | | | | | | | | The SSUSB IP's clocks come from ssusbsys module on mt7629, so add its driver Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
* ARM: MediaTek: add basic support for MT8512 boardsmingming lee2020-01-168-0/+253
| | | | | | | | | | | This adds a general board file based on MT8512 SoCs from MediaTek. Apart from the generic parts (cpu) we add some low level init codes and initialize the early clocks. This commit is adding the basic boot support for the MT8512 eMMC board. Signed-off-by: mingming lee <mingming.lee@mediatek.com>
* mmc: mtk-sd: fix hang when data read quicklymingming lee2020-01-161-5/+1
| | | | | | | | | | | For CMD21 tuning data, the 128/64 bytes data may coming in very short time, before msdc_start_data(), the read data has already come, in this case, clear MSDC_INT will cause the interrupt disappear and lead to the thread hang. the solution is just clear all interrupts before command was sent. Signed-off-by: mingming lee <mingming.lee@mediatek.com>
* mmc: mtk-sd: add support for MediaTek MT8512/MT8110 SoCsmingming lee2020-01-161-33/+101
| | | | | | | | This patch adds mmc support for MediaTek MT8512/MT8110 SoCs. MT8512/MT8110 SoCs puts the tune register at top layer, so need add new code to support it. Signed-off-by: mingming lee <mingming.lee@mediatek.com>
* pinctrl: mediatek: add driver for MT8512mingming lee2020-01-163-0/+392
| | | | | | Add Pinctrl driver for MediaTek MT8512 SoC. Signed-off-by: mingming lee <mingming.lee@mediatek.com>
* clk: mediatek: add configurable pcw_chg_reg/ibits/fmin to mtk_pllmingming lee2020-01-162-8/+20
| | | | Add configurable pcw_chg_reg/ibits/fmin to mtk_pll to support mt8512
* clk: mediatek: add set_clr_upd mux type flowmingming lee2020-01-162-11/+55
| | | | | Add new set_clr_upd mux type and related operation to mtk common clock driver to support mt8512
* clk: mediatek: add driver support for MT8512mingming lee2020-01-163-0/+1071
| | | | | | | Add clock driver for MediaTek MT8512 SoC, include topckgen, apmixedsys and infracfg support. Signed-off-by: mingming lee <mingming.lee@mediatek.com>
* ARM: MediaTek: Add support for MediaTek MT8512 SoCmingming lee2020-01-166-0/+245
| | | | | | | Add support for MediaTek MT8512 SoC. This include the file that will initialize the SoC after boot and its device tree. Signed-off-by: mingming lee <mingming.lee@mediatek.com>
* MAINTAINERS: Fix mailSam Protsenko2020-01-161-1/+1
| | | | | | | Sam doesn't work for Linaro anymore, so Linaro mail is not valid. Change it to his home mail instead. Signed-off-by: Sam Protsenko <joe.skb7@gmail.com>
* cmd/blk_common: clarify no partition error messageAlexandre Besnard2020-01-161-1/+2
| | | | | | | | When no partition table is found, users should be warned so. Warning that no device is available in this case could be misleading, especially as it is the same error when no device is selected. Signed-off-by: Alexandre Besnard <alexandre.besnard@softathome.com>
* test/py: use valid device tree in test_fit.pyHeinrich Schuchardt2020-01-151-3/+6
| | | | | | | | The device tree compiler expects that a node with a unit-address has a reg property. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* Add dependencies for MALLOC_F and OF_LIBFDTSean Anderson2020-01-152-0/+6
| | | | | | | Some features implicitly depended on MALLOC_F and OF_LIBFDT and would fail at link-time if these features were not enabled. Signed-off-by: Sean Anderson <seanga2@gmail.com>
* Include missing headers for asm-generic/sections.hSean Anderson2020-01-151-0/+2
| | | | | | | asm-generic/sections.h references ulong but does not include linux/types.h Signed-off-by: Sean Anderson <seanga2@gmail.com>
* dma: Add stub of dma_memcpy and dma_get_deviceVignesh Raghavendra2020-01-151-0/+11
| | | | | | | | Add stub for dma_memcpy() and dma_get_device when CONFIG_DMA is disabled. This avoids ifdefs in driver code using DMA APIs Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* Kconfig: Rename CONFIG_SPL_DMA_SUPPORT to CONFIG_SPL_DMAVignesh Raghavendra2020-01-1527-27/+27
| | | | | | | | | Rename CONFIG_SPL_DMA_SUPPORT to CONFIG_SPL_DMA. This allows to use macros such as CONFIG_IS_ENABLED() that allow conditional compilation of code for SPL and U-Boot. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* Merge tag 'efi-2020-04-rc1-2' of ↵Tom Rini2020-01-157-11/+55
|\ | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-efi Pull request for UEFI sub-system for efi-2020-04-rc1-2 Bug fixes for the UEFI sub-system are provided: * imply VIDEO_ANSI for correct cursor positioning and colors * fix issues in the UEFI block device driver * add missing documentation
| * efi_loader: imply VIDEO_ANSIHeinrich Schuchardt2020-01-151-0/+1
| | | | | | | | | | | | | | | | | | UEFI programs like GRUB make change terminal colors which requires support for ANSI escape sequences. Let CONFIG_EFI_LOADER=y imply CONFIG_VIDEO_ANSI. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
| * efi_driver: debug output efi_uc_start, efi_uc_stopHeinrich Schuchardt2020-01-151-2/+2
| | | | | | | | | | | | | | Use the correct printf codes for the debug output in efi_uc_start() and efi_uc_stop(). Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
| * efi_driver: fix efi_uc_stop()Heinrich Schuchardt2020-01-152-5/+6
| | | | | | | | | | | | | | | | | | | | Use the correct protocol in efi_uc_stop() when detaching the driver from the controller. Change the block IO unit test for the block device driver to throw an error instead of a todo if teardown fails. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
| * efi_selftest: enable CONFIG_CMD_POWEROFFHeinrich Schuchardt2020-01-151-0/+1
| | | | | | | | | | | | | | | | | | | | For automating testing we should be able to power off the test system. The implementation of EFI_RESET_SHUTDOWN requires the do_poweroff() function which is only available if CONFIG_CMD_POWEROFF=y. Enable CONFIG_CMD_POWEROFF if PSCI reset is available. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
| * efi_loader: describe returning of controlHeinrich Schuchardt2020-01-151-4/+4
| | | | | | | | | | | | | | Provide a sober description of how control can be returned by a UEFI binary. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
| * efi_loader: document functions in efi_rng.cHeinrich Schuchardt2020-01-152-0/+41
| | | | | | | | | | | | Add the missing Sphinx documentation. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
* | Merge tag 'u-boot-imx-20200115' of ↵Tom Rini2020-01-1579-275/+4882
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-imx ----------------------------------- - imx8: add capricorn giedi deneb boards - imx6: fixed fow wandboard - imx7: DM_ETHER for pico-imx7d - fsl_esdhc_imx: add broken-cd property - New SOC: IMXRT10xx Travis: https://travis-ci.org/sbabic/u-boot-imx/builds/637126531
| * | imx: imxrt1050-evk: Add support for the NXP i.MXRT1050-EVKGiulio Benetti2020-01-1412-0/+555
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds board support for i.MXRT1050-EVK from NXP. This board is an evaluation kit provided by NXP for i.MXRT105x processor family. More information about this board can be found here: https://www.nxp.com/design/development-boards/i.mx-evaluation-and-development-boards/i.mx-rt1050-evaluation-kit:MIMXRT1050-EVK The initial supported/tested devices include: - Debug serial - SD Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
| * | imx: Add basic support for the NXP IMXRT10xx SoC familyGiulio Benetti2020-01-1411-3/+140
| | | | | | | | | | | | | | | | | | Add i.IMXRT family basic support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
| * | mmc: fsl_esdhc: add compatible for fsl, imxrt-usdhcGiulio Benetti2020-01-142-2/+3
| | | | | | | | | | | | | | | | | | | | | Add compatible "fsl,imxrt-usdhc" to make mmc working on i.MXRT platforms with CONFIG_DM_MMC=y. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
| * | mmc: fsl_esdhc: make if(CONFIG_IS_ENABLED(CLK)) an #if statementGiulio Benetti2020-01-141-19/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Not all architectures(i.e. i.MXRT) support mxc_get_clock() and use DM_CLK instead. So building could result in failure due to missing mxc_get_clock(). Make if(CONFIG_IS_ENABLED(CLK)) an #if statement. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
| * | ram: add SDRAM driver for i.MXRT SoCsGiulio Benetti2020-01-144-0/+549
| | | | | | | | | | | | | | | | | | Add SDRAM driver for i.MXRT SoCs. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
| * | serial_lpuart: add support for i.MXRTGiulio Benetti2020-01-142-5/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add i.MXRT compatible string and cpu type support to lpuart driver, to use little endian 32 bits configurations. Also according to RM, the Receive RX FIFO Enable (RXFE) field in LPUART FIFO register is bit 3, so this definition should change to 0x08 as done for i.MX8. It needs also to set baudrate the same way as i.MX8 does. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
| * | serial_lpuart: add clock enable if CONFIG_CLK is definedGiulio Benetti2020-01-141-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This driver assumes that lpuart clock is already enabled before probing but using DM only lpuart won't be automatically enabled so add clk_enable() when probing if CONFIG_CLK is defined. If clock is not found, because DM is not used, let's emit a warning and proceed, because serial clock could also be already enabled by non DM code. If clock is found but cna't be enabled then return with error. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
| * | ARM: dts: imxrt1050: add dtsi fileGiulio Benetti2020-01-142-0/+1139
| | | | | | | | | | | | | | | | | | Add dtsi file for i.MXRT1050. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
| * | gpio: mxc_gpio: add support for i.MXRT1050Giulio Benetti2020-01-141-3/+4
| | | | | | | | | | | | | | | | | | Add i.MXRT1050 support, there are 5 GPIO banks. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
| * | pinctrl: add i.MXRT driverGiulio Benetti2020-01-143-0/+55
| | | | | | | | | | | | | | | | | | Add i.MXRT pinctrl driver. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
| * | clk: imx: add i.IMXRT1050 clk driverGiulio Benetti2020-01-144-0/+375
| | | | | | | | | | | | | | | | | | Add i.MXRT1050 clk driver support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
| * | clk: imx: pfd: add set_rate()Giulio Benetti2020-01-141-0/+22
| | | | | | | | | | | | | | | | | | | | | Implement set_rate() for pfd. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
| * | clk: imx: pllv3: add support for PLLV3_AV typeGiulio Benetti2020-01-141-0/+76
| | | | | | | | | | | | | | | | | | Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
| * | clk: imx: pllv3: add PLLV3_SYS supportGiulio Benetti2020-01-141-0/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
| * | clk: imx: pllv3: add set_rate() supportGiulio Benetti2020-01-141-0/+27
| | | | | | | | | | | | | | | | | | | | | Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
| * | clk: imx: pllv3: add disable() supportGiulio Benetti2020-01-141-0/+16
| | | | | | | | | | | | | | | | | | | | | Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
| * | clk: imx: pllv3: add enable() supportGiulio Benetti2020-01-141-0/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
| * | clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USBGiulio Benetti2020-01-141-0/+2
| | | | | | | | | | | | | | | | | | | | | div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
| * | clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocksGiulio Benetti2020-01-141-5/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
| * | armv7m: cache: add mmu_set_region_dcache_behaviour() stub for compatibilityGiulio Benetti2020-01-141-0/+6
| | | | | | | | | | | | | | | | | | | | | Since some driver requires this function add it as an empty stub when DCACHE is OFF. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
| * | spl: fix entry_point equal to load_addrGiulio Benetti2020-01-141-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At the moment entry_point is set to image_get_load(header) that sets it to "load address" instead of "entry point", assuming entry_point is equal to load_addr, but it's not true. Then load_addr is set to "entry_point - header_size", but this is wrong too since load_addr is not an entry point. So use image_get_ep() for entry_point assignment and image_get_load() for load_addr assignment. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
| * | imx: dts: imx8dx: add I2C IPG clock for bus 0 and 2Anatolij Gustschin2020-01-141-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | IPG clock description is missing for I2C0 and I2C2 busses, add it. Otherwise we see -ENODATA error when trying to get I2C clock for these busses. Signed-off-by: Anatolij Gustschin <agust@denx.de> Cc: Stefano Babic <sbabic@denx.de>
| * | clk: imx8qxp: extend to support getting I2C IPG clockAnatolij Gustschin2020-01-141-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since commit d02be21d3004 ("i2c: imx_lpi2c: add ipg clk") getting I2C clocks doesn't work. Add I2C IPG clock IDs to related switch statements to fix it. Signed-off-by: Anatolij Gustschin <agust@denx.de> Cc: Lukasz Majewski <lukma@denx.de> Reviewed-by: Peng Fan <peng.fan@nxp.com>
generated by cgit (git 2.34.1) at 2024-10-04 05:28:06 +0000