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* Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini2020-01-0884-1952/+4392
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| * ddr: socfpga: Enable ARM64 Non-Secure SDRAM ECC AccessThor Thayer2020-01-072-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | The ECC registers in the SDRAM HMC Adapter should always be accessible (both when ECC is enabled and disabled). Currently, the registers are accessible only when ECC is enabled. The ECC Enabled bit is used to determine the status of ECC by later OSes so always allow access. Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
| * arm: socfpga: stratix10: Enable SMMU accessThor Thayer2020-01-072-0/+21
| | | | | | | | | | | | | | | | Enable TCU access through the Stratix10 CCU so that the SMMU can access the SDRAM. Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
| * configs: socfpga: fix building Stratix10 and AgilexSimon Goldschmidt2020-01-071-1/+0
| | | | | | | | | | | | | | This fixes a merge error that accidentally left CONFIG_MTD_DEVICE active by removing it from the config file. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
| * arm: socfpga: agilex: Enable Agilex SoC buildLey Foon Tan2020-01-076-3/+104
| | | | | | | | | | | | | | Add build support for Agilex SoC. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
| * configs: socfpga: Move Stratix10 and Agilex common CONFIGsLey Foon Tan2020-01-072-189/+202
| | | | | | | | | | | | | | Move Stratix10 and Agilex common CONFIGs to socfpga_soc64_common.h. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
| * arm: dts: agilex: Add base dtsi and devkit dtsLey Foon Tan2020-01-075-0/+899
| | | | | | | | | | | | | | | | | | | | | | | | | | Add device tree files for Agilex SoC platform. socfpga_agilex-u-boot.dtsi and socfpga_agilex_socdk-u-boot.dts contains Uboot specific DT properties. socfpga_agilex.dtsi and socfpga_agilex_socdk.dts are from Linux (kernel/git/dinguyen/linux.git, commit 6f0bf971bacacc) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
| * arm: socfpga: agilex: Add SPL for Agilex SoCLey Foon Tan2020-01-072-0/+101
| | | | | | | | | | | | | | Add SPL support for Agilex SoC. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
| * board: intel: agilex: Add socdk board support for Intel Agilex SoCLey Foon Tan2020-01-073-0/+21
| | | | | | | | | | | | | | Add socdk board support for Intel Agilex SoC Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
| * ddr: altera: agilex: Add SDRAM driver for AgilexLey Foon Tan2020-01-075-3/+174
| | | | | | | | | | | | | | | | Add SDRAM driver for Agilex SoC. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
| * ddr: altera: Restructure Stratix 10 SDRAM driverLey Foon Tan2020-01-075-443/+493
| | | | | | | | | | | | | | | | Restructure Stratix 10 SDRAM driver. Move common code to separate file, in preparation to support SDRAM driver for Agilex. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
| * arm: agilex: Add clock handoff offset for AgilexLey Foon Tan2020-01-072-4/+10
| | | | | | | | | | | | | | Add clock handoff offset for Agilex. Remove S10 prefix to avoid confusion. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
| * cache: Add Arteris Ncore cache coherent unit driverLey Foon Tan2020-01-073-0/+173
| | | | | | | | | | | | | | | | | | | | | | | | Add Cache Coherency Unit (CCU) driver. CCU is to ensures consistency of shared data between multi masters in the system. Driver initializes CCU's directories and coherency agent interfaces in CCU IP. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
| * arm: socfpga: agilex: Add clock wrapper functionsLey Foon Tan2020-01-074-0/+105
| | | | | | | | | | | | | | | | Add clock wrapper functions call to clock DM functions to get clock frequency and used in cm_print_clock_quick_summary(). Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
| * clk: agilex: Add clock driver for AgilexLey Foon Tan2020-01-075-0/+893
| | | | | | | | | | | | | | | | | | | | | | Add clock manager driver for Agilex. Provides clock initialization and get_rate functions. agilex-clock.h is from Linux commit ID cd2e1ad12247. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
| * arm: socfpga: Fix CLKMGR_INTOSC_HZ to 400MHzLey Foon Tan2020-01-071-3/+1
| | | | | | | | | | | | | | | | CLKMGR_INTOSC_HZ should be 400MHz, instead of 460MHz. Removed also unused macros CLKMGR_EOSC1_HZ and CLKMGR_FPGA_CLK_HZ. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
| * arm: socfpga: Move Stratix10 and Agilex clock manager common codeLey Foon Tan2020-01-072-13/+26
| | | | | | | | | | | | | | Move Stratix10 and Agilex clock manager common code to new header file. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
| * arm: socfpga: agilex: Add system manager supportLey Foon Tan2020-01-071-1/+2
| | | | | | | | | | | | | | Add system manager support for Agilex. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
| * arm: socfpga: Move Stratix10 and Agilex system manager common codeLey Foon Tan2020-01-0712-156/+159
| | | | | | | | | | | | | | | | Move Stratix10 and Agilex system manager common code to system_manager_soc64.h. Changed macros to use SYSMGR_SOC64_*. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
| * arm: socfpga: agilex: Add reset manager supportLey Foon Tan2020-01-071-1/+2
| | | | | | | | | | | | | | Add reset manager support for Agilex. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
| * arm: socfpga: Move Stratix10 and Agilex reset manager common codeLey Foon Tan2020-01-074-106/+49
| | | | | | | | | | | | | | | | | | | | Move Stratix10 and Agilex reset manager common code to reset_manager_soc64.h. Changed macros to RSTMGR_SOC64_*. Remove unused RSTMGR_XXX defines. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
| * arm: socfpga: Move firewall code to firewall fileLey Foon Tan2020-01-075-96/+117
| | | | | | | | | | | | | | | | | | | | | | Move firewall related code to new firewall.c, to share code in Stratix 10 and Agilex. SDMMC will transfer data to OCRAM in SPL. So, enable privilege for SDMMC to allow DMA transfer to OCRAM. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
| * arm: socfpga: agilex: Add base address for Intel Agilex SoCLey Foon Tan2020-01-071-0/+4
| | | | | | | | | | | | | | | | | | | | Add base address for Intel Agilex SoC. Reuse base_addr_s10.h for Agilex, only one base address is different from S10. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
| * arm: socfpga: Convert clock manager from struct to definesLey Foon Tan2020-01-0710-475/+501
| | | | | | | | | | | | | | | | | | | | | | Convert clock manager for Gen5, Arria 10 and Stratix 10 from struct to defines. Change to get clock manager base address from DT node instead of using #define. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
| * arm: socfpga: Convert system manager from struct to definesLey Foon Tan2020-01-0725-422/+267
| | | | | | | | | | | | | | | | | | | | | | Convert system manager for Gen5, Arria 10 and Stratix 10 from struct to defines. Change to get system manager base address from DT node instead of using #define. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
| * arm: socfpga: Convert reset manager from struct to definesLey Foon Tan2020-01-0714-152/+153
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert reset manager for Gen5, Arria 10 and Stratix 10 from struct to defines. Change to get reset manager base address from DT node instead of using #define. spl_early_init() initializes the DT setup. So, move spl_early_init() to beginning of function and before get base address from DT. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
| * arm: dts: socfpga: Add u-boot, dm-pre-reloc for sysmgr and clkmgr nodesLey Foon Tan2020-01-076-3/+27
| | | | | | | | | | | | | | | | Add u-boot,dm-pre-reloc for sysmgr and clkmgr nodes to use it in SPL. In preparation to get base address from DT. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
| * spl: Allow cache drivers to be used in SPLLey Foon Tan2020-01-073-1/+8
| | | | | | | | | | | | | | | | Add an option for building cache drivers in SPL. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
* | Merge tag 'u-boot-amlogic-20200108' of ↵Tom Rini2020-01-0815-16/+334
|\ \ | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic - Khadas VIM3L based on Amlogic S905D3 support - Various fixups for amlogic boards - Unnecessary header includes drop into video/meson
| * | board: amlogic: select PWRSEQ for all amlogic platformAnand Moon2020-01-071-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit a10388dc6982 ("mmc: meson-gx: add support for mmc-pwrseq-emmc") introduce CONFIG_PWRSEQ for power sequence for eMMC module on amlogic platform, so enable this to all amlogic boards. Signed-off-by: Anand Moon <linux.amoon@gmail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
| * | configs: meson64: enable GIC support for G12A/G12BAnand Moon2020-01-071-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Enable GIC support for G12A/G12B platform. Signed-off-by: Anand Moon <linux.amoon@gmail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
| * | boards: amlogic: add Khadas VIM3L supportChristian Hewitt2020-01-073-0/+195
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Khadas VIM3L uses the same board layout as VIM3, but with an S905D3 chip instead of A311D. Board config is derived from khadas-vim3_defconfig and sei610_defconfig. README is based on README.khadas-vim3; the difference is that VIM3L uses FIP files from the g12a folder in vendor sources not the g12b folder. Signed-off-by: Christian Hewitt <christianshewitt@gmail.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> [narmstrong: added vim3l readme into w400 MAINTAINERS]
| * | ARM: dts: Import Khadas VIM3L DT from Linux 5.5-rc1Christian Hewitt2020-01-072-0/+96
| | | | | | | | | | | | | | | | | | | | | | | | | | | Import the Khadas VIM3L device-tree from [1] [1] e42617b825f8 ("Linux 5.5-rc1") Signed-off-by: Christian Hewitt <christianshewitt@gmail.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
| * | video: meson: Drop unnecessary header includesSimon Glass2020-01-078-15/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These files should not be included in meson header files. Drop them and tidy up the affected C files. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* | | Merge branch '2020-01-07-master-imports'Tom Rini2020-01-0846-80/+879
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | - DT overlay support in FIT images in SPL - remoteproc update - Assorted SATA fixes - Other assorted fixes
| * | | ata: fsl_sata: Continue probing other sata port when failed current port.Peng Ma2020-01-081-7/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the initialization of sata driver, we want to initialize all port probes, Therefore, any detection failure between of them should continue initialization by skipping the current port instead of exit. Signed-off-by: Peng Ma <peng.ma@nxp.com>
| * | | ata: sata_sil: Continue probing other sata port when failed current port.Peng Ma2020-01-081-4/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the initialization of sata driver, we want to initialize all port probes, Therefore, any detection failure between of them should continue initialization by skipping the current port instead of exit. Signed-off-by: Peng Ma <peng.ma@nxp.com>
| * | | treewide: Remove CONFIG_SYS_UBOOT_START from configs board filesPatrice Chotard2020-01-0813-16/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As previous CONFIG_SYS_UBOOT_START is now set by default to CONFIG_SYS_TEXT_BASE when not defined, CONFIG_SYS_UBOOT_START can be removed from include/configs board files. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Acked-by: Lukasz Majewski <lukma@denx.de>
| * | | Makefile: Fix CONFIG_SYS_UBOOT_START default valuePatrice Chotard2020-01-081-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patches restores boot on boards which rely on CONFIG_SYS_UBOOT_START equal to CONFIG_SYS_TEXT_BASE when using SPL Fixes: d3e97b53c1f2 ("spl: fix entry_point equal to load_addr") Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | | cmd/Kconfig: Add more dependencies to OSE bootm supportTom Rini2020-01-081-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Per Enea OSE documentation, it supports some classes of ARM, PowerPC and X86. Limit the option to those platforms. Signed-off-by: Tom Rini <trini@konsulko.com>
| * | | bdinfo: show multi_dtb_fitHeiko Schocher2020-01-071-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | if MULTI_DTB_FIT is enabled it is helpful to display the value of gd->multi_dtb_fit in bdinfo. Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | | cmd_ut: add a parameter prefix to the function cmd_ut_categoryPhilippe Reynes2020-01-079-12/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is black magic in the file conftest.py that list all the test unit. Then, all those test unit are called in pytest. This call is done with the end of the name (for example checksum if the full name is bloblist_test_checksum). The result is that only test for dm are really executed. by pytest, all others tests are listed but never executed. This behaviour happens because the dm test unit only check the end of the name and others tests checks the full name. To fix this issue, I've added a prefix to the function cmd_ut_category, and this prefix is removed when looking for the unit test. Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com> Tested-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
| * | | power: regulator: support off-on-delay-usPeng Fan2020-01-071-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | off-on-delay-us has been supported by Linux, so let's use it. Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * | | remoteproc: stm32: load resource table from firmwareFabien Dessenne2020-01-071-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Load the optional resource table from the firmware, and write its address in the dedicated backup register. Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com> Acked-by: Patrick Delaunay <patrick.delaunay@st.com>
| * | | stm32mp1: remove copro_state environment variableFabien Dessenne2020-01-071-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since the coprocessor state is tracked in a backup register, there is no more need for tracking it in an environment variable : remove it. Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com> Acked-by: Patrick Delaunay <patrick.delaunay@st.com>
| * | | remoteproc: stm32: track the coprocessor state in a backup registerFabien Dessenne2020-01-071-12/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update the dedicated backup register to track the coprocessor state and rely on that register to compute the .is_running() value (which expects a return value of 0 -not 1- if the processor is running). Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com> Acked-by: Patrick Delaunay <patrick.delaunay@st.com>
| * | | stm32mp1: reset coprocessor status at cold bootFabien Dessenne2020-01-071-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Reset ResourceTableAddress and CoprocessorState at cold boot, preserve these values at standby wakeup. Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com> Acked-by: Patrick Delaunay <patrick.delaunay@st.com>
| * | | stm32mp1: declare backup registers for coprocessorFabien Dessenne2020-01-071-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the backup register #17 as coprocessor resource table address and backup register #18 as coprocessor state. Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com> Acked-by: Patrick Delaunay <patrick.delaunay@st.com>
| * | | remoteproc: elf_loader: Add elf resource table load supportFabien Dessenne2020-01-073-11/+419
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add rproc_elf_load_rsc_table(), which searches for a resource table in an elf64/elf32 image, and if found, copies it to device memory. Add also the elf32 and elf64 variants of this API. Add a test for this. Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com> Acked-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
| * | | spl: fit: Allow the board to tell if more images must be loaded from FITJean-Jacques Hiblot2020-01-071-3/+62
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | spl_fit_get_image_name() is used to get the names of the images that the SPL must load from the FIT. It relies on the content of a property present in the FIT. The list of images is thus statically defined in the FIT. With this scheme, it quickly becomes hard to manage combinations of more than a handful of images. To address this problem, give the board driver code the opportunity to add to the list of images. The images from the FIT property are loaded first, and then the board_get_fit_loadable() is called to get more image names. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org>
generated by cgit (git 2.34.1) at 2025-01-10 15:22:19 +0000