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* ARM: Tegra186: don't map memory not in RAM banksStephen Warren2018-01-122-26/+55
| | | | | | | | | | | | | | | | | | | | Tegra186 currently restricts its DRAM usage to entries in the /memory node in the DTB passed to it. However, the MMU configuration always maps the entire first 2GB of RAM. This could allow the CPU to speculatively access RAM that isn't part of the in-use banks. This patch switches to runtime construction of the table that's used to construct the MMU translation tables, and thus prevents access to RAM that's not part of a valid bank. Note: This patch is intended to prevent access to RAM regions which U-Boot does not need to access, with the primary purpose of avoiding theoretical speculative access to physical regions for which the HW will throw errors (e.g. carve-outs that the CPU has no permission to access at a bus level, bad ECC pages, etc.). In particular, this patch is not deliberately related to the speculation-related security issues that were recently announced. The apparent similarity is a coincidence. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARM: tegra: p2771-000: increase max DRAM bank countStephen Warren2018-01-121-0/+3
| | | | | | | | | | On this platform, there may be up to 1024 unusable chunks of memory. Increase CONFIG_NR_DRAM_BANKS so that U-Boot can remember all the banks required to represent such fragmented memory. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARM: Tegra186: search for best RAM bankStephen Warren2018-01-121-19/+69
| | | | | | | | | | | | In the future, the list of DRAM regions passed to U-Boot in the DTB may be quite long and fragmented. Due to this, U-Boot must search through the regions to find the best region to relocate into, rather than relying on the current assumption that the top of bank 0 is a reasonable relocation target. This change implements such searching. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARM: bootm: don't assume sp is in DRAM bank 0Stephen Warren2018-01-121-3/+12
| | | | | | | | | | | | arch_lmb_reserve() currently assumes that the stack pointer is within DRAM bank 0. This is not necessarily true. Enhance the code to search through DRAM banks until the bank that does contain SP is found, and then reserve the tail of that bank. Fixes: 2d1916e48bd8 ("ARM: add flat device tree support") Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARM: Tegra186: mem parsing fixes from downstreamStephen Warren2018-01-121-7/+13
| | | | | | | | | | | | | Apply a few small fixes for the DTB /memory node parsing from NVIDIA's downstream U-Boot: - Allow arbitrary number of DRAM banks. - Correctly calculate the number of DRAM banks. - Clip PCIe memory in the same way as U-Boot CPU memory use. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARM: tegra: use LINUX_KERNEL_IMAGE_HEADERStephen Warren2018-01-121-0/+6
| | | | | | | | | Enable CONFIG_LINUX_KERNEL_IMAGE_HEADER for all 64-bit Tegra boards. cboot (the boot SW that runs before U-Boot) will eventually use this information. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARMv8: add optional Linux kernel image headerStephen Warren2018-01-125-1/+159
| | | | | | | | | | | Allow placing a Linux kernel image header at the start of the U-Boot binary. This is useful since the image header reports the amount of memory (BSS and similar) that U-Boot needs to use, but that isn't part of the binary size. This can be used by the code that loads U-Boot into memory to determine where to load U-Boot, based on other users of memory. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARM: tegra: use CONFIG_SYS_INIT_SP_BSS_OFFSETStephen Warren2018-01-125-10/+8
| | | | | | | | | | | Enable CONFIG_SYS_INIT_SP_BSS_OFFSET for all 64-bit Tegra boards. Place the stack/... 512KiB from the end of the U-Boot binary. This should be plenty to accommodate the current DTBs (max 64 KiB), early malloc region (6KiB), stack usage, and plenty of slack, while still not placing it too far away from the U-Boot binary. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARMv8: Allow dynamic early stack pointerStephen Warren2018-01-122-0/+16
| | | | | | | | | | | | | | U-Boot typically uses a hard-coded value for the stack pointer before relocation. Implement option SYS_INIT_SP_BSS_OFFSET to instead calculate the initial SP at run-time. This is useful to avoid hard-coding addresses into U-Boot, so that can be loaded and executed at arbitrary addresses and thus avoid using arbitrary addresses at runtime. This option's value is the offset added to &_bss_start in order to calculate the stack pointer. This offset should be large enough so that the early malloc region, global data (gd), and early stack usage do not overlap any appended DTB. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARM: tegra: remove SPL config for non-SPL SoCsStephen Warren2018-01-123-10/+2
| | | | | | | | No 64-bit Tegra uses SPL. Remove various unused definitions from config headers. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARM: tegra: don't use CONFIG_SPL_TEXT_BASE when no SPLStephen Warren2018-01-121-6/+9
| | | | | | | | | | 64-bit Tegra don't use SPL, and soon won't define CONFIG_SPL_TEXT_BASE when building. Fix the binman .dts file so that it doesn't use undefined values. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* Merge git://git.denx.de/u-boot-sunxiTom Rini2018-01-116-1/+211
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| * configs: sun50i: Enable eMMC on a64-olinuxinoJagan Teki2018-01-121-0/+1
| | | | | | | | | | | | | | a64-olinuxino has 8GiB eMMC, enable it. Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * ARM: sunxi: Remove left-over cd-inverted property from pcDuino3Tuomas Tynkkynen2018-01-101-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 8620f384098b ("dm: sunxi: Linksprite_pcDuino3: Correct polarity of MMC card detect") claims that the Pcduino3 device tree had an incorrect polarity for the card detect pin and thus changed the polarity flag of the cd-gpios from GPIO_ACTIVE_HIGH to GPIO_ACTIVE_LOW. Actually the DT was correct since according to the mmc binding, a combination of GPIO_ACTIVE_HIGH + cd-inverted results in an active-low polarity. But because the U-Boot driver lacks the code to look at the cd-inverted property (unlike the Linux driver) it interpreted the polarity of active-high. Thus, after that commit the DT is actually wrong from the binding/Linux point of view. To make both Linux and U-Boot interpret the DT in the same way, just drop the left-over cd-inverted property. I've sent a Linux patch to switch all sunxi DTs over to not using the cd-inverted property, so eventually all sunxi boards in U-Boot will be consistent in not using cd-inverted. Signed-off-by: Tuomas Tynkkynen <tuomas@tuxera.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * sunxi: maintainers: Add myself for the TBS A711Maxime Ripard2018-01-101-0/+5
| | | | | | | | | | | | | | | | | | Support for that board got introduced recently without the maintainers part. Let's fix that. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * sunxi: Add support for Libre Computer Board ALL-H3-CC H3 ver.Chen-Yu Tsai2018-01-104-0/+205
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Libre Computer Board ALL-H3-CC from Libre Technology is a Raspberry Pi B+ form factor single board computer based on the Allwinner H3 SoC. The board has 1GB DDR3 SDRAM, provided by 4 2Gb chips. The mounting holes and connectors are in the exact same position as on the Raspberry Pi B+. Raspberry Pi B+ like peripherals supported on this board include: - Power input through micro-USB connector (without USB OTG) - Native 100 Mbps ethernet using the internal PHY, as opposed to USB-based on the RPi - 4x USB 2.0 host ports, directly connected to the SoC, as opposed to being connected through a USB 2.0 hub on the RPi - TV and audio output on a 3.5mm TRRS jack - HDMI output - Micro-SD card slot - Standard RPi B+ GPIO header, with the standard peripherals routed to the same pins. * 5V, 3.3V power, and ground * I2C0 on the H3 is routed to I2C1 pins on the RPi header * I2C1 on the H3 is routed to I2C0 pins on the RPi header * UART1 on the H3 is routed to UART0 pins on the RPi header * SPI0 on the H3 is routed to SPI0 pins on the RPi header, with GPIO pin PA17 replacing the missing Chip Select 1 * I2S1 on the H3 is routed to PCM pins on the RPi header - Additional peripherals from the H3 are available on different pins. These include I2S0, JTAG, PWM1, SPDIF, SPI1, and UART3 In addition, there are a number of new features: - Console UART header - Consumer IR receiver - Camera interface (not compatible with RPi) - Onboard microphone - eMMC expansion module port - Heatsink mounting holes This patch adds defconfig and dts files for this board. The dts file is the same as the one submitted for inclusion in Linux, with some minor revisions to match the dtsi file and old EMAC bindings in U-boot. Since the OTG controller is wired to a USB host port, and the H3 has proper USB hosts to handle host mode, the MUSB driver is not enabled. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
* | Merge git://git.denx.de/u-boot-videoTom Rini2018-01-117-26/+71
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| * | board/BuR: drop LCDC clock manipulation from board codeHannes Schmelzer2018-01-112-5/+0
| | | | | | | | | | | | | | | | | | | | | | | | The clock selection is done now from the am335x-fb code, so there is no more need doing this in the board code. Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at> Reviewed-by: Anatolij Gustschin <agust@denx.de>
| * | board/BuR: provide real clock-frequency instead a dividerHannes Schmelzer2018-01-111-10/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | Actual am335x-fb implementation takes now a real clock frequency instead a divider. So this component doesn't need to know anymore some base frequency of the LCDC, we simply provide the pixel-clock frequency. Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at> Reviewed-by: Anatolij Gustschin <agust@denx.de>
| * | am335x-fb: setup display PLLHannes Schmelzer2018-01-112-4/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The LCDC IP-core an be feed from several clock sources, one of those is a dedicated DPLL for generating a dividable base-clock for this IP-core. The TRM specifies the maximum input frequency for the LCCD with 200 MHz, so we must not exceed this value with the PLL frequency (which can lock much higher). This patch tries every combination of multipliers and divisors of the PLL and the IP-core itself for getting as near as possible the the requested panel->pxl_clk. Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at> Reviewed-by: Anatolij Gustschin <agust@denx.de>
| * | am335x-fb: cosmetic: fix coding styleHannes Schmelzer2018-01-111-3/+3
| | | | | | | | | | | | | | | Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at> Reviewed-by: Anatolij Gustschin <agust@denx.de>
| * | am335x-fb: cosmetic: update-copyrightHannes Schmelzer2018-01-112-4/+4
| | | | | | | | | | | | | | | Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at> Reviewed-by: Anatolij Gustschin <agust@denx.de>
| * | mach-omap2: add AM335x Display PLL register definitionHannes Schmelzer2018-01-112-0/+8
| | | | | | | | | | | | | | | | | | | | | Adds the register definition of the Display DPLL Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at> Reviewed-by: Anatolij Gustschin <agust@denx.de>
* | | Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini2018-01-1147-390/+641
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| * | | ls1088ardb: Add SD Secure boot target supportSumit Garg2018-01-104-9/+71
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> [YS: run moveconfig.py -s] Reviewed-by: York Sun <york.sun@nxp.com>
| * | | armv8: ls1088a: SPL size reductionSumit Garg2018-01-104-7/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Using changes in this patch we were able to reduce approx 8k size of u-boot-spl.bin image. Following is breif description of changes to reduce SPL size: 1. Changes in board/freescale/ls1088a/Makefile to remove compilation of eth.c and cpld.c in case of SPL build. 2. Changes in board/freescale/ls1088a/ls1088a.c to keep board_early_init_f funcations in case of SPL build. 3. Changes in ls1088a_common.h & ls1088ardb.h to remove driver specific macros due to which static data was being compiled in case of SPL build. Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | armv8: fsl-layerscape: SPL size reductionSumit Garg2018-01-101-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Compile-off mp.c and libfdt.c in case of SPL build. SPL size reduces by approx 2k. Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | Powerpc: T208xQDS: Modify the comment of the CONFIG_FSL_PCIE_RESET macroBao Xiaowei2018-01-101-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove duplicate macro CONFIG_FSL_PCIE_RESET and update its comment. It enables PCIe reset to fix link width 2x - 4x. Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | armv8: Implement workaround for Cortex-A53 erratum 855873Alison Wang2018-01-103-1/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 855873: An eviction might overtake a cache clean operation Workaround: The erratum can be avoided by upgrading cache clean by address operations to cache clean and invalidate operations. For Cortex-A53 r0p3 and later release, this can be achieved by setting CPUACTLR.ENDCCASCI to 1. This patch is to implement the workaround for this erratum. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | configs: Move SYS_DPAA_QBMAN to KconfigAhmed Mansour2018-01-1018-20/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The CONFIG_SYS_DPAA_QBMAN define is used by DPAA1 freescale SOCs to add device tree fixups that allow deep sleep in Linux. The define was placed in header files included by a number of boards, but was not explicitly documented in any of the Kconfigs. A description was added to the drivers/networking menuconfig and default selection for current SOCs that have this part Signed-off-by: Ahmed Mansour <ahmed.mansour@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | drivers/misc: Share qbman init between archsAhmed Mansour2018-01-1018-351/+454
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds changes necessary to move functionality present in PowerPC folders with ARM architectures that have DPAA1 QBMan hardware - Create new board/freescale/common/fsl_portals.c to house shared device tree fixups for DPAA1 devices with ARM and PowerPC cores - Add new header file to top includes directory to allow files in both architectures to grab the function prototypes - Port inhibit_portals() from PowerPC to ARM. This function is used in setup to disable interrupts on all QMan and BMan portals. It is needed because the interrupts are enabled by default for all portals including unused/uninitialised portals. When the kernel attempts to go to deep sleep the unused portals prevent it from doing so Signed-off-by: Ahmed Mansour <ahmed.mansour@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | armv8: layerscape: sata: refine port register configurationYuantian Tang2018-01-102-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Sata registers PP2C and PP3C are used to control the configuration of the PHY control OOB timing for the COMINIT/COMWAKE parameters respectively. Calculate those parameters from port clock frequency. Overwrite those registers with calculated values to get better OOB timing. Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | armv8: ls1088 : MC alignment should always be fixed to 512MBAshish Kumar2018-01-101-2/+1
| |/ / | | | | | | | | | | | | Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | | Merge git://git.denx.de/u-boot-socfpgaTom Rini2018-01-1114-6/+23
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| * | | arm: socfpga: Guard commands with CONFIG_SPL_BUILD testsTom Rini2018-01-092-6/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order for these commands to not be included in SPL we need to guard compilation with CONFIG_SPL_BUILD checks. Reorganize some sections of code slightly in order to avoid new warnings and mark the command functions as static as they should have been before. Cc: Marek Vasut <marex@denx.de> Signed-off-by: Tom Rini <trini@konsulko.com>
| * | | ARM: socfpga: Enable part command for socfpga platformAndrey Zhizhikin2018-01-0912-0/+12
| |/ / | | | | | | | | | | | | | | | | | | Enable CONFIG_CMD_PART item, as default environment requires it and complains this command in unknown. Signed-off-by: Andrey Zhizhikin <andrey.z@gmail.com>
* | | Merge git://git.denx.de/u-boot-usbTom Rini2018-01-1129-49/+1120
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| * | | rockchip: rk3288: enable rockusb support on rk3288 based deviceEddie Cai2018-01-1013-0/+98
| | | | | | | | | | | | | | | | | | | | | | | | | | | | this patch enable rockusb support on rk3288 based device. Signed-off-by: Eddie Cai <eddie.cai.linux@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | | rockchip:usb: add a simple readme for rockusbEddie Cai2018-01-102-0/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | add a simple readme to introduce rockusb and tell people how to use it Signed-off-by: Eddie Cai <eddie.cai.linux@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | | usb: rockchip: add rockusb commandEddie Cai2018-01-104-0/+84
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | this patch add rockusb command. the usage is rockusb <USB_controller> <devtype> <dev[:part]> e.g. rockusb 0 mmc 0 Signed-off-by: Eddie Cai <eddie.cai.linux@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | | usb: rockchip: add the rockusb gadgetEddie Cai2018-01-105-0/+865
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | this patch implement rockusb protocol on the device side. this is based on USB download gadget infrastructure. the rockusb function implements the rd, wl, rid commands. it can work with rkdeveloptool Signed-off-by: Eddie Cai <eddie.cai.linux@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | | musb: sunxi: Use base address from device treeChen-Yu Tsai2018-01-101-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that the musb sunxi glue driver is completely device model / device tree driven, we should use the base address from the device tree, instead of hard-coding it in the source code. Fixes: 3a61b080acee ("musb: sunxi: switch to the device model") Signed-off-by: Chen-Yu Tsai <wens@csie.org>
| * | | arm64: layerscape: Move CONFIG_HAS_FSL_DR_USB to KconfigRan Wang2018-01-094-42/+6
| | | | | | | | | | | | | | | | | | | | | | | | Rename to USB_EHCI_FSL, use Kconfig to select ehci accordingly. Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
| * | | usb: ehci: fsl: Fix some compile warnings.Ran Wang2018-01-091-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When enable CONFIG_HAS_FSL_DR_USB, we might encounter below compile warning, apply this patch can fix it: drivers/usb/host/ehci-fsl.c:109:4: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] ((u32)hccr + HC_LENGTH(ehci_readl(&hccr->cr_capbase))); ^ drivers/usb/host/ehci-fsl.c:108:9: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] hcor = (struct ehci_hcor *) ^ drivers/usb/host/ehci-fsl.c:115:8: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] (u32)hccr, (u32)hcor, ^ include/log.h:131:26: note: in definition of macro 'debug_cond' printf(pr_fmt(fmt), ##args); \ ^~~~ drivers/usb/host/ehci-fsl.c:114:2: note: in expansion of macro 'debug' debug("ehci-fsl: init hccr %x and hcor %x hc_length %d\n", ^~~~~ drivers/usb/host/ehci-fsl.c:115:19: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] (u32)hccr, (u32)hcor, ^ include/log.h:131:26: note: in definition of macro 'debug_cond' printf(pr_fmt(fmt), ##args); \ ^~~~ drivers/usb/host/ehci-fsl.c:114:2: note: in expansion of macro 'debug' debug("ehci-fsl: init hccr %x and hcor %x hc_length %d\n", ^~~~~ Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
| * | | armv8: ls1012a: Add USB 2.0 controller phy type for ls1012aqds boardRan Wang2018-01-091-0/+5
| |/ / | | | | | | | | | | | | | | | | | | Without this propertiy, U-Boot will pop warning of 'USB phy type not defined' when select CONFIG_HAS_FSL_DR_USB. Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
* | | Merge git://git.denx.de/u-boot-marvellTom Rini2018-01-108-13/+164
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| * | | ARM: mvebu: correct reference for "ethernet1" on DB-88F6820-AMCChris Packham2018-01-101-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The DB-88F6820-AMC connects ethernet@34000 and ethernet@70000 which are labeled as eth2 and eth0 in armada-38x.dts. The ethernet@30000 (eth1) is not used on the AMC board. This eliminates the following bootup message Device 'ethernet@70000': seq 0 is in use by 'ethernet@34000' Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * | | pinctrl: mvebu: Make drivers depend on the pinctrl frameworkMiquel Raynal2018-01-091-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Armada pinctrl drivers shall not be compiled without the entire pinctrl framework and thus lack a "depends on" condition, otherwise the driver will simply not be probed. Signed-off-by: Miquel Raynal <miquel.raynal@free-electrons.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * | | ARM: mvebu: Allow MVNETA to be selected with Armada 3700 SoCsMiquel Raynal2018-01-091-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Until now, Armada 3700 SoCs could not enable the mvneta driver, and thus did not benefit from Ethernet support. Add ARMADA_3700 in the "depends on" list of the MVNETA Kconfig entry. Signed-off-by: Miquel Raynal <miquel.raynal@free-electrons.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * | | arm: mvebu: ClearFog: document boot selection switches, update UARTFlorian Klink2018-01-091-4/+17
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Florian Klink <flokli@flokli.de> Signed-off-by: Stefan Roese <sr@denx.de>
generated by cgit (git 2.34.1) at 2024-09-20 22:04:05 +0000