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* T4240/ramboot: enable PBL tool for T4240Shaohui Xie2013-05-243-0/+45
| | | | | | | | Added a default RCW(1_28_6_12) and PBI configure file for T4240, so it can use PBL tool to produce the ramboot image. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/t4240qds: Add VDD overrideYork Sun2013-05-242-2/+61
| | | | | | | | | | | | | | | | | | | | Allow VDD voltage overriding with a command. This is an add-on feasture of VID. To override VDD, use command vdd_override with the value of voltage in mV, for example vdd_override <voltage in mV, eg. 1050> The above example will set the VDD to 1.050 volt. Any wrong value out of range of 0.8188 to 1.2125 volt or invalid string is ignored. In addition to the command, if overriding VDD is needed earlier in booting process, save an variable and reboot: setenv t4240qds_vdd_mv <voltage in mV> saveenv Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/mpc85xx: check if core is disabled for showing statusYork Sun2013-05-241-0/+2
| | | | | | | | "cpu <num> status" should check if core is disabled before printing the spin table location. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* net/phy: fix select line for TN80xxShaohui Xie2013-05-241-2/+14
| | | | | | | | | | TN80xx has same PHY ID as TN2020, but it needs different setting to register 30.93 which used to select line, so we read register 30.32 which has bit 15:12 to indicate PHY hardware version, for TN20xx we will get 3 or 2, for TN80xx we will get 5 or 4. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* Enable L2 cache parity/ECC error checkingJames Yang2013-05-242-2/+2
| | | | | Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/t4240qds: Add board detail for bdinfo commandYork Sun2013-05-241-0/+100
| | | | | | | | | | Print more detail information including core voltage, RCW source, switch settings, etc. with bdinfo command. Signed-off-by: York Sun <yorksun@freescale.com> CC: Wolfgang Denk <wd@denx.de> CC: Tom Rini <trini@ti.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* common: Update cmd_bdinfo for PPCYork Sun2013-05-241-0/+5
| | | | | | | Add board detail function to print more individual board information. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* cmd_mem: fix cp commandMasahiro Yamada2013-05-241-1/+1
| | | | | | | | | | | | | The "cp" command has not worked since commit 0628ab8ec59834f98ede267edd21ddb8ba0bb57b, because of the following lines, which set the destination and the source to the same address. buf = map_sysmem(addr, bytes); src = map_sysmem(addr, bytes); Tested-by: Tom Rini <trini@ti.com> Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* ext4: assign get_fs()->dev_desc before using itStephen Warren2013-05-241-1/+1
| | | | | | | | | | | | Commit 50ce4c0 "fs/ext4: Support device block sizes != 512 bytes" modified ext4fs_set_blk_dev() to calculate total_sect based on get_fs()->dev_desc->log2blksz rather than SECTOR_SIZE. However, this value wasn't yet assigned. Move the assignment earlier so the code doesn't crash or hang. Cc: Egbert Eich <eich@suse.com> Tested-by: Tom Rini <trini@ti.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* cfi_flash: return NULL for invalid base address inputMasahiro Yamada2013-05-231-3/+3
| | | | | | | | | | | | | | | | | When base address given was out of valid flash address ranges, flash_get_info() function returned the pointer to the last element of flash_info[i] array. This patch changes this function to return NULL pointer in such a case, which is more correct behaviour. The function flash_protect_default() calls flash_protect() immediately after flash_get_info() invocation. With this correction, flash_protect() function would be able to return soon, for NULL flash_info. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Signed-off-by: Stefan Roese <sr@denx.de>
* cosmetic: cfi_flash: delete a space after an unary operatorMasahiro Yamada2013-05-231-1/+1
| | | | | | | | Linux Kernel Documentation/CodingStyle says: Do not add a space after unary operators such as &, *, ... Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Signed-off-by: Stefan Roese <sr@denx.de>
* cfi_flash: Fix unaligned accesses to cfi_qry structureAndrew Gabbasov2013-05-232-13/+20
| | | | | | | | | | | | | | | Packed structure cfi_qry contains unaligned 16- and 32-bits members, accessing which causes problems when cfi_flash driver is compiled with -munaligned-access option: flash initialization hangs, probably due to data error. Since the structure is supposed to replicate the actual data layout in CFI Flash chips, the alignment issue can't be fixed in the structure. So, unaligned fields need using of explicit unaligned access macros. Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com> Reviewed-By: Albert ARIBAUD <albert.u.boot@aribaud.net> Signed-off-by: Stefan Roese <sr@denx.de>
* Update MAINTAINERS file for sandboxSimon Glass2013-05-171-0/+11
| | | | | | This currently has no maintainer listed. Signed-off-by: Simon Glass <sjg@chromium.org>
* Update MAINTAINERS file for x86Simon Glass2013-05-171-3/+13
| | | | | | This still shows the previous maintainer. Signed-off-by: Simon Glass <sjg@chromium.org>
* .gitignore: add GNU GLOBAL filesMasahiro Yamada2013-05-171-0/+6
| | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* fdt_support: Use CONFIG_NR_DRAM_BANKS if definedDoug Anderson2013-05-171-0/+4
| | | | | | | | | It appears that there are some cases where we have more than 4 banks of memory. Use CONFIG_NR_DRAM_BANKS if it's defined to handle this. This will take up a little extra stack space (64 bytes extra if we go up to 8 banks), but that seems OK. Signed-off-by: Doug Anderson <dianders@chromium.org>
* bootm: Avoid 256-byte overflow in fixup_silent_linux()Doug Anderson2013-05-171-12/+29
| | | | | | | | | | | | | | This makes fixup_silent_linux() use malloc() to allocate its working space, meaning that our maximum kernel command line should only be limited by malloc(). Previously it was silently overflowing the stack. Note that nothing about this change increases the kernel's maximum command line length. If you have a command line that is >256 bytes it's up to you to make sure that kernel can handle it. Signed-off-by: Doug Anderson <dianders@chromium.org> Acked-by: Mike Frysinger <vapier@gentoo.org>
* README: Correct reference for CONFIG_SUPPORT_RAW_INITRDTom Rini2013-05-161-1/+1
| | | | Signed-off-by: Tom Rini <trini@ti.com>
* powerpc/esdhc: Correct judgement for DATA PIO modeHaijun.Zhang2013-05-151-1/+1
| | | | | | | | | | | | The logic for the whether to configure for polling or DMA was mistakenly reversed in this patch: Commit 7b43db92110ec2f15c5f7187a165f2928464966b drivers/mmc/fsl_esdhc.c: fix compiler warnings Signed-off-by: Haijun Zhang <Haijun.Zhang@freescale.com> CC: Sun Yusong-R58495 <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* mmc: update Faraday FTSDC010 for rw performanceKuo-Jung Su2013-05-154-697/+400
| | | | | | | | | | | | | | | | Faraday FTSDC010 is a MMC/SD host controller. Although there is already a driver in current u-boot release, which is modified from eSHDC and contributed by Andes Tech. Its performance is too terrible on Faraday A36x SoC platforms, so I turn to implement this new version of driver which is 10+ times faster than the old one. It's carefully designed to be compatible with Andes chips, so it should be safe to replace it. Signed-off-by: Kuo-Jung Su <dantesu@faraday-tech.com> CC: Andy Fleming <afleming@gmail.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* Merge branch 'master' of git://www.denx.de/git/u-boot-mpc85xxTom Rini2013-05-1530-227/+1154
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| * T4240/eth: fix SGMII card PHY addressShaohui Xie2013-05-141-4/+133
| | | | | | | | | | | | | | | | | | | | | | | | | | QSGMII card assumed to be used by default, but if SGMII card is used, it will use different PHY address, but we don't know which card is used until we access PHY on the card. So we check the card type slot by slot, if we can read a PHY ID by reading a SGMII PHY address on a slot, then the slot must have a SGMII card pluged, we mark all ports on that slot, and fix dts to use the SGMII card PHY address when doing dts fixup for the marked ports. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/t4qds: Fix disabling remote I2C connectionEd Swarthout2013-05-142-3/+3
| | | | | | | | | | | | | | | | | | Only clear IRE bit in qixis brdcfg5 register and keep other bits unchanged. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/b4860qds: Assign DDR address in board fileYork Sun2013-05-141-0/+72
| | | | | | | | | | | | | | | | B4860QDS requires DDRC2 has 0 as base address and DDRC1 has higher address. This is the requirement for DSP cores to run in 32-bit address space. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/mpc8xxx: Allow board file to override DDR address assignmentYork Sun2013-05-141-1/+6
| | | | | | | | | | | | | | | | | | This gives boards flexibility to assign other than default addresses to each DDR controller. For example, DDR controler 2 can have 0 as the base and DDR controller 1 has higher memory. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/mpc85xx: Update workaround for DDR erratum A-004934York Sun2013-05-141-1/+1
| | | | | | | | | | | | | | | | The workaround has been updated to use a slightly different magic number. Change from 0x00003000 to 0x30003000. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * T4/usb: move usb 2.0 utmi dual phy init code to cpu_init.cRoy Zang2013-05-142-21/+22
| | | | | | | | | | | | | | | | This is what we have done for the UTMI PHY on P3041/P5020. Then the PHY initialization can be reused in kernel without “usb start” command. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * T4240/net: use QSGMII card PHY address by defaultShaohui Xie2013-05-142-57/+67
| | | | | | | | | | | | | | | | Use QSGMII card PHY address as default SGMII card PHY address, QSGMII card PHY address is variable depends on different slot. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * net/phy: add VSC8574 supportShaohui Xie2013-05-142-0/+69
| | | | | | | | | | | | | | | | | | | | The VSC8574 is a quad-port Gigabit Ethernet transceiver with four SerDes interfaces for quad-port dual media capability. This driver supports SGMII and QSGMII MAC mode. For now SGMII mode is tested. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/85xx: fix build error introduced by serdes_get_prtclShengzhou Liu2013-05-141-1/+0
| | | | | | | | | | | | | | Removed unused declare serdes_get_prtcl() which was no longer needed. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * net/fm: fixup ethernet for mEMACShengzhou Liu2013-05-142-0/+27
| | | | | | | | | | | | | | | | | | - set proper compatible property name for mEMAC. - fixed ft_fixup_port for dual-role mEMAC, which will lead to MAC node disabled incorrectly. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * t4240qds/eth: fixup ethernet for t4240qdsShengzhou Liu2013-05-143-18/+91
| | | | | | | | | | | | | | | | | | | | | | 1, Implemented board_ft_fman_fixup_port() to fix port for kernel. 2, Implemented fdt_fixup_board_enet() to fix node status of different slots and interfaces. 3, Adding detection of slot present for XGMII interface. 4, There is no PHY for XFI, so removed related phy address settings. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/85xx: add missing QMAN frequency calculationShaohui Xie2013-05-141-0/+4
| | | | | | | | | | | | | | | | When CONFIG_SYS_FSL_QORIQ_CHASSIS2 is not defined, QMAN frequency will not be initialized, and QMAN will have a wrong frequency display. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc: Add T4160QDSYork Sun2013-05-142-1/+17
| | | | | | | | | | | | | | | | | | T4160QDS shares the same platform as T4240QDS. T4160 is a low power version of T4240, with eight e6500 cores, two DDR3 controllers, and slightly different SerDes protocols. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/t4240qds: Move SoC define into boards.cfgYork Sun2013-05-142-4/+3
| | | | | | | | | | | | | | | | Separate CONFIG_PPC_T4240 from board config file. Prepare to add more SoC variants supported on the same board. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/mpc85xx: Add T4160 SoCYork Sun2013-05-147-2/+173
| | | | | | | | | | | | | | | | | | | | T4160 SoC is low power version of T4240. The T4160 combines eight dual threaded Power Architecture e6500 cores and two memory complexes (CoreNet platform cache and DDR3 memory controller) with the same high-performance datapath acceleration, networking, and peripheral bus interfaces. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/t4240: Fix SerDes protocol arrays with const prefixYork Sun2013-05-141-7/+7
| | | | | | | | | | | | | | Protocols are constants. Fix arrays with const prefix. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/mpc85xx: Fix PIR parsing for chassis2York Sun2013-05-141-3/+3
| | | | | | | | | | | | | | | | The PIR parsing algorithm we used is not only for E6500. It applies to all SoCs with chassis 2. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/corenet2: Print SerDes protocol in decimalYork Sun2013-05-141-1/+1
| | | | | | | | | | | | | | | | Use decimal and hexadecimal for protocol numbers. It helps to match with SoC user manual. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * T4/USB: Add USB 2.0 UTMI dual phy supportRoy Zang2013-05-143-2/+63
| | | | | | | | | | | | | | | | | | | | | | | | T4240 internal UTMI phy is different comparing to previous UTMI PHY in P3041. This patch adds USB 2.0 UTMI Dual PHY new memory map and enable it for T4240. The phy timing is very sensitive and moving the phy enable code to cpu_init.c will not work. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/t4240qds: Add voltage ID supportYork Sun2013-05-142-2/+239
| | | | | | | | | | | | | | | | T4240 has voltage ID fuse. Read the fuse and configure the voltage correctly. Core voltage has higher tolerance on over side than below. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/mpc85xx: Fix portal setupYork Sun2013-05-141-14/+22
| | | | | | | | | | | | | | | | | | Missing nodes of crypto, pme, etc in device tree is not a fatal error. Setting up the qman portal should skip the missing node and continue to finish the rest. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/mpc8xxx: Fix DDR 3-way interleavingYork Sun2013-05-141-8/+11
| | | | | | | | | | | | | | Should check if interleaving is enabled before using interleaving mode. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/t4240qds: Update DDR timing tableYork Sun2013-05-141-22/+34
| | | | | | | | | | | | | | | | | | | | Update the timing table to support more rank density, based on the theory that similar density DIMMs have similar clock adjust and write level start timing. Update the timing for 1600 and 1866 MT/s. Tested with Micron MT18JSF1G72AZ-1G9E1 DIMMs, iDIMM M3CN-4GMJ3C0C-M92. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * T4/SerDes: correct the SATA indexRoy Zang2013-05-141-2/+2
| | | | | | | | | | | | | | | | Lane H on SerDes4 should be SATA2 instead of SATA1 Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * Fman/t4240: some fix for 10G XAUIShaohui Xie2013-05-144-6/+20
| | | | | | | | | | | | | | | | | | | | 1. fix 10G mac offset by plus 8; 2. add second 10G port info for FM1 & FM2 when init ethernet info; 3. fix 10G lanes name to match lane protocol table; Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/t4240qds: fix XAUI card PHY addressShaohui Xie2013-05-141-4/+4
| | | | | | | | | | | | Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * T4/serdes: fix the serdes clock frequencyRoy Zang2013-05-141-2/+2
| | | | | | | | | | | | | | | | | | | | Reverse the bit sequence to set and display serdes clock frequency correctly. The correct bit maps in BRDCFG2 are 0 1 2 3 4 5 6 7 S1RATE[1:0] S2RATE[1:0] S3RATE[1:0] S4RATE[1:0] Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * e6500: Move L1 enablement after L2 enablementAndy Fleming2013-05-141-47/+47
| | | | | | | | | | | | | | | | | | | | The L1 D-cache on e6500 is write-through. This means that it's not considered a good idea to have the L1 up and running if the L2 is disabled. We don't actually *use* the L1 until after the L2 is brought up on e6500, so go ahead and move the L1 enablement after that code is done. Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/t4240qds: Fix SPI flash typeShaohui Xie2013-05-141-1/+1
| | | | | | | | | | | | | | T4240QDS uses a SST instead of SPANSION SPI flash. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
generated by cgit (git 2.34.1) at 2024-11-20 06:40:04 +0000