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* mtd: nand: raw: Move CONFIG_SYS_NAND_USE_FLASH_BBT to KconfigStefan Roese2019-08-25103-17/+91
| | | | | | | | | | | | | | | | | | Convert CONFIG_SYS_NAND_USE_FLASH_BBT to Kconfig, update defconfigs, headers and whitelist. Please note that this symbol already was used in Kconfig (imply in CONFIG_NAND_ATMEL) which did not work, since this symbol was not available in Kconfig. This changes now with this patch and all boards with CONFIG_NAND_ATMEL will have BBT enabled. Which is what I also need on my GARDENA AT91SAM based board. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Eugen Hristev <eugen.hristev@microchip.com> Cc: Miquel Raynal <miquel.raynal@bootlin.com> Cc: Gregory CLEMENT <gregory.clement@bootlin.com> [trini: Rework such that the configs are unchanged to start with] Signed-off-by: Tom Rini <trini@konsulko.com>
* Convert CONFIG_ARCH_CPU_INIT to KconfigAdam Ford2019-08-25268-54/+230
| | | | | | | | | This converts the following to Kconfig: CONFIG_ARCH_CPU_INIT Signed-off-by: Adam Ford <aford173@gmail.com> Acked-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Tested-by: Felix Brack <fb@ltec.ch>
* configs: Resync with savedefconfigTom Rini2019-08-2535-80/+33
| | | | | | Rsync all defconfig files using moveconfig.py Signed-off-by: Tom Rini <trini@konsulko.com>
* Merge tag 'u-boot-rockchip-20190823' of ↵Tom Rini2019-08-2456-965/+409
|\ | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip - remove rk3288 fennec board - remove SPL raw image support for Rockchip SoCs - add common misc_init_r() for ethaddr from cpuid - enable USB HOST support for rk3328 - unify code for finding a valid gpt in part driver
| * evb_rk3399: revert CONFIG_SYS_MMC_ENV_DEV to 0Max Kellermann2019-08-231-1/+1
| | | | | | | | | | | | | | | | | | | | | | This was changed to 1 in commit 0717dde057e, but a few months later, commit 5f9411af37b swapped the order of eMMC and SD card by assigning indexed aliases to `&sdhci` and `&sdmmc`. Signed-off-by: Max Kellermann <max.kellermann@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> (Add signature) Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
| * disk: efi: ignore 'IGNOREME' GPT header found on cros eMMCsUrja Rannikko2019-08-232-7/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | Some ChromeOS devices (atleast veyron speedy) have the first 8MiB of the eMMC write protected and equipped with a dummy 'IGNOREME' GPT header - instead of spewing error messages about it, just silently try the backup GPT. Note: this does not touch the gpt cmd writing/verifying functions, those will still complain. Signed-off-by: Urja Rannikko <urjaman@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * disk: efi: unify code for finding a valid gptUrja Rannikko2019-08-231-39/+34
| | | | | | | | | | | | | | There were 3 copies of the same sequence, make it into a function. Signed-off-by: Urja Rannikko <urjaman@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * board: puma: Use rockchip_* helpers to setup cpuid and macaddrRohan Garg2019-08-231-90/+18
| | | | | | | | | | | | | | We should use the shared helpers to setup the necessary parts Signed-off-by: Rohan Garg <rohan.garg@collabora.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * rockchip: rk3399: Enable CONFIG_MISC_INIT_R for the Rock PI 4Rohan Garg2019-08-231-0/+1
| | | | | | | | | | | | | | This enables us to set a static MAC address Signed-off-by: Rohan Garg <rohan.garg@collabora.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * rockchip: rk3399: derive ethaddr from cpuidRohan Garg2019-08-234-0/+154
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Generate a MAC address based on the cpuid available in the efuse block: Use the first 6 byte of the cpuid's SHA256 hash and set the locally administered bits. Also ensure that the multicast bit is cleared. The MAC address is only generated and set if there is no ethaddr present in the saved environment. This is based off of Klaus Goger's work in 8adc9d Signed-off-by: Rohan Garg <rohan.garg@collabora.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * rockchip: rk3288: remove fennec board supportKever Yang2019-08-2312-642/+1
| | | | | | | | | | | | Since there is no one using this board, remove it. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
| * rockchip: rk3399: defconfig: remove SPL raw image supportKever Yang2019-08-2315-0/+15
| | | | | | | | | | | | RK3399 SPL only support FIT image for ATF bl31. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
| * rockchip: rk3368: defconfig: remove SPL raw image supportKever Yang2019-08-231-0/+1
| | | | | | | | | | | | RK3368 SPL only support FIT image for ATF bl31. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
| * rockchip: rk3328: defconfig: remove SPL raw image supportKever Yang2019-08-232-0/+2
| | | | | | | | | | | | RK3328 SPL only support FIT image for ATF bl31. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
| * rockchip: Move config SYS_MALLOC_LEN to KconfigKever Yang2019-08-2310-10/+2
| | | | | | | | | | | | Use Kconfig for option SYS_MALLOC_LEN and default to 0x2000000. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
| * rockchip: dts: rk3328-rock64: fix usb power supplyKever Yang2019-08-231-21/+2
| | | | | | | | | | | | | | | | According to rock64 schemetic, both VCC_HOST1_5V and VCC_HOST_5V are controlled by USB20_HOST_DRV(GPIO0A2), fix it so that we can get correct power supply for USB HOST ports. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
| * rockchip: rk3328: migrate u-boot node to -u-boot.dtsiKever Yang2019-08-235-85/+66
| | | | | | | | | | | | | | Move all the nodes only shown in u-boot to -u-boot.dtsi to make rk3328.dtsi clean. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
| * rockchip: dts: rk3328-rock64: enable usb3 xhci controllerKever Yang2019-08-231-0/+4
| | | | | | | | | | | | Rock64 has a USB3.0 port, enable the controller so that we can use it. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
| * rockchip: clk: rk3328: add clk_enable ops for HCLK_HOST0Kever Yang2019-08-231-0/+12
| | | | | | | | | | | | Required to successfully probe the ehci generic driver Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
| * ram: rk3399: update cap and ddrconfig for each channel after initKever Yang2019-08-231-78/+81
| | | | | | | | | | | | | | | | | | We need to store all the ram related cap/map info back to register for each channel after all the init has been done in case some of register was reset during the process. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* | Merge branch '2019-08-23-master-imports'Tom Rini2019-08-24195-168/+195
|\ \ | | | | | | | | | | | | | | | - Migrate CONFIG_MX_CYCLIC, CONFIG_FSL_USDHC and CONFIG_MXS_GPIO to Kconfig - Fix some SPL/TPL and ARM64 dependencies
| * | Convert CONFIG_MX_CYCLIC to KconfigAdam Ford2019-08-2342-17/+43
| | | | | | | | | | | | | | | | | | | | | | | | This converts the following to Kconfig: CONFIG_MX_CYCLIC Signed-off-by: Adam Ford <aford173@gmail.com> Acked-by: David Lechner <david@lechnology.com>
| * | Convert CONFIG_FSL_USDHC to KconfigAdam Ford2019-08-23137-136/+123
| | | | | | | | | | | | | | | | | | | | | | | | | | | This converts the following to Kconfig: CONFIG_FSL_USDHC Signed-off-by: Adam Ford <aford173@gmail.com> [trini: Add IMX8M, TARGET_S32V234EVB to FSL_USDHC list] Signed-off-by: Tom Rini <trini@konsulko.com>
| * | Kconfigs: Various: Fix some SPL, TPL and ARM64 dependenciesAdam Ford2019-08-233-8/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Several options are presenting themselves on a various boards where the options are clearly not used. (ie, arm64 options on arm9, or SPL/TPL options when SPL or TPL are not defined) This patch is not attempting to be a complete list of items, but more like low hanging fruit. This patch attempts to reduce some of the menuconfig noise by defining dependencies so they don't appear when not used. Signed-off-by: Adam Ford <aford173@gmail.com>
| * | kconfig: Convert CONFIG_MXS_GPIO to KconfigLukasz Majewski2019-08-2315-7/+17
| |/ | | | | | | | | | | | | | | | | | | | | This converts the following to Kconfig: CONFIG_MXS_GPIO Travis-CI: https://travis-ci.org/lmajewski/u-boot-dfu/builds/571260789 Signed-off-by: Lukasz Majewski <lukma@denx.de> Acked-by: Peng Fan <peng.fan@nxp.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
* | Merge https://gitlab.denx.de/u-boot/custodians/u-boot-clkTom Rini2019-08-2315-38/+1178
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| * clk: imx: add i.MX8MM clk driverPeng Fan2019-08-222-0/+417
| | | | | | | | | | | | Add i.MX8MM clk driver support. Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * clk: imx: add i.MX8M composite clk supportPeng Fan2019-08-221-0/+170
| | | | | | | | | | | | Import i.MX8M composite clk from Linux Kernel 5.3.0-rc2 Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * clk: imx: add pll14xx driverPeng Fan2019-08-222-0/+406
| | | | | | | | | | | | | | Add pll14xx driver for i.MX8MM usage, modifed from Linux Kernel 5.3.0-rc1 Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * clk: imx: expose CCF entry for allPeng Fan2019-08-222-2/+16
| | | | | | | | | | | | Expose CCF entry, then we could avoid expand the SoC support list Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * sandbox: clk: add clk enable/disable test codePeng Fan2019-08-223-0/+46
| | | | | | | | | | | | | | | | | | | | | | Since we added clk enable_count and prograte clk child enabling operation to clk parent, so add a new function sandbox_clk_enable_count to get enable_count for test usage. And add test code to get the enable_count after we enable/disable the device clk. Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * clk: support clk tree dumpPeng Fan2019-08-221-30/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The previous code only dump the clk list. This patch is to support clk tree dump, and also dump the enable_cnt. The code used in patch is similar to dm_dump_all, but the code here only filter out the UCLASS_CLK devices. On i.MX8MM, Partial output: u-boot=> clk dump Rate Usecnt Name ------------------------------------------ 24000000 0 |-- clock-osc-24m 24000000 0 | |-- dram_pll_ref_sel 750000000 0 | | `-- dram_pll 750000000 0 | | `-- dram_pll_bypass 750000000 0 | | `-- dram_pll_out 24000000 0 | |-- arm_pll_ref_sel 1200000000 0 | | `-- arm_pll 1200000000 0 | | `-- arm_pll_bypass 1200000000 0 | | `-- arm_pll_out 1200000000 0 | | `-- arm_a53_src 1200000000 0 | | `-- arm_a53_cg 1200000000 0 | | `-- arm_a53_div 24000000 4 | |-- sys_pll1_ref_sel 800000000 4 | | `-- sys_pll1 800000000 4 | | `-- sys_pll1_bypass 800000000 4 | | `-- sys_pll1_out 40000000 0 | | |-- sys_pll1_40m Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * clk: prograte clk enable/disable to parentPeng Fan2019-08-221-6/+71
| | | | | | | | | | | | | | | | | | | | | | On i.MX8MM, thinking such as clk path OSC->PLL->PLL GATE->CCM ROOT->CCGR GATE->Device Only enabling CCGR GATE is not enough, we also need to enable PLL GATE to make sure the clk path work. So when enabling CCGR GATE, we could prograte to enabling PLL GATE to make life easier. Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * clk: introduce enable_countPeng Fan2019-08-223-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | As what Linux Kernel 5.3.0 provides when enable/disable clk, there is an enable_count in clk_core_disable/enable. Introduce enable_count to track the clk enable/disable count when clk_enable/disable for CCF. And Initialize enable_count to 0 when register the clk. And clk tree dump with enable_count will be supported, it will be easy for us to check the clk status with enable_count Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * test/py: Add cmd_memory dependency back to test_mmc_wrMichal Simek2019-08-221-1/+1
| | | | | | | | | | | | | | | | | | | | Based on discussion with Stephen Warren there was recommendation to list both memory and random command dependencies just in case that dependency is not properly handled by Kconfig. Fixes: a09c1f7e1c1b ("test/py: Fix MMC/SD block write test dependency") Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Stephen Warren <swarren@nvidia.com>
| * easylogo: avoid buffer overrunHeinrich Schuchardt2019-08-221-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Building easylogo with `HOST_TOOLS_ALL=y make tools` results in a build warning due to a possible buffer overrun: tools/easylogo/easylogo.c:453:4: note: ‘sprintf’ output between 7 and 262 bytes into a destination of size 256 sprintf (str, "%s, 0x%02x", app, *dataptr++); ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Truncate the output to fit into the destination buffer. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
| * jffs2: remove unused code filesUwe Kleine-König2019-08-222-1169/+0
| | | | | | | | | | I failed to find where these two files are used and a few test compile runs with JFFS2 enabled succeeded also without these.
| * mmc: mtk-sd: Add MT8183 SoC supportFabien Parent2019-08-221-0/+10
| | | | | | | | | | | | Add support for the MT8183 in the MediaTek MMC driver. Signed-off-by: Fabien Parent <fparent@baylibre.com>
| * mailmap: provide usage instructionHeinrich Schuchardt2019-08-221-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Looking at the contents of file .mailmap it seems that some editors assumed that translation is done by entering multiple lines into the file and the last one replaces the others. This is not how it works. The translation occurs according to entries in single lines as described in the git-check-mailmap man-page. Add a description of the file format. Add an entry for Alexander Graf as his old email address is not valid anymore. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
| * README: Clarify use of BSS during SPL board_init_f()Andreas Dannenberg2019-08-221-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The earlier commit.... commit a5a5d997b41a ("spl: Allow performing BSS init early before board_init_f()") ...introduced the ability to use BSS from SPL's board_init_f() as it may be required in certain exceptional use cases so go ahead and update the README to reflect this change. Note that as highlighted with the changes the use of the associated CONFIG option is generally not recommended. Signed-off-by: Andreas Dannenberg <dannenberg@ti.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
* | Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriqTom Rini2019-08-2270-196/+1533
|\ \ | | | | | | | | | | | | | | | - i2c dm model support of lx2160a, ls1088a, lx2088a, ls1028a - icid setup for ls1028a, ls1088a - other small fixes
| * | armv8: ls1028a: add icid setup for platform devicesLaurentiu Tudor2019-08-228-16/+76
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add ICID setup for the platform devices contained on this chip: usb, sata, sdhc, edma, qdma, gpu, display and sec. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Horia Geantă <horia.geanta@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
| * | armv8: ls1088a: add icid setup for platform devicesLaurentiu Tudor2019-08-226-10/+89
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add ICID setup for the platform devices contained on this chip: usb, sata, sdhc, sec. The ICID macros for SEC needed to be adapted because the format of the registers is different. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Horia Geantă <horia.geanta@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
| * | armv8: fsl-layerscape: make icid setup endianness awareLaurentiu Tudor2019-08-222-11/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current implementation assumes that the registers holding the ICIDs are universally big endian. That's no longer the case on newer platforms so update the code to take into account the endianness of each register. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Horia Geantă <horia.geanta@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
| * | armv8: fsl-layerscape: add base addresses for several devicesLaurentiu Tudor2019-08-221-0/+15
| | | | | | | | | | | | | | | | | | | | | Add CCSR base addresses for ESDHC2, EDMA QDMA, DISPLAY and GPU devices. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
| * | armv8: fsl-layerscape: add missing sec jr base address definesLaurentiu Tudor2019-08-221-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | Add defines for all the SEC job rings base addresses. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Horia Geantă <horia.geanta@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
| * | armv8: kconfig: Fix some platforms incorrect I2C clock dividerChuanhua Han2019-08-221-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | By default, i2c input clock is platform clk / 2, but some of the platform of i2c clock divider does not meet this kind of circumstance, so alone to set default values for these platforms. Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
| * | armv8: ls1088aqds: support DSPI mode by hwconfigChuanhua Han2019-08-223-0/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BRDCFG4[USBOSC] and BRDCFG5[SPR] register field of Qixis device is used to control SPI and other IP signal routing. USBOSC: 0= SPI_CLK used as external USB REFCLK input driven with 24.000 MHz. SPI devices are unusable in this mode. 1= SPI_CLK used as SPI clock. SPI devices are usable in this mode. USB block is clocked from internal sources SPR[3:2]: SPI_CS / SDHC_DAT4:7 Routing (schematic net CFG_SPI_ROUTE[3:2]): 00= SDHC/eMMC 8-bit 01= SD Card Rev 2.0/3.0 10= SPI on-board memory 11= TDM Riser / SPI off-board connector. The default value is 00 if an SDCard/eMMC card is selected as the boot device. SPR[1:0]: SPI_SIN/SOUT/SCK Routing (schematic net CFG_SPI_ROUTE[1:0]): 00= SDHC Sync loop 01= TDM Riser / SPI off-board connector. 10= SPI on-board memory. 11= SPI off-board connector. By default, the SPI feature is not available, so we need to configure the above register fields to select the route to the SPI feature. Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
| * | armv8: ls1028aqds: define ARCH_MISC_INIT to handle muxPankaj Bansal2019-08-221-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Define ARCH_MISC_INIT for LS1028AQDS platform to handle board related mux. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
| * | armv8: ls1046afrwy: Define CONFIG_ENV_ADDR for QSPI BootAlison Wang2019-08-221-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | Defines CONFIG_ENV_ADDR for QSPI Boot which specifies the start address of the flash sector containing the environment. It fixes the issue that bootcmd is always set as default at bootup. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
generated by cgit (git 2.34.1) at 2024-07-05 18:57:25 +0000