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* sunxi: Convert SUNXI_EMAC to KconfigMylène Josserand2017-04-209-8/+18
| | | | | | | | | Convert the SUNXI_EMAC config to Kconfig. Remove it from SYS_EXTRA_OPTIONS from many sunxi defconfig and renamed it into SUN4I_EMAC to not confuse it with SUN8I_EMAC. Signed-off-by: Mylène Josserand <mylene.josserand@free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* sunxi: mk802_defconfig: Remove SYS_EXTRA_OPTIONSMylène Josserand2017-04-201-1/+0
| | | | | | | | | The USB_EHCI configuration is already set in this defconfig using kconfig's config. This configuration in SYS_EXTRA_OPTIONS must be removed and so the SYS_EXTRA_OPTIONS. Signed-off-by: Mylène Josserand <mylene.josserand@free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* sunxi: icnova-a20-swac_defconfig: Remove CMD_BMP fromMylène Josserand2017-04-201-1/+0
| | | | | | | | This configuration is not necessary in a defconfig file so it is removed from the SYS_EXTRA_OPTIONS. Signed-off-by: Mylène Josserand <mylene.josserand@free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* sunxi: icnova-a20-swac_defconfig: Remove AXP209_POWERMylène Josserand2017-04-201-1/+1
| | | | | | | | | Remove the AXP209_POWER option from SYS_EXTRA_OPTIONS. As this configuration already exists on Kconfig, we just need to remove it from defconfig. Signed-off-by: Mylène Josserand <mylene.josserand@free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* sunxi: Move SUNXI_GMAC to KconfigMylène Josserand2017-04-2029-28/+54
| | | | | | | | Move the SUNXI_GMAC config option to Kconfig, remove it from SYS_EXTRA_OPTIONS and rename it into SUN7I_GMAC. Signed-off-by: Mylène Josserand <mylene.josserand@free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* sunxi: Add maintainer of the NanoPi NEO AirJelle van der Waa2017-04-181-0/+5
| | | | | | | Add myself as maintainer of the NanoPi NEO Air board. Signed-off-by: Jelle van der Waa <jelle@vdwaa.nl> Reviewed-by: Jagan Teki <jagan@openedev.com>
* Prepare v2017.05-rc2Tom Rini2017-04-171-1/+1
| | | | Signed-off-by: Tom Rini <trini@konsulko.com>
* Merge git://git.denx.de/u-boot-rockchipTom Rini2017-04-1624-15/+439
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| * rockchip: rk3399: spl: add UART0 support for SPLPhilipp Tomsich2017-04-153-8/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The RK3399-Q7 ("Puma") SoM exposes UART0 as the Qseven UART (i.e. the serial line available via standardised pins on the edge connector and available on a RS232 connector). To support boards (such as the RK3399-Q7) that require UART0 as a debug console, we match CONFIG_DEBUG_UART_BASE and add the appropriate iomux setup to the rk3399 SPL code. As we are already touching this code, we also move the board-specific UART setup (i.e. iomux setup) into board_debug_uart_init(). This will be called from the debug UART init when CONFIG_DEBUG_UART_BOARD_INIT is set. As the RK3399 needs to use its board_debug_uart_init() function, we have Kconfig enable it by default for RK3399 builds. With everything set up to define CONFIG_BAUDRATE via defconfig and with to have the SPL debug UART either on UART0 or UART2, the configs for the RK3399 EVB are then update (the change for the RK3399-Q7 is left for later to not cause issues on applying the change). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * rockchip: pmic: Enable RK808 for rk3399 evberic.gao@rock-chips.com2017-04-152-0/+44
| | | | | | | | | | | | | | | | For using mipi display, we need to enable lcd3v3 which supplied by rk808,so enable rk808 first. Signed-off-by: Eric Gao <eric.gao@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * rockchip: i2c: Enable i2c for rk3399eric.gao@rock-chips.com2017-04-153-0/+18
| | | | | | | | | | | | | | | | | | To enable mipi display, we need to enable pmic rk808 first for lcd3v3 power,which use i2c0 to communicate with soc. So enable i2c0. Signed-off-by: Eric Gao <eric.gao@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * rockchip: rk3399: Add missing sentinel in sysconeric.gao@rock-chips.com2017-04-151-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | when enable PMIC rk808,the system will halt at very early stage,log is shown as bellow. INFO: plat_rockchip_pmu_init(1211): pd status 3e INFO: BL31: Initializing runtime services INFO: BL31: Preparing for EL3 exit to normal world INFO: Entry point address = 0x200000 INFO: SPSR = 0x3c9 time 44561b, 0 (<<----Just stop here) It's caused by the absence of "{ }" in syscon_rk3399.c ,which will lead to memory overflow like below.According to Sysmap file ,we can find the function buck_get_value of rk808 is just follow the compatible struct,the pointer "of_match" point to "buck_get_value",but it is not a struct and don't have member of compatible, In this case, system crash. So,on the face, it looks like that rk808 is guilty.but he is really innocent. while (of_match->compatible) { <<---------- if (!strcmp(of_match->compatible, compat)) { *of_idp = of_match; return 0; } of_match++; } Signed-off-by: Eric Gao <eric.gao@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Tested-by: Kever Yang <kever.yang@rock-chips.com>
| * rockchip: ARM64: split RK3399-Q7 board off the RK3399-EVB boardKlaus Goger2017-04-159-1/+281
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The RK3399-Q7 SoM is a Qseven-compatible (70mm x 70mm, MXM-230 connector) system-on-module from Theobroma Systems, featuring the Rockchip RK3399. It provides the following feature set: * up to 4GB DDR3 * on-module SPI-NOR flash * on-module eMMC (with 8-bit interace) * SD card (on a baseboad) via edge connector * Gigabit Ethernet w/ on-module Micrel KSZ9031 GbE PHY * HDMI/eDP/MIPI displays * 2x MIPI-CSI * USB - 1x USB 3.0 dual-role (direct connection) - 2x USB 3.0 host + 1x USB 2.0 (on-module USB 3.0 hub) * on-module STM32 Cortex-M0 companion controller, implementing: - low-power RTC functionality (ISL1208 emulation) - fan controller (AMC6821 emulation) - USB<->CAN bridge controller Note that we use a multi-payload FIT image for booting and have Cortex-M0 payload in a separate subimage: we thus rely on the FIT image loader to put it into the SRAM region that ATF expects it in. Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Fixed build warning on puma-rk3399: Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
| * rockchip: dts: rk3399-puma: make the DTS dual-licensedPhilipp Tomsich2017-04-151-1/+1
| | | | | | | | | | | | | | | | The RK3399-Q7 (Puma) DTS should (of course) be dual-licensed. This updates the licensing info in the rk3399-puma.dts. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * rockchip: sysreset: rk3188: Make sure remap is off on warm-resetsHeiko Stübner2017-04-151-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | The warm-reset of rk3188 socs keeps the remap setting as it was, so if it was enabled, the cpu would start from address 0x0 of the sram instead of address 0x0 of the bootrom, thus making the reset hang. Therefore make sure the remap is disabled before attempting a warm reset. Cold reset is not affected by this at all. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Simon Glass <sjg@chromium.org>
| * rockchip: rk3399: do not use lower addressKever Yang2017-04-151-2/+2
| | | | | | | | | | | | | | The lower address is reserved for ATF, do not use it. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * rockchip: rk3188: enable remap functionHeiko Stübner2017-04-152-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Most Rockchip socs have the ability to either map the bootrom or a sram area to the starting address of the cpu by flipping a bit in the GRF. Newer socs leave this untouched and mapped to the bootrom but the legacy loaders on rk3188 and before enabled the remap functionality and the current smp implementation in the Linux kernel also requires it to be enabled, to bring up secondary cpus. So to keep smp working in the kernel, mimic the behaviour of the legacy bootloaders and enable the remap functionality. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Simon Glass <sjg@chromium.org>
| * rockchip: cosmetic: Move rock board to its correct positionHeiko Stübner2017-04-151-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Somehow 43b5c78d8d91 ("rockchip: cosmetic: Sort RK3288 boards") moved the rock board in between some rk3288 board, probably as a result of rebasing. So move it back to its original position above all rk3288 boards. Fixes: 43b5c78d8d91 ("rockchip: cosmetic: Sort RK3288 boards") Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Simon Glass <sjg@chromium.org>
| * rockchip: Add USB to the default boot targetsEddie Cai2017-04-151-0/+9
| | | | | | | | | | | | | | | | | | | | Now that most rockchip SoC based board have usb host support, enable USB boot targets by default. Signed-off-by: Eddie Cai <eddie.cai.linux@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Fixed build errors when CONFIG_CMD_USB not defined: Signed-off-by: Simon Glass <sjg@chromium.org>
| * rockchip: tinker: configs: Add USB, PXE, DHCP to the default boot targetsEddie Cai2017-04-151-1/+4
| | | | | | | | | | | | | | tinker board support ethernet and usb host, so enable USB, PXE and DHCP support. Signed-off-by: Eddie Cai <eddie.cai.linux@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * rockchip: dts: rk3399-puma: disable 'fifo-mode' in sdmmcPhilipp Tomsich2017-04-151-1/+0
| | | | | | | | | | Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Simon Glass <sjg@chromium.org>
| * rockchip: spl: rk3399: disable DDR security regions for SPLPhilipp Tomsich2017-04-151-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The RK3399 hangs during DMA of the Designware MMC controller, when performing DMA-based transactions in SPL due to the DDR security settings left behind by the BootROM (i.e. accesses to the first MB of DRAM are restricted... however, the DMA is likely to target this first MB, as it transfers from/to the stack). System security is not affected, as the final security configuration is performed by the ATF, which is executed after the SPL stage. With this fix in place, we can now drop 'fifo-mode' in the DTS for the RK3399-Q7 (Puma). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* | Merge git://git.denx.de/u-boot-dmTom Rini2017-04-1626-439/+778
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| * | board: sama5d3_xplained: Enable early debug UARTWenyou Yang2017-04-143-1/+24
| | | | | | | | | | | | | | | | | | | | | Enable the early debug UART to debug problems when an ICE or other debug mechanism is not available. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
| * | board: sama5d3_xplained: Clean up codeWenyou Yang2017-04-141-34/+0
| | | | | | | | | | | | | | | | | | | | | | | | Due to the introduction of the pinctrl and clk driver, and using device tree files, remove the unneeded hardcoded pin configuration and clock enabling code from the board file. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
| * | board: sama5d3_xplained: Update to support DM/DTWenyou Yang2017-04-144-25/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update the configuration files to support the device tree and driver model, so do SPL. The device clock and pins configuration are handled by the clock and the pinctrl drivers respectively. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Fix build error with sama5d3_xplained_mmc: Signed-off-by: Simon Glass <sjg@chromium.org>
| * | board: sama5d3xek: Enable early debug UARTWenyou Yang2017-04-144-1/+30
| | | | | | | | | | | | | | | | | | | | | Enable the early debug UART to debug problems when an ICE or other debug mechanism is not available. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
| * | board: sama5d3xek: Clean up codeWenyou Yang2017-04-142-134/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Due to the introduction of the pinctrl and clk driver, and using device tree files, remove the unneeded hardcoded pin configuration and clock enabling code from the board file. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Remove CONFIG_PHY_MICREL as per previous patch: Signed-off-by: Simon Glass <sjg@chromium.org>
| * | board: sama5d3xek: Update to support DM/DTWenyou Yang2017-04-145-35/+101
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update the configuration files to support the device tree and driver model, so do SPL. The device clock and pins configuration are handled by the clock and the pinctrl drivers respectively. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Add back CONFIG_PHY_MICREL to prevent a build error: Signed-off-by: Simon Glass <sjg@chromium.org>
| * | dm: led: Add a new 'led' commandSimon Glass2017-04-143-0/+155
| | | | | | | | | | | | | | | | | | | | | When driver model is used for LEDs, provide a command to allow LED access. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Ziping Chen <techping.chan@gmail.com>
| * | led: Mark existing driver as legacySimon Glass2017-04-142-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | The existing 'led' command does not support driver model. Rename it to indicate that it is legacy code. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Ziping Chen <techping.chan@gmail.com>
| * | dm: led: Add support for blinking LEDsSimon Glass2017-04-147-0/+83
| | | | | | | | | | | | | | | | | | | | | | | | Allow LEDs to be blinked if the driver supports it. Enable this for sandbox so that the tests run. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Ziping Chen <techping.chan@gmail.com>
| * | dm: led: Support toggling LEDsSimon Glass2017-04-143-0/+33
| | | | | | | | | | | | | | | | | | | | | | | | Add support for toggling an LED into the uclass interface. This can be efficiently implemented by the driver. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Ziping Chen <techping.chan@gmail.com>
| * | dm: led: Add support for getting the state of an LEDSimon Glass2017-04-144-0/+50
| | | | | | | | | | | | | | | | | | | | | | | | It is useful to be able to read the LED as well as write it. Add this to the uclass and update the GPIO driver. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Ziping Chen <techping.chan@gmail.com>
| * | dm: led: Adjust the LED uclassSimon Glass2017-04-144-14/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | At present this is very simple, supporting only on and off. We want to also support toggling and blinking. As a first step, change the name of the main method and use an enum to indicate the state. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Ziping Chen <techping.chan@gmail.com>
| * | dm: led: Rename struct led_uclass_platSimon Glass2017-04-143-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | These structures are normally named with 'uc' instead of 'uclass'. Change this one for consistency. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Ziping Chen <techping.chan@gmail.com>
| * | dm: led: Add a missing blank line in the Kconfig fileSimon Glass2017-04-141-0/+1
| | | | | | | | | | | | | | | | | | | | | There should be a blank line between each option. Add one before LED_GPIO. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Ziping Chen <techping.chan@gmail.com>
| * | sandbox: Add some test LEDsSimon Glass2017-04-142-0/+14
| | | | | | | | | | | | | | | | | | | | | Add some LEDs to the standard sandbox device tree. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Ziping Chen <techping.chan@gmail.com>
| * | dm: scsi: fix divide-by-0 error in scsi_scan()Jean-Jacques Hiblot2017-04-141-9/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With DM_SCSI enabled, blk_create_devicef() is called with blkz = 0, leading to a divide-by-0 exception. scsi_detect_dev() can be used to get the required parameters (block size and number of blocks) from the drive before calling blk_create_devicef(). Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | scsi: move the partition initialization out of the scsi detectionJean-Jacques Hiblot2017-04-141-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | We might want to get information about the scsi device without initializing the partition. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | scsi: make the LUN a parameter of scsi_detect_dev()Jean-Jacques Hiblot2017-04-141-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a cosmetic change. target and LUN have kind of the same role in this function. One of them was passed as a parameter and the other was embedded in a structure. For consistency, pass both of them as parameters. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | arm: omap: sata: compile out board-level sata code when CONFIG_DM_SCSI is ↵Jean-Jacques Hiblot2017-04-141-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | defined When CONFIG_DM_SCSI is defined, the SATA initialization will be implemented in the scsi-uclass driver. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * | arm: omap: sata: move enable sata clocks to enable_basic_clocks()Mugunthan V N2017-04-142-23/+12
| |/ | | | | | | | | | | | | | | | | | | All the clocks which has to be enabled has to be done in enable_basic_clocks(), so moving enable sata clock to common clocks enable function. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-videoTom Rini2017-04-1439-113/+773
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| * video: Fix crash when scroll screeneric.gao@rock-chips.com2017-04-141-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | After enabling log printing to lcd, when the screen starts scrolling, system crashes. Log is shown as bellow: "Synchronous Abort" handler, esr 0x96000045 "Synchronous Abort" handler, esr 0x96000045 Checking the source code, we found that the variable "pixels" gets a wrong value: int pixels = VIDEO_FONT_HEIGHT * vid_priv->line_length; "pixels" here means the value of pixels for a character, rather than the bytes for a character. So the variable "pixels" is 4 times bigger than it's exact value, which will cause the memory overflow when the cpu runs the following code: for (i = 0; i < pixels; i++) *dst++ = clr; <<---- Signed-off-by: Eric Gao <eric.gao@rock-chips.com>
| * at91: video: DT binding for HLCDC driverSongjun Wu2017-04-141-0/+42
| | | | | | | | | | | | DT binding documentation for atmel HLCDC driver. Signed-off-by: Songjun Wu <songjun.wu@microchip.com>
| * at91: video: Support driver-model for the HLCD driverSongjun Wu2017-04-142-71/+417
| | | | | | | | | | | | Add driver-model support to this driver. Signed-off-by: Songjun Wu <songjun.wu@microchip.com>
| * board: toradex: colibri_vf: Add DCU support for Colibri VybridStefan Agner2017-04-149-16/+166
| | | | | | | | | | | | | | | | | | | | | | The Vybrid SoC family has the same display controller unit (DCU) like the LS1021A SoC. This patch adds platform data, pinmux defines and clock control to enable the driver for Toradex Colibri Vybrid module. Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com> Reviewed-by: Stefano Babic <sbabic@denx.de>
| * video: fsl_dcu_fb: add additional modes for DCUStefan Agner2017-04-141-2/+59
| | | | | | | | | | | | | | | | Add common widescreen modes 800x480 and 1024x600. Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com> Reviewed-by: Alison Wang <alison.wang@nxp.com>
| * video: fsl_dcu_fb: Fix DCU_MODE_BLEND_ITER settingStefan Agner2017-04-141-1/+1
| | | | | | | | | | | | | | | | | | DCU_LAYER_MAX_NUM is currently used for DCU_MODE_BLEND_ITER and it actually overflows the maximum value of BLEND_ITER for Vybrid and LS102XA. Fix this by using a default value of 2. Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
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