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* clk: rk3399: Set empty for TCPHY assigned-clocksJagan Teki2020-05-291-0/+2
| | | | | | | | | | | | | | | | Due to v5.7-rc1 sync the SD controller nodes in rk3399.dtsi have SCLK_UPHY0_TCPDCORE, SCLK_UPHY1_TCPDCORE assigned-clocks which are usually required for Linux and don't require to handle them in U-Boot. assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>; assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>; So, mark them as empty in clock otherwise device probe on those typec phy driver would fail. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* clk: rk3399: Enable/Disable the USB2PHY clkJagan Teki2020-05-291-0/+12
| | | | | | | | | Enable/Disable the USB2PHY clk for rk3399. CLK is clear in enable and set in disable functionality. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* doc: rockchip: Remove list of supported boardsWalter Lozano2020-05-291-68/+4
| | | | | | | | As documentation is being moved to doc/boards/rockchip create a warning message and remove the redundant list of supported boards. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* doc: board: rockchip: Add missing supported boardsWalter Lozano2020-05-291-0/+16
| | | | | | | | | Update the list of supported boards with the information available on doc/README.rockchip. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* doc: board: rockchip: Improve supported board list formatWalter Lozano2020-05-291-34/+34
| | | | | | | | | | | As an additional step to move documentation to doc/boards/rockchip improve format of the supported board list to make it more readable. Additionally, add the configuration files used to build them based on doc/README.rockchip. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* rockchip: enable USB OHCI host for RockPro64Marcin Juszkiewicz2020-05-292-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | U-Boot has video output enabled so time to get keyboard working. => usb reset;usb tree resetting USB... Bus usb@fe380000: USB EHCI 1.00 Bus usb@fe3a0000: USB OHCI 1.0 Bus usb@fe3c0000: USB EHCI 1.00 Bus usb@fe3e0000: USB OHCI 1.0 Bus dwc3: usb maximum-speed not found Register 2000140 NbrPorts 2 Starting the controller USB XHCI 1.10 scanning bus usb@fe380000 for devices... 1 USB Device(s) found scanning bus usb@fe3a0000 for devices... 1 USB Device(s) found scanning bus usb@fe3c0000 for devices... 1 USB Device(s) found scanning bus usb@fe3e0000 for devices... 3 USB Device(s) found scanning bus dwc3 for devices... cannot reset port 1!? 2 USB Device(s) found scanning usb for storage devices... 2 Storage Device(s) found USB device tree: 1 Hub (480 Mb/s, 0mA) u-boot EHCI Host Controller 1 Hub (12 Mb/s, 0mA) U-Boot Root Hub 1 Hub (480 Mb/s, 0mA) u-boot EHCI Host Controller 1 Hub (12 Mb/s, 0mA) | U-Boot Root Hub | +-2 Hub (12 Mb/s, 100mA) | ALCOR Generic USB Hub | +-3 Mass Storage (12 Mb/s, 200mA) Kingston DT 101 G2 001478544887BB3157380157 1 Hub (5 Gb/s, 0mA) | U-Boot XHCI Host Controller | +-2 Mass Storage (5 Gb/s, 76mA) ADATA ADATA USB Flash Drive 1520405012240002 Signed-off-by: Marcin Juszkiewicz <marcin@juszkiewicz.com.pl> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* rk3399: Enable NVMe distro bootcmdMark Kettenis2020-05-291-0/+7
| | | | | | | Include NVME in the list of boot targets if CONFIG_NVME is enabled. Signed-off-by: Mark Kettenis <kettenis@openbsd.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* pci: Make Rockchip PCIe voltage regulators optionalMark Kettenis2020-05-291-13/+20
| | | | | | | | | | | | | | The vpcie*-supply properties are optional and these are absent on boards like the ROCKPro64 and Firefly RK3399 where the voltage is supplied by always-on regulators that are already enabled upon boot. Make these regulators optional and properly check their presence before attempting to enable them. Makes PCIe work on un U-Boot on the boards mentioned above. Signed-off-by: Mark Kettenis <kettenis@openbsd.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Tested-by: Marcin Juszkiewicz <marcin@juszkiewicz.com.pl>
* doc: rockchip: Document eMMC program stepsJagan Teki2020-05-291-2/+30
| | | | | | | | Document eMMC partition creation and program steps for rockchip platforms. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* nanopc-t4: Enable USB GadgetJagan Teki2020-05-291-0/+3
| | | | | | | | | Enable DWC3 core, gadget for nanopc-t4 board. This would help to use fastboot by default. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* arm64: dts: rk3399-nanopi4: Add u-boot,spl-boot-orderJagan Teki2020-05-291-0/+6
| | | | | | | | Add u-boot,spl-boot-order as sdhci and sdmmc for booting from eMMC and SD card. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* clk: rk3399: Fix eMMC get_clk reg offsetJagan Teki2020-05-291-1/+1
| | | | | | | | | | Actual eMMC get_clk register is clksel_con22 instead of clksel_con21. Fix it. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* rockchip: Fix spl mmc boot device ofpathJagan Teki2020-05-295-7/+7
| | | | | | | | | | | | | | | | | | | | | | Linux v5.7-rc1 dts(i) sync has changed the sdmmc node from dwmmc@fe320000 to mmc@fe320000 and this ofpath is being used in rockchip spl bootdevice code. So, update the ofpath with a new node name and prefix "same-as-spl" to missing u-boot,spl-boot-order. Bug log: U-Boot SPL 2020.07-rc2-00256-g9c5fef5774 (May 24 2020 - 20:20:43 +0530) Trying to boot from MMC2 mmc_load_image_raw_sector: mmc block read error Trying to boot from MMC1 mmc_load_image_raw_sector: mmc block read error SPL: failed to boot from all boot devices Fixes: 167efc2c7a46 ("arm64: dts: rk3399: Sync v5.7-rc1 from Linux" Signed-off-by: Suniel Mahesh <sunil@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvellTom Rini2020-05-2716-147/+179
|\ | | | | | | | | | | - Fix SPI boot on ds414 (Ezra) - Fix PHY mode definition on armada-3720-uDPU (Jakov) - Convert CRS305-1G-4S to generic version (Luka)
| * arm: mvebu: Convert CRS305-1G-4S board to CRS3xx-98DX3236Luka Kovacic2020-05-2713-145/+165
| | | | | | | | | | | | | | | | | | | | | | Convert the CRS305-1G-4S board to CRS3xx-98DX3236 to enable easier implementation of new CRS3xx series boards, based on Marvell Prestera 98DX3236. Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr> Reviewed-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Jakov Petrina <jakov.petrina@sartura.hr>
| * arm: mvebu: armada-3720-uDPU: fix PHY mode definition to sgmii-2500Jakov Petrina2020-05-271-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit f49ac7e1c4 switched the default PHY speed to 3.125Gbit to resolve issues with SFP modules. However, U-Boot does not have a "2500base-x" phy-mode. Resolve this by using "sgmii-2500" instead. Signed-off-by: Jakov Petrina <jakov.petrina@sartura.hr> Signed-off-by: Vladimir Vid <vladimir.vid@sartura.hr> Reviewed-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Stefan Roese <sr@denx.de>
| * arm: mvebu: ds414: define CONFIG_SYS_U_BOOT_OFFSEzra Buehler2020-05-271-0/+3
| | | | | | | | | | | | | | | | | | Without CONFIG_SYS_U_BOOT_OFFS set to CONFIG_SYS_SPI_U_BOOT_OFFS, U-Boot will be located at address 0x16000. But, SPL will try to load the payload from 0x24000 causing the boot to hang. Signed-off-by: Ezra Buehler <ezra@easyb.ch> Reviewed-by: Stefan Roese <sr@denx.de>
| * arm: mvebu: ds414: add u-boot,dm-pre-reloc to spi0Ezra Buehler2020-05-271-0/+9
| | | | | | | | | | | | | | | | | | Without this U-Boot-specific property, booting on the Synology DS414 (or DS214+) fails in SPL. The spi0 DT node is not scanned, as a result the SPI flash cannot be found. Signed-off-by: Ezra Buehler <ezra@easyb.ch> Reviewed-by: Stefan Roese <sr@denx.de>
* | Merge https://gitlab.denx.de/u-boot/custodians/u-boot-x86Tom Rini2020-05-2718-678/+3399
|\ \ | |/ |/| | | | | | | - Use device tree for FSP-M and FSP-S configuration on Intel Apollo Lake - Add SMBIOS cbmem entry parsing for coreboot - Various clean-ups to CBFS implementation
| * cbfs: Don't require the CBFS size with cbfs_init_mem()Simon Glass2020-05-273-8/+8
| | | | | | | | | | | | | | | | The size is not actually used since it is present in the header. Drop this parameter. Also tidy up error handling while we are here. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * cbfs: Allow reading a file from a CBFS given its base addrSimon Glass2020-05-272-0/+27
| | | | | | | | | | | | | | | | | | Currently we support reading a file from CBFS given the address of the end of the ROM. Sometimes we only know the start of the CBFS. Add a function to find a file given that. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * cbfs: Change file_cbfs_find_uncached() to return an errorSimon Glass2020-05-272-29/+36
| | | | | | | | | | | | | | | | | | | | | | | | This function currently returns a node pointer so there is no way to know the error code. Also it uses data in BSS which seems unnecessary since the caller might prefer to use a local variable. Update the function and split its body out into a separate function so we can use it later. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * cbfs: Return the error code from file_cbfs_init()Simon Glass2020-05-273-13/+19
| | | | | | | | | | | | | | | | | | We may as well return the error code and use it directly in the command code. CBFS still uses its own error enum which we may be able to remove, but leave it for now. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * cbfs: Record the start address in cbfs_privSimon Glass2020-05-271-13/+31
| | | | | | | | | | | | | | | | | | | | | | The start address of the CBFS is used when scanning for files. It makes sense to put this in our cbfs_priv struct and calculate it when we read the header. Update the code accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * cbfs: Use void * for the position pointersSimon Glass2020-05-271-9/+8
| | | | | | | | | | | | | | | | | | It doesn't make sense to use u8 * as the pointer type for accessing the CBFS since we do not access it as bytes, but via structures. Change it to void *, which allows us to avoid a cast. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * cbfs: Unify the two header loadersSimon Glass2020-05-271-22/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | These two functions have mostly the same code. Pull this out into a common function. Also make this function zero the private data so that callers don't have to do it. Finally, update cbfs_load_header_ptr() to take the base of the ROM as its parameter, which makes more sense than passing the address of the header within the ROM. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * cbfs: Adjust cbfs_load_header_ptr() to use cbfs_privSimon Glass2020-05-271-3/+6
| | | | | | | | | | | | | | | | | | This function is strange at the moment in that it takes a header pointer but then accesses the cbfs_s global. Currently clients have their own priv pointer, so update the function to take that as a parameter instead. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * cbfs: Adjust file_cbfs_load_header() to use cbfs_privSimon Glass2020-05-271-4/+5
| | | | | | | | | | | | | | | | | | This function is strange at the moment in that it takes a header pointer but then accesses the cbfs_s global. Currently clients have their own priv pointer, so update the function to take that as a parameter instead. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * cbfs: Adjust return value of file_cbfs_next_file()Simon Glass2020-05-271-20/+23
| | | | | | | | | | | | | | | | | | | | | | At present this uses a true return to indicate it found a file. Adjust it to use 0 for this, so it is consistent with other functions. Update its callers accordingly and add a check for malloc() failure in file_cbfs_fill_cache(). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * cbfs: Use bool type for whether initialisedSimon Glass2020-05-271-4/+4
| | | | | | | | | | | | | | | | At present this uses an int type. U-Boot now supports bool so use this instead. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * cbfs: Use ulong consistentlySimon Glass2020-05-272-7/+6
| | | | | | | | | | | | | | | | | | U-Boot uses ulong for addresses but there are a few places in this driver that don't use it. Convert this driver over to follow this convention fully. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * cbfs: Rename the result variableSimon Glass2020-05-271-10/+10
| | | | | | | | | | | | | | | | | | At present the result variable in the cbfs_priv is called 'result' as is the local variable in a few functions. Change the latter to 'ret' which is more common in U-Boot and avoids confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * cbfs: drop file_cbfs_result declarationChristian Gmeiner2020-05-271-2/+0
| | | | | | | | | | | | | | | | It is not definded anywhere. Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-by: Heinrich Schuchardt <xypron.gpk@gmx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: coreboot: add SMBIOS cbmem entry parsingChristian Gmeiner2020-05-273-0/+27
| | | | | | | | | | Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: apl: Use devicetree for FSP-S configurationBernhard Messerklinger2020-05-276-387/+1922
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A the moment the FSP-S configuration is a mix of hard coded values and devicetree properties. This patch makes FSP-S full configurable from devicetree by adding binding properties for all FSP-S parameters. Co-developed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> (Tested on coral) Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: apl: Use devicetree for FSP-M configurationBernhard Messerklinger2020-05-277-164/+1244
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A the moment the FSP-M configuration is a mix of hard coded values and devicetree properties. This patch makes FSP-M full configurable from devicetree by adding binding properties for all FSP-M parameters. Co-developed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> (Tested on coral) [sjg: Fix a build error for coral] Signed-off-by: Simon Glass <sjg@chromium.org> [bmeng: Add __maybe_unused to fsp_update_config_from_dtb()] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: apl: Only load VBT if CONFIG_HAVE_VBT is enabledBernhard Messerklinger2020-05-271-21/+25
| | | | | | | | | | | | | | | | | | | | Only load VBT if it's present in the u-boot.rom. Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> (Tested on coral) Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: mtrr: Drop the mask display when changing an mtrrSimon Glass2020-05-271-1/+0
|/ | | | | | | | We don't need to print this information since it is shown when the MTRRs are displayed. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* Merge https://gitlab.denx.de/u-boot/custodians/u-boot-riscvTom Rini2020-05-263-23/+21
|\ | | | | | | | | - sifive: fix palmer's email address. - Move all SMP related SBI calls to SBI_v01.
| * sifive: fix palmer's email addressPragnesh Patel2020-05-261-1/+1
| | | | | | | | | | | | | | | | Fix Palmer's email address Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
| * riscv: Move all SMP related SBI calls to SBI_v01Atish Patra2020-05-262-22/+20
| | | | | | | | | | | | | | | | | | | | | | SMP support for S-mode U-Boot is enabled only if SBI_V01 is enabled. There is no point in supporting SMP related (IPI and fences) SBI calls when SBI_V02 is enabled. Modify all the SMP related SBI calls to be defined only for SBI_V01. Signed-off-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | configs: Resync with savedefconfigTom Rini2020-05-2614-22/+16
|/ | | | | | Rsync all defconfig files using moveconfig.py Signed-off-by: Tom Rini <trini@konsulko.com>
* Prepare v2020.07-rc3Tom Rini2020-05-251-1/+1
| | | | Signed-off-by: Tom Rini <trini@konsulko.com>
* Merge tag 'ti-v2020.07-rc3' of ↵Tom Rini2020-05-2522-39/+455
|\ | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-ti - Enable DM_ETH on omap3_logic board - Enable Caches in SPL for K3 platforms - Enable backup boot mode support for J721E - Update the DDR timings for AM654 EVM - Add automated tests for RX-51
| * arm: mach-k3: Enable dcache in SPLJan Kiszka2020-05-195-0/+40
| | | | | | | | | | | | | | | | | | | | Add support for enabling dcache already in SPL. It accelerates the boot and resolves the risk to run into unaligned 64-bit accesses. Based on original patch by Lokesh Vulta. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Acked-by: Lokesh Vutla <lokeshvutla@ti.com>
| * Nokia RX-51: Add automated test for running RX-51 build in qemuPali Rohár2020-05-195-0/+291
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch contains test/nokia_rx51_test.sh script which automatically download and compile all needed tools in local temporary directory to generate a simple MTD images for booting Maemo kernel image by U-Boot from RAM, eMMC and OneNAND. MTD images are then run in virtual n900 machine provided by qemu-linaro project. This script does not need any special privileges, so it can be run as non-root nobody user. It can be used to check that U-Boot for Nokia N900 is not broken and can be successfully booted in emulator. Script is registered to .azure-pipelines.yml, .gitlab-ci.yml and .travis.yml so it would be automatically run on those CI services. Signed-off-by: Pali Rohár <pali@kernel.org>
| * arm: mach-k3: j721e_init: Add support for backup boot modesAndreas Dannenberg2020-05-193-2/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | When the boot of J721E devices using the primary bootmode (configured via device pins) fails a boot using the configured backup bootmode is attempted. To take advantage of the backup boot mode feature go ahead and add support to the J721E init code to determine whether the ROM code performed the boot using the primary or backup boot mode, and if booted from the backup boot mode, decode the bootmode settings into the appropriate U-Boot mode accordingly so that the boot can proceed. Signed-off-by: Andreas Dannenberg <dannenberg@ti.com> Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
| * ARM: omap3_logic boards: Convert to DM_ETHAdam Ford2020-05-199-23/+63
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With the converstion of SMC911x to DM, this can facilitate the omap3 boards from LogicPD (now called Beacon EmbeddedWorks) to be converted. There isn't a clean solution to doing this in phases, so the boards are all being done together to avoid breaking functionality. Because the GPMC bus hasn't been converted, the -u-boot.dtsi node needs to show the address of the ethernet controller for each board. The board file, which is common betwen the OMAP35 and DM37 SOM LV and Torpedo boards, can remove the manual ethernet initialization, but it still needs to register the address and GPMC configuration for the Ethernet controller which is now being moved around to board_late_init(). Lastly, this patch updates the various config files to add the reference for DM_ETH and remove the SMC address, which is now fetched from the newly created device tree nodes. Signed-off-by: Adam Ford <aford173@gmail.com>
| * ddr: k3-am654: EMIF Tool update to 2.02 for IO optimizations and fixesPraneeth Bajjuri2020-05-191-14/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | EMIF tool for AM65x [1] is now updated from rev 1.98 to 2.02 This update includes * Optimizations in IO configuration. * Fix for byte enablement in GCR registers. * Fixes for PG2.0 including ZQ control. [1]: http://www.ti.com/lit/zip/sprcah7 Acked-by: James Doublesin <doublesin@ti.com> Signed-off-by: Praneeth Bajjuri <praneeth@ti.com>
* | Merge branch '2020-05-25-misc-fixes'Tom Rini2020-05-2532-60/+254
|\ \ | | | | | | | | | | | | | | | | | | - A few minor Kconfig migrations / corrections - DFU doc fixes/improvements - Bugfix for ARMv8, env userspace building, more NULL checks in generic PHY code
generated by cgit (git 2.34.1) at 2024-10-06 09:13:34 +0000