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| * | usb: gadget: ether set wMaxPacketSizeTroy Kisky2013-10-201-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | set wMaxPacketSize for full speed descriptors fs_source_desc, fs_sink_desc to 64. Full-speed bulk endpoint can have a maximum packet size of 8, 16, 32, or 64 bytes, so choice 64. The hs_source_desc, hs_sink_desc, already have their wMaxPacketSize set to 512. That is the only legal value for high speed bulk endpoints. Strictly speaking, this patch is not needed because usb_ep_autoconfig will call ep_matches which will override wMaxPacketSize for BULK endpoints only with the size associated with the endpoint setup by the udc driver. But if you want to rely on this, you may as well combine the full speed descriptor with the high speed descriptor to minimize confusion. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
| * | OMAP5-uevm: USB: Add xHCI host contoller supportDan Murphy2013-10-201-23/+51
| | | | | | | | | | | | | | | | | | | | | Add the call back into the board file for to enable the SMPS10 VBUS regulator. Signed-off-by: Dan Murphy <dmurphy@ti.com>
| * | OMAP5: USB: Add OMAP xHCI file and headerDan Murphy2013-10-203-0/+451
| | | | | | | | | | | | | | | | | | | | | | | | Add the OMAP file for the xHCI Host controller This code will initilialize the proper components within the OMAP5 to enable the xHCI host controller. Signed-off-by: Dan Murphy <dmurphy@ti.com>
| * | ARM: OMAP5: Add registers and defines for USBOTG SSDan Murphy2013-10-204-2/+20
| | | | | | | | | | | | | | | | | | | | | Add the prcm registers and the bit definitions to enable the USB SS port of the OMAP5 device. Signed-off-by: Dan Murphy <dmurphy@ti.com>
| * | ARM: OMAP5: Power: Add new function to turn on SMPS10Dan Murphy2013-10-202-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | Add new functionality to turn on SMPS10 regulator. This supplies the VBUS to devices connected to the USB host ports Signed-off-by: Dan Murphy <dmurphy@ti.com>
| * | exynos: dts: Add USB VBUS GPIOs to the device treeJulius Werner2013-10-202-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds a new samsung,vbus-gpio parameter to the device tree, in preparation of replacing the currently hardcoded VBUS GPIO mechanism in exynos5-dt.c with a device tree controlled solution, just as it already exists in the Linux kernel. Signed-off-by: Julius Werner <jwerner@chromium.org> Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com> Cc: Simon Glass <sjg@chromium.org> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Marek Vasut <marex@denx.de>
| * | exynos: usb: Switch USB VBUS GPIOs to be device tree configuredJulius Werner2013-10-203-19/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some Exynos boards, such as the SMDK5250, control USB port power through a GPIO pin. For now this had been hardcoded in the exynos5-dt board file, but not all boards use the same pin, requiring local changes to support different boards. This patch moves the GPIO initialization into the USB host controller drivers which they belong to, and uses the samsung,vbus-gpio parameter in the device tree to configure it. Signed-off-by: Julius Werner <jwerner@chromium.org> Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com> Cc: Simon Glass <sjg@chromium.org> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Marek Vasut <marex@denx.de>
| * | temp: config: exynos5250: Enable xHCI support for Exynos5Vivek Gautam2013-10-201-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This enables support for xHCI host controller on Exynos5 and further disables EHCI support, to make sure only one host controller is enabled at a time, since right now using two controllers at a time is not possible with current usb core infrastructure. Anyone who wants to enable EHCI support again needs to enable CONFIG_USB_EHCI, CONFIG_USB_EHCI_EXYNOS once again in exynos5-dt config. Signed-off-by: Vikas C Sajjan <vikas.sajjan@samsung.com> Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com> Cc: Julius Werner <jwerner@chromium.org> Cc: Simon Glass <sjg@chromium.org> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Dan Murphy <dmurphy@ti.com> Cc: Marek Vasut <marex@denx.de>
| * | config: arm: exynos5250: Define CONFIG_SYS_CACHELINE_SIZEVivek Gautam2013-10-201-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | XHCI stack driver needs this to align buffers to CacheLine boundary. So define the same to be '64' Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com> Cc: Julius Werner <jwerner@chromium.org> Cc: Simon Glass <sjg@chromium.org> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Dan Murphy <dmurphy@ti.com> Cc: Marek Vasut <marex@denx.de>
| * | exynos5: dts: Add device node for XHCIVivek Gautam2013-10-201-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adding device node for xhci host controller to enable usb 3.0 on exynos5250. Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com> Cc: Julius Werner <jwerner@chromium.org> Cc: Simon Glass <sjg@chromium.org> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Dan Murphy <dmurphy@ti.com> Cc: Marek Vasut <marex@denx.de>
| * | exynos5: dts: Add COMPAT string data for USB 3.0 PHY and XHCIVivek Gautam2013-10-202-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adding required compatible string for xHCI host controller as well as USB 3.0 PHY to enable dt support for usb 3.0 on exynos5. Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com> Cc: Julius Werner <jwerner@chromium.org> Cc: Simon Glass <sjg@chromium.org> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Dan Murphy <dmurphy@ti.com> Cc: Marek Vasut <marex@denx.de>
| * | arm: exynos: Add methods to control power to USB 3.0 PHYVivek Gautam2013-10-202-0/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adding methods to turn on/off power to USB3.0 type PHY as and when required by the controller. Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com> Cc: Julius Werner <jwerner@chromium.org> Cc: Simon Glass <sjg@chromium.org> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Dan Murphy <dmurphy@ti.com> Cc: Marek Vasut <marex@denx.de>
| * | USB: XHCI: Add xHCI host controller support for Exynos5Vivek Gautam2013-10-205-0/+601
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds driver layer for xHCI controller in Samsung's exynos5 soc. This interacts with xHCI host controller stack. Signed-off-by: Vikas C Sajjan <vikas.sajjan@samsung.com> Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com> Cc: Julius Werner <jwerner@chromium.org> Cc: Simon Glass <sjg@chromium.org> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Dan Murphy <dmurphy@ti.com> Cc: Marek Vasut <marex@denx.de>
| * | USB: xHCI: Add stack support for xHCIVivek Gautam2013-10-207-3/+3986
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds stack layer for eXtensible Host Controller Interface which facilitates use of USB 3.0 in host mode. Adapting xHCI host controller driver in linux-kernel by Sarah Sharp to needs in u-boot. Initial porting from Linux kernel version 3.4, with following top commit history of drivers/usb/host/xhci* : cf84055 xHCI: Cleanup isoc transfer ring when TD length mismatch found This adds the basic xHCI host controller driver with bare minimum features: - Control/Bulk transfer support has been added with required infrastructure for necessary xHC data structures. - Stream protocol hasn't been supported yet. - No support for quirky devices has been added. Signed-off-by: Vikas C Sajjan <vikas.sajjan@samsung.com> Signed-off-by: Julius Werner <jwerner@chromium.org> Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com> Cc: Simon Glass <sjg@chromium.org> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Dan Murphy <dmurphy@ti.com> Cc: Marek Vasut <marex@denx.de>
| * | usb: Move 'bmRequestType' USB device request macros from EHCI headerVivek Gautam2013-10-202-16/+19
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | Macros defining bmRequestType field of USB device request, given in table 9.2 USB 2.0 spec, are rather generic macros which can be further used by other Host controller stacks. So moving them to usb_defs header. Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com> Cc: Julius Werner <jwerner@chromium.org> Cc: Simon Glass <sjg@chromium.org> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Dan Murphy <dmurphy@ti.com> Cc: Marek Vasut <marex@denx.de>
* | Merge branch 'master' of git://git.denx.de/u-boot-i2cTom Rini2013-10-1728-308/+1187
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| * | i2c: eliminate warnings in i2c_reloc_fixup functionMasahiro Yamada2013-10-171-7/+5
| | | | | | | | | | | | | | | | | | | | | | | | The prototype of handlers had changed. This commit uses cast with (void *) rather than the handler-specific prototype. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * | README: I2C: Fix indentNobuhiro Iwamatsu2013-10-171-3/+3
| | | | | | | | | | | | Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
| * | i2c: s3c24xx: add hsi2c controller supportNaveen Krishna Ch2013-10-172-51/+616
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for hsi2c controller available on exynos5420. Note: driver currently supports only fast speed mode 100kbps Change-Id: I02555b1dc8f4ac21c50aa5158179768563c92f43 Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com> Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Signed-off-by: R. Chandrasekar <rc.sekar@samsung.com>
| * | exynos: i2c: Change FDT bus setup code to enumerate ports correctlySimon Glass2013-10-172-7/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present the i2c ports are enumerated in a strange way - the fdtdec_find_aliases_for_id() function is used, but then the ID returned is ignored and the ports are renumbered. The effect is the same provided that the device tree has the ports in the same order, or uses aliases, and has no gaps, but it is not correct. Adjust the code to use the function as intended. This will allows device tree aliases to change the device order if required. As a result, the i2c_busses variable is dropped. We can't be sure that there are no 'holes' in the list of buses, so must check the whole array. Note: it seems that non-FDT operation is now broken in this drive and will need to be reinstated for upstream. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/59369 Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
| * | exynos: i2c: Fix i2c driver to handle NACKs properlyNaveen Krishna Ch2013-10-171-124/+90
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Exynos5 i2c driver does not handle NACKs properly. This change: - fixes the NACK processing problem (do not continue transaction if address cycle was NACKed) - eliminates a fair amount of duplicate code Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Simon Glass <sjg@google.com> Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
| * | Fix: nommu I2C adapter relocation errorJens Scharsig (BuS Elektronik)2013-10-171-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | NoMMU systems have a access violation problem with i2c_reloc_fixup. Blame for it is a double relocation of the adapter itself. The i2c_adap_p is already relocated, if i2c_reloc_fixup is called. This patch removes the relocation of i2c_adap_p from i2c_reloc_fixup to fix this. Signed-off-by: Jens Scharsig (BuS Elektronik) <esw@bus-elektronik.de>
| * | i2c: sh_i2c: Avoid using I2C prior to relocationNobuhiro Iwamatsu2013-10-171-2/+8
| | | | | | | | | | | | | | | | | | | | | If user uses the I2C in before the relocation, board of sh and rmobile will not start. This will solve this problem. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
| * | i2c, core: optimze i2c_set_bus_num()Heiko Schocher2013-10-171-8/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | check first, if we are on the bus, we want to enable. If so, return immediately, do not calc max adapter number, nor check other things. Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Lukasz Majewski <l.majewski@samsung.com> Acked-by: Lukasz Majewski <l.majewski@samsung.com>
| * | i2c: Add support for Renesas rcarNobuhiro Iwamatsu2013-10-173-0/+303
| | | | | | | | | | | | | | | | | | | | | This supports i2c controller for Renesas rcar. Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
| * | i2c: Zynq: Support for TI PCA9548 bus multiplexerMichael Burr2013-10-172-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | (Interface is not quite the same as Phillips PCA9547.) Signed-off-by: Michael Burr <michael.burr@logicpd.com> Cc: Heiko Schocher <hs@denx.de> Cc: Michal Simek <monstr@monstr.eu>
| * | i2c: update config using mxc driver to new subsystemtrem2013-10-1715-56/+46
| | | | | | | | | | | | Signed-off-by: Philippe Reynes <tremyfr@yahoo.fr>
| * | i2c: mxc: move to new subsystemtrem2013-10-176-63/+93
| | | | | | | | | | | | Signed-off-by: Philippe Reynes <tremyfr@yahoo.fr>
| * | i2c: fix init on generic boardtrem2013-10-171-0/+4
| |/ | | | | | | | | | | | | | | | | | | | | On generic board, the i2c init initialize only one bus. But the new i2c subsystem allow to manage severals i2c bus. So in the case, instead of initializing a bus, we just set the current i2c bus. The initialization will be done in the i2c command. Signed-off-by: Philippe Reynes <tremyfr@yahoo.fr>
* | PCIe:change the method to get the address of a requested capability in ↵Zhao Qiang2013-10-164-30/+107
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | configuration space. Previously, the address of a requested capability is define like that "#define PCI_DCR 0x78" But, the addresses of capabilities is different with regard to PCIe revs. So this method is not flexible. Now a function to get the address of a requested capability is added and used. It can get the address dynamically by capability ID. The step of this function: 1. Read Status register in PCIe configuration space to confirm that Capabilities List is valid. 2. Find the address of Capabilities Pointer Register. 3. Find the address of requested capability from the first capability. Signed-off-by: Zhao Qiang <B45475@freescale.com>
* | boards/c29xpcie: Update TLB and LAW size for IFC NAND, CPLDPrabhakar Kushwaha2013-10-162-4/+4
| | | | | | | | | | | | | | | | NAND,CPLD AMASK register is programmed for 64K size. so Update TLB & LAW size accordingly. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
* | powerpc/mpc85xx: Add workaround for erratum A006379York Sun2013-10-165-0/+40
| | | | | | | | | | | | | | | | | | | | | | | | Erratum A006379 says CPCHDBCR0 bit field [10:14] has incorrect default value after POR. The workaround is to set this field before enabling CPC to 0x1e. Erratum A006379 applies to T4240 rev 1.0 B4860 rev 1.0, 2.0 Signed-off-by: York Sun <yorksun@freescale.com>
* | powerpc/p1010rdb: add p1010rdb-pb support with updating p1010rdb-paShengzhou Liu2013-10-163-34/+285
| | | | | | | | | | | | | | | | | | | | | | | | - Rename old P1010RDB board as P1010RDB-PA. - Add support for new P1010RDB-PB board. - Some optimization. For more details, see board/freescale/p1010rdb/README. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> [York Sun: fix conflicts in boards.cfg] Acked-by: York Sun <yorksun@freescale.com>
* | board/p1010rdb: add pin mux and sdhc support in any bootShengzhou Liu2013-10-164-33/+107
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since pins multiplexing, SDHC shares signals with IFC, with this patch: To enable SDHC in case of NOR/NAND/SPI boot a) For temporary use case in runtime without reboot system run 'mux sdhc' in u-boot to validate SDHC with invalidating IFC. b) For long-term use case set 'esdhc' in hwconfig and save it. To enable IFC in case of SD boot a) For temporary use case in runtime without reboot system run 'mux ifc' in u-boot to validate IFC with invalidating SDHC. b) For long-term use case set 'ifc' in hwconfig and save it. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
* | powerpc/eeprom: update MAX_NUM_PORTS to adapt non-256-bytes EEPROMShengzhou Liu2013-10-161-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | Some boards use System EEPROM with 128-bytes instead of 256-bytes. Since we regard 256-bytes EEPROM as standard EEPROM with default value for MAX_NUM_PORTS. For those non-256-bytes EEPROM, we can redefine MAX_NUM_PORTS in board-specific file to override the default MAX_NUM_PORTS. This patch doesn't impact on previous existing boards. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
* | powerpc/p1010rdb: remove unused cpld_showShengzhou Liu2013-10-161-35/+0
| | | | | | | | | | | | Function cpld_show() was for debug and not called, so clean it. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
* | powerpc/t1040qds: Add T1040QDS boardPrabhakar Kushwaha2013-10-1615-1/+1622
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | T1040QDS is a high-performance computing evaluation, development and test platform supporting the T1040 QorIQ Power Architecture™ processor. T1040QDS board Overview ----------------------- - Four e5500 cores, each with a private 256 KB L2 cache - 256 KB shared L3 CoreNet platform cache (CPC) - Interconnect CoreNet platform - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support - Data Path Acceleration Architecture (DPAA) incorporating acceleration for the following functions: - Packet parsing, classification, and distribution - Queue management for scheduling, packet sequencing, and congestion management - Cryptography Acceleration - RegEx Pattern Matching Acceleration - IEEE Std 1588 support - Hardware buffer management for buffer allocation and deallocation - Ethernet interfaces - Integrated 8-port Gigabit Ethernet switch - Four 1 Gbps Ethernet controllers - SERDES Connections, 8 lanes supporting: — PCI Express: supporting Gen 1 and Gen 2; — SGMII — QSGMII — SATA 2.0 — Aurora debug with dedicated connectors - DDR Controller 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and Interleaving -IFC/Local Bus - NAND flash: 8-bit, async, up to 2GB. - NOR: 8-bit or 16-bit, non-multiplexed, up to 512MB - GASIC: Simple (minimal) target within Qixis FPGA - PromJET rapid memory download support - Ethernet - Two on-board RGMII 10/100/1G ethernet ports. - PHY #0 remains powered up during deep-sleep - QIXIS System Logic FPGA - Clocks - System and DDR clock (SYSCLK, “DDRCLK”) - SERDES clocks - Power Supplies - Video - DIU supports video at up to 1280x1024x32bpp - USB - Supports two USB 2.0 ports with integrated PHYs — Two type A ports with 5V@1.5A per port. — Second port can be converted to OTG mini-AB - SDHC - SDHC port connects directly to an adapter card slot, featuring: - Supporting SD slots for: SD, SDHC (1x, 4x, 8x) and/or MMC — Supporting eMMC memory devices - SPI - On-board support of 3 different devices and sizes - Other IO - Two Serial ports - ProfiBus port - Four I2C ports Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [York Sun: fix conflict in boards.cfg] Acked-by-by: York Sun <yorksun@freescale.com>
* | powerpc: Fix CamelCase warnings in DDR related codePriyanka Jain2013-10-1638-665/+665
| | | | | | | | | | | | | | | | | | | | | | Some DDR related structures present in fsl_ddr_dimm_params.h, fsl_ddr_sdram.h, ddr_spd.h has various parameters with embedded acronyms capitalized that trigger the CamelCase warning in checkpatch.pl Convert those variable names to smallcase naming convention and modify all files which are using these structures with modified structures. Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
* | powerpc/tool/pbl: fix pbl image compiling processShaohui Xie2013-10-162-9/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previous process of compiling a PBL boot image is: 1: make <board_name_config> 2: make u-boot.pbl for example: make T4240QDS_SDCARD_config make u-boot.pbl Now the process is: 1: make <board_name> for example: make T4240QDS_SDCARD Also, updated README.pblimage. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
* | powerpc/B4860: enable PBL tool for B4860Shaohui Xie2013-10-163-0/+36
| | | | | | | | | | | | | | | | Use a default RCW of protocol 0x2A_0x98, and a PBI configure file which uses CPC1 as 512KB SRAM, then PBL tool can be used on B4860 to build a pbl boot image. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
* | powerpc/t4240: updated rcw_cfg to align with default hardware configurationShaohui Xie2013-10-161-4/+4
| | | | | | | | | | | | | | | | | | Default configuration has been changed, the most important one is DDR ref_clock which is changed from 66.67MHz to 133.33MHz. so the ratio need to change from 24x to 12x to keep the DDR frequency. There are also some other optimise to align with default configuration. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
* | powerpc/usb: Mention usb1 before usb2 inside default hwconfig stringramneek mehresh2013-10-161-2/+2
| | | | | | | | | | | | | | | | For USB device-tree fix-up to work properly, its necessary to mention USB1 options before that of USB2 inside default hwconfig string Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
* | board/bsc9131rdb: Update IFC timings for NAND flashPrabhakar Kushwaha2013-10-161-8/+8
| | | | | | | | | | | | | | | | | | Current IFC timings for NAND flash are not able to support existing K9F1G08U0B and new K9F1G08U0D flash. so Update the timings to support both. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
* | powerpc: p1_p2_rdb_pc: add TPL for p1_p2_rdb_pc nand bootYing Zhang2013-10-164-105/+84
| | | | | | | | | | | | Enable TPL for p1_p2_rdb_pc nand boot. Signed-off-by: Ying Zhang <b40530@freescale.com>
* | powerpc : p1_p2_rdb_pc : Enable p1_p2_rdb_pc to start from eSPI with SPLYing Zhang2013-10-162-7/+38
| | | | | | | | | | | | Enable p1_p2_rdb_pc to start from eSPI with SPL. Signed-off-by: Ying Zhang <b40530@freescale.com>
* | powerpc: p1_p2_rdb_pc: Enable p1_p2_rdb_pc to boot from SD Card with SPLYing Zhang2013-10-164-26/+155
| | | | | | | | | | | | Enable p1_p2_rdb_pc to start from eSDHC with SPL. Signed-off-by: Ying Zhang <b40530@freescale.com>
* | SGMII:fix PHY addresses for QSGMII Riser Card working in SGMII modeZhao Qiang2013-10-168-0/+140
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix PHY addresses for QSGMII Riser Card working in SGMII mode on board P3041/P5020/P4080/P5040/B4860. QSGMII Riser Card can work in SGMII mode, but having the different PHY addresses. So the following steps should be done: 1. Confirm whether QSGMII Riser Card is used. 2. If yes, set the proper PHY address. Generally, the function is_qsgmii_riser_card() is for step 1, and set_sgmii_phy() for step 2. However, there are still some special situations, take P5040 and B4860 as examples, the PHY addresses need to be changed when serdes protocol is changed, so it is necessary to confirm the protocol before setting PHY addresses. Signed-off-by: Zhao Qiang <B45475@freescale.com>
* | Corenet/p5040/SGMII:fix the problem for SGMII5/6Zhao Qiang2013-10-161-4/+18
| | | | | | | | | | | | | | | | | | | | | | SGMII5/6 and SGMII7/8 are not on the same slot on P5040 according to the serdes protocol. So it is not proper to organize SGMII5/6 and SGMII7/8 on one bus and SGMII5/6 can't work. So a new bus SUPER_HYDRA_FM3_SGMII_MDIO is added for SGMII5/6 Signed-off-by: Zhao Qiang <B45475@freescale.com>
* | powerpc/mpc85xx:Avoid fix clk groups for Cluster & HW acceleratorPrabhakar Kushwaha2013-10-163-60/+89
| | | | | | | | | | | | | | | | | | | | | | CHASSIS2 architecture never fix clock groups for Cluster and hardware accelerator like PME, FMA. These are SoC defined. SoC defines :- - NUM of PLLs present in the system - Clusters and their Clock group - hardware accelerator and their clock group if no clock group, then platform clock divider for FMAN, PME Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
* | powerpc/mpc85xx:Update processor defines for T1040Prabhakar Kushwaha2013-10-161-8/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | T1040 SoC has - DDR controller ver 5.0 - 2 PLLs - 8 IFC Chip select - FMAN Muram 192K - No Srio - Sec controller ver 5.0 - Max CPU update for its personalities So, update the defines accordingly. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
generated by cgit (git 2.34.1) at 2024-09-30 20:34:26 +0000