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* x86: Add a simple TPL implementationSimon Glass2019-05-086-13/+183
| | | | | | | | Add the required CPU code so that TPL builds correctly. Also update the SPL code to deal with being booted from TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add a way to jump from TPL to SPLSimon Glass2019-05-081-0/+13
| | | | | | | | When TPL finishes it needs to jump to SPL with the stack set up correctly. Add a function to handle this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: samus: Increase the pre-reloc memory againSimon Glass2019-05-081-1/+1
| | | | | | | This is again too small, so increase it slightly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: broadwell: Update PCH to work in TPLSimon Glass2019-05-081-3/+9
| | | | | | | | The early init should only happen once. Update the probe method to deal with TPL, SPL and U-Boot proper. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Enable the RTC on all boardsSimon Glass2019-05-082-1/+1
| | | | | | | | With the move to Kconfig this option should be set in Kconfig, not in the config header file. Move it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Fix device-tree indentationSimon Glass2019-05-081-74/+73
| | | | | | | | With the use of a phandle we can outdent the device tree nodes a little. Fix this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Update device tree for Chromium OS verified bootSimon Glass2019-05-081-2/+15
| | | | | | | | | | | The standard image generated by U-Boot on x86 is u-boot.rom. Add a separate image called image.bin for verified boot. This supports verification in TPL of which SPL/U-Boot to start, then jumping to the correct one, with SPL setting up the SDRAM and U-Boot proper providing the user interface if needed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Update device tree for TPLSimon Glass2019-05-081-2/+32
| | | | | | | | | Add TPL binaries to the device x86 binman desciption. When enabled, TPL will start first, doing the 16-bit init, then jump to SPL and finally U-Boot proper. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add documentation on the samus flashmapSimon Glass2019-05-081-0/+16
| | | | | | | | | | | | There are quite a few variables which control where things appear in the final ROM image. Add a flashmap in the documentation to make this easier to figure out. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed "x86: Update the memory map a little" in] [bmeng: fixed typo of 'documentation' in the commit title] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Support PCI VGA ROM when TPL is usedSimon Glass2019-05-081-1/+1
| | | | | | | | | When TPL is in use, U-Boot proper should support initing the VGA ROM even though the 32-bit init portion is in SPL. Update the condition to handle this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Don't generate a bootstage report in SPLSimon Glass2019-05-081-1/+1
| | | | | | | | This report is normally generated by U-Boot proper. Correct the condition here so that it respects the Kconfig options for bootstage. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Don't set up MTRRs in SPLSimon Glass2019-05-081-1/+4
| | | | | | | | The MTRRs are normally set up in U-Boot proper, so avoid setting them up in SPL as well. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Support TPL in Intel common codeSimon Glass2019-05-081-3/+6
| | | | | | | | Update the Makefie rules to ensure that the correct files are built when TPL is being used. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: sysreset: Implement the get_last() methodSimon Glass2019-05-081-0/+6
| | | | | | | | | Add a default implementation of this method which always indicates that the last reset was a power-on reset. This is the most likely type of reset and without a PCH-specific driver we cannot determine any other type. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: sysreset: Implement power-off if availableSimon Glass2019-05-081-1/+78
| | | | | | | | On modern x86 devices we can power the system off using the power- management features of the PCH. Add an implementation for this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: sysreset: Separate out the EFI codeSimon Glass2019-05-081-5/+11
| | | | | | | | | | | | | | The EFI implementation of reset sits inside the driver and is called directly from outside the driver, breaking the normal driver-model conventions. Worse, it passed NULL as the device pointer, hoping that the called function won't use it, which breaks as soon as code is added to use it. Separate out the implementation to improve the situation enough to allow a future patch to add new sysreset features. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: broadwell: Implement PCH_REQ_PMBASE_INFOSimon Glass2019-05-081-0/+25
| | | | | | | Implement this ioctl() to support power off. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Implement PCH_REQ_PMBASE_INFOSimon Glass2019-05-081-0/+15
| | | | | | | Implement this ioctl() to support power off. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: pch: Add an ioctl to read power-management infoSimon Glass2019-05-081-0/+18
| | | | | | | | Add a new ioctl() request to read information about the power-management system. This can be used to power off the device. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: mrccache: Add more debuggingSimon Glass2019-05-081-4/+12
| | | | | | | | When the MRC cache fails to save it is useful to have some debugging info to indicate what when wrong. Add some more debug() calls. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Support saving MRC data from SPLSimon Glass2019-05-082-9/+38
| | | | | | | | | When SPL is used to set up the memory controller we want to save the MRC data in SPL to avoid needing to pass it up to U-Boot proper to save. Add a function to handle that. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add common Intel code for SPLSimon Glass2019-05-082-0/+33
| | | | | | | | Add an implementation of arch_cpu_init_f() so that the x86 SPL code builds and identifies the CPU. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: broadwell: Select refcode and CPU code for SPLSimon Glass2019-05-081-3/+4
| | | | | | | Allow broadwell to build for SPL and include the reference code. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: broadwell: Allow booting from SPLSimon Glass2019-05-082-0/+78
| | | | | | | | | At present broadwell only supports booting straight into U-Boot proper. Add a separate init file to boot from SPL into U-Boot proper, and select it when SPL is in use. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Allow 16-bit init to be in TPLSimon Glass2019-05-085-5/+14
| | | | | | | | At present we support having 16-bit init be in SPL or U-Boot proper, but not TPL. Add support for this so that TPL can boot. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add support for starting from SPL/TPLSimon Glass2019-05-084-1/+146
| | | | | | | | | | | When a previous phase of U-Boot has run we need to adjust the init of subsequent states to avoid messing up the CPU state. Add a new version of the start logic for SPL, when it boots from TPL (start_from tpl.c) and a new version for U-Boot when it boots from SPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: broadwell: Split CPU initSimon Glass2019-05-083-673/+695
| | | | | | | | | Split the CPU init into two parts - the 'full' init which happens in the first U-Boot phase, and the rest of the init that happens on subsequent stages. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: broadwell: Move init of debug UART to cpu.cSimon Glass2019-05-082-11/+13
| | | | | | | | | | | At present the debug UART is set up in sdram.c which is not the best place since it has nothing in particular to do with SDRAM. Since we want to support initing this in SPL too, move it to a common file. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: added 'broadwell' tag in the commit title] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* x86: broadwell: Allow SDRAM init from SPLSimon Glass2019-05-083-94/+101
| | | | | | | | | | | | | At present, for broadwell, SDRAM is always set up in U-Boot proper since the 64-bit mode (which uses SDRAM init in SPL) is not supported. Update the code to allow SDRAM init in SPL instead so that U-Boot proper can be loaded into SDRAM and run from there. This allows U-Boot to be compressed to reduce space, since it is not necessary to run it directly from flash. It could later allow us to support 64-bit U-Boot on broadwell. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: broadwell: Improve SDRAM debugging outputSimon Glass2019-05-081-12/+20
| | | | | | | | Add debugging during SDRAM init so that problems are easier to diagnose. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add a handoff header fileSimon Glass2019-05-081-0/+15
| | | | | | | | Add an arch-specific handoff header so that we can use the HANDOFF feature on x86 devices. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Support booting with TPLSimon Glass2019-05-081-1/+8
| | | | | | | | | | | Some boards want to use TPL as the first phase of U-Boot. This allows selection of A or B SPL phases, thus allowing the memory init to be upgraded in the field. Add a new Kconfig option for this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Support SPL and TPLSimon Glass2019-05-082-1/+31
| | | | | | | | | | | At present only chromebook_link64 supports SPL. It is useful to eb able to support both TPL and SPL to implement verified boot on x86. Enable the options for both along with some suitable default options needed to boot through these phases. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: dts: Add device-tree labels for rtc and resetSimon Glass2019-05-082-2/+2
| | | | | | | Add labels for these nodes so that board DT files can reference them. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add a way to reinit the cpuSimon Glass2019-05-083-44/+94
| | | | | | | | | We cannot init the CPU fully both than once during a boot. Add a new function which can be called to figure out the CPU identity, but which does not change anything. For x86_64, this is empty for now. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: mp_init: Use proper error numbersSimon Glass2019-05-081-5/+5
| | | | | | | | At present many of the functions in this file return -1 as an error number. which is -EPERM. Update the code to use real error numbers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Update a stale comment about ifdtoolSimon Glass2019-05-082-2/+2
| | | | | | | | We use binman to build the x86 image now. Update a comment which still refers to ifdtool. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: start64: Fix copyright messageSimon Glass2019-05-081-1/+1
| | | | | | | There is a typo in this header. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS"Simon Glass2019-05-081-5/+1
| | | | | | | | | | | | | | | | | | | | | | This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* cros_ec: Use a hyphen in the uclass nameSimon Glass2019-05-081-1/+1
| | | | | | | | | | | | | | | | Device-tree rules require that aliases use a hyphen rather than a underscore. Update the uclass name to fit with this. This allows device-tree aliases to be used to refer to cros-ec devices, for example: aliases { cros-ec0 = &ec; cros-ec1 = &pd; }; Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* spl: Allow sandbox to build a device-tree fileSimon Glass2019-05-081-1/+13
| | | | | | | | | | | | | | | | | | | | | | | At present only OF_SEPARATE is considered valid for building a device-tree file in SPL. However sandbox uses OF_HOSTFILE instead. Update the logic to handle this and make it easier to understand. Note that the new logic is not quite the same as the old logic. It was previously assumed that checking for: $(CONFIG_$(SPL_TPL_)OF_CONTROL) $(CONFIG_OF_SEPARATE) $(CONFIG_$(SPL_TPL_)OF_PLATDATA) producing 'yy' meant that the first two were 'y' and the last was empty. Strictly speaking it would be possible for any two of the three to be 'y' and still yield the same result. However, that was not the intention of the new logic, since OF_PLATDATA always ensures that no device-tree file is included. So in effect the new logic is the same, with the addition of OF_HOSTFILE as an option for OP_SEPARATE. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: core: Fix translate condition in ofnode_get_addr_size()Simon Glass2019-05-081-1/+1
| | | | | | | Update the condition to translate only if this is enabled for SPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* binman: Allow sections to have an offsetSimon Glass2019-05-085-5/+67
| | | | | | | | | At present sections are always placed automatically. Even if an 'offset' property is provided it is ignored. Update the logic to support an offset for sections. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* binman: Add a missing comment in Entry_vblockSimon Glass2019-05-081-0/+1
| | | | | | | | An important property is missing. Update the entry comment to include this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* binman: Don't show image-skip message by defaultSimon Glass2019-05-082-9/+21
| | | | | | | | | | | | This message is not very important since it is simply indicating that the user's instructions are being followed. Only show it when the verbosity level is above the default. Also drop the unnecessary extra newline on this message, which causes two line breaks. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* binman: Don't generate an error in 'text' entry constructorSimon Glass2019-05-081-2/+2
| | | | | | | | | | | It is not good practice to raise an exception in a constructor. In this case the 'text' entry may not actually be used, if -i is used to filter out the images that get built. Move the exception to where the data is actually used. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* Merge branch 'master' of git://git.denx.de/u-boot-shTom Rini2019-05-0758-2164/+1860
|\ | | | | | | | | - RZ/A1 addition. - Old board removal.
| * ARM: dts: renesas: Add RZ/A1 GR-Peach boardChris Brandt2019-05-0711-0/+513
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add board code and DTs for Renesas RZ/A1 SoC-based GR-Peach, which is a cheap development platform with RZ/A1H SoC. The DTs are imported from Linux 5.0.11, commit d5a2675b207d . Currently supported are UART, ethernet and RPC SPI. The board can be booted from RPC SPI by writing the u-boot.bin binary to the beginning of the SPI NOR, e.g. using the "sf" command. The board can also be booted via JTAG by setting text base to 0x20020000, loading u-boot.bin there via JTAG and executing it from that address. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * ARM: dts: renesas: Add RZ/A1 platform codeChris Brandt2019-05-078-1/+871
| | | | | | | | | | | | | | | | | | | | | | | | Add platform code and DTs for Renesas RZ/A1 R7S72100 SoC. Distinguishing feature of this SoC is that it has up to 10 MiB of on-SoC static RAM (SRAM). The DTs are imported from Linux 5.0.11, commit d5a2675b207d . Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * spi: rpc: Add support for operation without clock frameworkMarek Vasut2019-05-072-5/+9
| | | | | | | | | | | | | | | | | | | | | | Add ifdeffery to allow operation without the clock framework enabled. This is required on RZ/A1, as it does not have clock driver yet. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Jagan Teki <jagan@amarulasolutions.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
generated by cgit (git 2.34.1) at 2024-10-06 16:20:18 +0000