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* phy: Wire return value from phy_config()Michal Simek2016-05-242-5/+2
| | | | | | Fix zynq_gem driver to handle error from phy_config correctly. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* image: Add boot_get_fpga() to load fpga with bootmMichal Simek2016-05-245-2/+110
| | | | | | | | | | Add function boot_get_fpga() which find and load bitstream to programmable logic if fpga entry is present. Function is supported on Xilinx devices for full and partial bitstreams in BIN and BIT format. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Remove additional blankline in image.h
* net: phy: Handle phy_startup() error codes properlyMichal Simek2016-05-2411-56/+115
| | | | | | | Propagate error code from genphy_update_link() to phy startup(). Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Stephen Warren <swarren@nvidia.com>
* phy: Return correct error code when timeout happensMichal Simek2016-05-242-3/+3
| | | | | | | Return -ETIMEDOUT if timeout happens. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Stephen Warren <swarren@nvidia.com>
* net: xilinx: Handle error value from phy_startup()Michal Simek2016-05-242-3/+8
| | | | | | | Handle error returned by phy_startup() properly. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Stephen Warren <swarren@nvidia.com>
* mkimage: Report information about fpgaMichal Simek2016-05-245-1/+78
| | | | | | | | Add FIT_FPGA_PROP that user can identify an optional entry for fpga. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* fpga: Fix typo in function commentMichal Simek2016-05-241-1/+1
| | | | | | Trivial patch. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* ARM64: zynqmp: Enable CLK frameworkMichal Simek2016-05-246-0/+12
| | | | | | | ZynqMP is using fixed clocks now that's why enabling it to be available for drivers. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* ARM64: zynqmp: Add SPL support supportMichal Simek2016-05-247-3/+209
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Support RAM and MMC boot mode in SPL also with SPL_FIT images. In MMC boot mode two boot options are available: 1) Boot flow with ATF(EL3) and full U-Boot(EL2): aarch64-linux-gnu-objcopy -O binary bl31.elf bl31.bin mkimage -A arm64 -O linux -T kernel -C none -a 0xfffe5000 -e 0xfffe5000 -d bl31.bin atf.ub cp spl/boot.bin <sdcard fat partition> cp atf.ub <sdcard fat partition> cp u-boot.bin <sdcard fat partition> 2) Boot flow with full U-Boot(EL3): cp spl/boot.bin <sdcard> cp u-boot*.img <sdcard> 3) emmc boot mode dd if=/dev/zero of=sd.img bs=1024 count=1024 parted sd.img mktable msdos parted sd.img mkpart p fat32 0% 100% kpartx -a sd.img mkfs.vfat /dev/mapper/loop0p1 mount /dev/mapper/loop0p1 /mnt/ cp spl/boot.bin /mnt cp u-boot.img /mnt cp u-boot.bin /mnt cp atf.ub /mnt umount /dev/mapper/loop0p1 kpartx -d sd.img cp sd.img /tftpboot/ and program it via u-boot tftpb 10000 sd.img mmcinfo mmc write 10000 0 $filesize mmc rescan mmc part ls mmc 0 psu_init() function contains low level SoC setup generated for every HW design by Xilinx design tools. xil_io.h is only supporting file to fix all dependencies from tools. The same solution was used on Xilinx Zynq. The patch also change CONFIG_SYS_INIT_SP_ADDR to the end of OCM which stays at the same location all the time. Bootrom expects starting address to be at 0xfffc0000 that's why this address is SPL_TEXT_BASE. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* ARM64: zynqmp: Add missing u-boot,dm-pre-reloc to DTSIMichal Simek2016-05-241-0/+5
| | | | | | Add missing u-boot,dm-pre-reloc to get IPs initialized. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* ARM64: zynqmp: Align gic ranges for 64k in device treeAlexander Graf2016-05-241-2/+2
| | | | | | | | | | | | | The GIC ranges in the zynqmp device tree are only 4kb aligned. Since commit 12e14066f we automatically deal with aliases GIC regions though, so we can map them transparently into guests even on 64kb page size systems. This patch makes use of that features and sets GICC and GICV to 64kb aligned and sized regions. Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* tools: zynqmpimage: Add Xilinx ZynqMP boot header generationMichal Simek2016-05-245-1/+280
| | | | | | | | | | Add support for the zynqmpimage to mkimage. Only basic functionality is supported without encryption and register initialization with one partition which is filled by U-Boot SPL. For more detail information look at Xilinx ZynqMP TRM. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* SPL: FIT: Enable SPL_FIT_LOAD in RAM based boot modeMichal Simek2016-05-241-9/+36
| | | | | | | | | | Support loading FIT in SPL for RAM bootmode. CONFIG_SPL_LOAD_FIT_ADRESS points to address where FIT image is stored in memory. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: zynq: Call ps7_post_config() for SPLMichal Simek2016-05-241-0/+15
| | | | | | | If ps7_post_config() is defined call it. It is enabling for example level shifters for PL bitstreams. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* ARM64: zynqmp: Enable option to overwrite default variablesMichal Simek2016-05-241-0/+2
| | | | | | Enable overwriting variables out of main config file. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* spl: Introduce new function spl_board_prepare_for_bootMichal Simek2016-05-242-0/+7
| | | | | | | | | Call this function before passing control from SPL. For fpga case it is necessary to enable for example level shifters when bitstream is programmed. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* ARM64: zynqmp: Add debug uart for zc1751-dc1Michal Simek2016-05-241-0/+5
| | | | | | It is helpful for debugging. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* ARM64: zynqmp: Enable SPI_FLASH and FLASH_BAR for ep108Michal Simek2016-05-241-0/+2
| | | | | | Add missing SPI flash options. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* ARM64: zynqmp: Remove CONFIG_PREBOOTMichal Simek2016-05-241-1/+0
| | | | | | | CONFIG_PREBOOT variable is breaking ./test/py framework. Remove it. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* ARM: zynq: Add support for SPL_LOAD_FITMichal Simek2016-05-241-0/+10
| | | | | | Enable minimal function to be able to compile SPL_LOAD_FIT. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* ARM64: zynqmp: Wire up debug_uart setupMichal Simek2016-05-243-0/+15
| | | | | | It has to be enabled by debug_uart_init(). Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* ARM64: zynqmp: Enable eMMC boot partitions commandsMichal Simek2016-05-241-0/+1
| | | | | | Enable some additional features of the eMMC boot partitions. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* ARM64: zynqmp: Add support for reading MAC from eepromMichal Simek2016-05-242-0/+23
| | | | | | | | | | | | | | | | | | | | | | Add support for on board eeprom with programmed MAC for using in u-boot to have uniq address for every board. Most of the time uniq MAC address is on a label on the board. If address is not programmed use these command to program it. On zcu102: ZynqMP> mm.b 0 00000000: 00 ? 00 00000001: a0 ? 0a 00000002: 35 ? 35 00000003: 02 ? 02 00000004: 00 ? ef 00000005: 00 ? 67 00000006: 00 ? q i2c dev 5 i2c write 0 54 20 6 i2c md 54 20 Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* ARM64: zynqmp: Enable missing distro default optionsMichal Simek2016-05-241-0/+14
| | | | | | Enable all options which distros requires. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* ARM64: zynqmp: Enable HUSH parser for all zynqmp targetsMichal Simek2016-05-245-0/+5
| | | | | | Enable HUSH for all zynqmp boards which don't have it. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* ARM: dts: zynq: describe SLCR as simple-mfd rather than simple-busMasahiro Yamada2016-05-241-1/+1
| | | | | | | | | | | | | | | Commit 9f56917ab88a ("dm: core: make simple-bus compatible to simple-mfd") made possible to import the following commit: Linux commit: bc5ba9b98435bf76d92e0954da1784695aa449f1 The SLCR (System-Level Control Registers) block is an MFD (Multi Function Device) rather than a bus. "simple-mfd" seems a more suitable compatible string than "simple-bus". Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* gpio: zynq: Add support for reading gpio pin stateMichal Simek2016-05-241-0/+22
| | | | | | | Add zynq_gpio_get_function() which return status on gpio pin. This function enables gpio status command. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* ARM: zynq: load u-boot.img whether CONFIG_OF_SEPARATE is defined or notMasahiro Yamada2016-05-241-5/+1
| | | | | | | | | Since commit ad1ecd2063da ("fdt: Build a U-Boot binary without device tree"), u-boot-dtb.img is identical to u-boot.img, so SPL can always load u-boot.img whether CONFIG_OF_SEPARATE is defined or not. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* Merge branch 'master' of git://git.denx.de/u-boot-mipsTom Rini2016-05-2379-67/+6448
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| * malta: Support MIPS32r6 configurationsPaul Burton2016-05-211-0/+1
| | | | | | | | | | | | | | | | Both real Malta boards & QEMU's Malta emulation can feature MIPS32r6 CPUs. Allow building U-Boot for such systems by selecting CONFIG_SUPPORTS_CPU_MIPS32_R6 for Malta. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * malta: Remove ".set mips32" directivePaul Burton2016-05-211-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | We always build for a mips32 or higher ISA, so this ".set mips32" directive is redundant. Once MIPSr6 support is added it will become harmful since some instruction encodings change & this directive will cause the older encodings to be incorrectly emitted instead of the appropriate ones for the build. In preparation for supporting MIPSr6, remove this redundant directive. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * MIPS: Support for targetting MIPSr6Paul Burton2016-05-212-6/+30
| | | | | | | | | | | | | | | | | | | | | | Add support for targetting MIPS32r6 & MIPS64r6 systems, in the same way that we currently select release 1 or release 2 targets. MIPSr6 is not entirely backwards compatible with earlier releases of the architecture. Some instructions are encoded differently, some are removed, some are reused, so it is not practical to run U-Boot built for earlier revisions on a MIPSr6 system. Update their Kconfig help text to reflect that. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * MIPS: Simplify CONFIG_SYS_CPU valuesPaul Burton2016-05-211-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | Rather than having the values for CONFIG_SYS_CPU depend upon each architecture revision, have them depend upon the more general CONFIG_CPU_MIPS32 & CONFIG_CPU_MIPS64 which in turn depend upon the architecture revisions. This is done in preparation for adding MIPSr6 support, which would otherwise need to introduce new cases here. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * MIPS: Use unchecked immediate addition/subtractionPaul Burton2016-05-212-11/+13
| | | | | | | | | | | | | | | | | | | | | | | | In MIPS assembly there have historically been 2 variants of immediate addition - the standard "addi" which traps if an overflow occurs, and the unchecked "addiu" which does not trap on overflow. In release 6 of the MIPS architecture the trapping variants of immediate addition & subtraction have been removed. In preparation for supporting MIPSr6, stop using the trapping instructions from assembly & switch to their unchecked variants. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * mips: ath79: Add support for TPLink WDR4300Marek Vasut2016-05-219-0/+295
| | | | | | | | | | | | | | | | | | | | Add support for the TPLink WDR4300 router, which is based on the AR9344 MIPS 74Kc CPU and has 128 MiB of RAM. The USB is supported on this system as well. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Wills Wang <wills.wang@live.com>
| * mips: ath79: Add AR934x supportMarek Vasut2016-05-219-1/+683
| | | | | | | | | | | | | | | | | | | | Add support for the Atheros AR934x WiSoCs. This patchs adds complete system init, including PLL and DRAM init, both of which happen from full C environment, since the AR934x has proper SRAM. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Wills Wang <wills.wang@live.com>
| * mips: ath79: Add support for ungating ethernet on ar933x and ar934xMarek Vasut2016-05-213-0/+80
| | | | | | | | | | | | | | | | Add code to ungate the ethernet controller on ar933x and ar934x . Signed-off-by: Marek Vasut <marex@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Wills Wang <wills.wang@live.com>
| * mips: ath79: dts: Add ethernet MAC nodes for ar933xMarek Vasut2016-05-211-0/+26
| | | | | | | | | | | | | | | | | | Add node for both ethernet controllers in the ar933x. The PHY is attached only to the first ethernet controller. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Wills Wang <wills.wang@live.com>
| * mips: ath79: Add support for ungating USB on ar933x and ar934xMarek Vasut2016-05-212-0/+61
| | | | | | | | | | | | | | | | Add code to ungate the USB controller on ar933x and ar934x . Signed-off-by: Marek Vasut <marex@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Wills Wang <wills.wang@live.com>
| * mips: ath79: dts: Add generic-ehci nodeMarek Vasut2016-05-211-0/+7
| | | | | | | | | | | | | | | | Add generic EHCI node for the ChipIdea EHCI controller in the ath79. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Wills Wang <wills.wang@live.com>
| * mips: ath79: Fix compiler warning on const assignmentMarek Vasut2016-05-211-1/+1
| | | | | | | | | | | | | | | | | | The assignment const T var; var = value; is illegal, since var is constant. Drop the const to fix the compiler warning. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Wills Wang <wills.wang@live.com>
| * mips: ath79: Fix ar71xx_regs.h indentMarek Vasut2016-05-211-1034/+1069
| | | | | | | | | | | | | | | | | | The indent in this file triggers my OCD, so fix it. Replace multiple spaces with tabs and align the values in one column. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Wills Wang <wills.wang@live.com>
| * mips: Add MIPS 74Kc tuneMarek Vasut2016-05-212-0/+4
| | | | | | | | | | | | | | | | | | | | Add MIPS 74Kc tune Kconfig option. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Wills Wang <wills.wang@live.com> [added missing tune-y entry in arch/mips/Makefile] Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * mips: Fix compiler warning in cpu.cMarek Vasut2016-05-211-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There really is zero reason for including netdev.h in generic mips CPU code. Removing the netdev.h from cpu.c also fixes the following compiler warning: In file included from arch/mips/cpu/cpu.c:10:0: include/netdev.h:204:41: warning: 'struct eth_device' declared inside parameter list [enabled by default] int fecmxc_register_mii_postcall(struct eth_device *dev, int (*cb)(int)); ^ include/netdev.h:204:41: warning: its scope is only this definition or declaration, which is probably not what you want [enabled by default] Signed-off-by: Marek Vasut <marex@denx.de> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * ath79: add readonly attribute for ath79_soc_descWills Wang2016-05-211-4/+4
| | | | | | | | | | | | use 'const' keywork to qualify readonly attribute for lookup-table member Signed-off-by: Wills Wang <wills.wang@live.com>
| * ath79: ar933x: use BIT macro for bit shift operationWills Wang2016-05-211-7/+7
| | | | | | | | | | | | used a uniform BIT macro for register bit-field shift Signed-off-by: Wills Wang <wills.wang@live.com>
| * ar933x: serial: Remove the explicit pinctrl settingWills Wang2016-05-211-14/+2
| | | | | | | | | | | | | | The correct pinctrl is handled automatically so we don't need to do it in the driver. Signed-off-by: Wills Wang <wills.wang@live.com>
| * ath79: spi: Remove the explicit pinctrl settingWills Wang2016-05-211-12/+0
| | | | | | | | | | | | | | The correct pinctrl is handled automatically so we don't need to do it in the driver. Signed-off-by: Wills Wang <wills.wang@live.com>
| * mips: Report reloc information in bdinfoTim Chick2016-05-211-0/+2
| | | | | | | | Signed-off-by: Tim Chick <tim.chick@mediatek.com>
| * drivers: mtd: add Microchip PIC32 internal non-CFI flash driver.Purna Chandra Mandal2016-05-213-0/+452
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PIC32 internal flash devices are parallel NOR flash divided into number of banks to allow erase-programming in one while fetch and execution continues on other. As the flash banks are memory mapped stored code can be executed directly from flash (XIP), also there is additional hardware logic to prefetch and cache contents to improve execution performance. These flash can also be used to store user data (like environment). Flash erase and programming are handled by on-chip NVM controller. Driver implemented driver model but MTD is not really support. Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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