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* arm: meson: remove static ethernet memory power domain enableNeil Armstrong2021-04-062-6/+0
| | | | | | | The ethernet memory power domain is handled by the meson-ee-pwrc driver, delete the static code. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* net: designware: remove amlogic compatiblesNeil Armstrong2021-04-061-3/+0
| | | | | | These compatibles are now handled by the dwmac_meson8b glue driver. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* configs: meson: use Designware glue driver for Amlogic Meson8b & later SoCsNeil Armstrong2021-04-0623-23/+23
| | | | | | Use the proper Synopsys DWMAC Meson8b glue to handle the ethernet link type. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* arm: meson: remove static MDIO mux handlingNeil Armstrong2021-04-062-45/+2
| | | | | | The static MDIO mux handling in mach-meson is no more needed, delete it. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* configs: update Amlogic Meson G12A, G12B & SM1 configs for MDIO MUXNeil Armstrong2021-04-069-6/+27
| | | | | | Use DM_MDIO and the new G12A MDIO MUX driver for G12A, G12B & SM1 boards. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* configs: update Amlogic Meson GXL & GXM config for MDIO MUXNeil Armstrong2021-04-069-10/+27
| | | | | | Use DM_MDIO and the new MMIOREG MDIO MUX driver for GXL & GXM board. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* net: designware: add Amlogic Meson8b & later glue driverNeil Armstrong2021-04-063-0/+159
| | | | | | | | | | | | | This adds a proper glue driver for the Designware DWMAC ethernet MAC IP found in the Amlogic Meson8, GXBB, GXL, GXM, G12A, G12B & SM1 SoCs. This is aimed to replace the static ethernet link setup found on the board init code for the Amlogic SoC based boards. Tested on a libretech-cc (S905x Internal RMII 10/100 PHY) and Khadas VIM3 (A113d with external 10/100/1000 RGMII PHY) to cover the most extreme setups. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* net: add Amlogic Meson G12A MDIO MUX driverNeil Armstrong2021-04-063-0/+157
| | | | | | | | | | The Amlogic G12A & compatible SoCs embeds a mux to either communicate with the external PHY or the internal 10/100 PHY. This adds support for this mux as a MDIO MUX device. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
* net: designware: add DM_MDIO supportNeil Armstrong2021-04-061-1/+92
| | | | | | | | | Add support for DM_MDIO to connect to PHY and expose a MDIO device for the internal MDIO bus in order to dynamically connect to MDIO PHYs with DT with eventual MDIO muxes in between. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
* net: add MMIO Register MDIO MUX driverNeil Armstrong2021-04-063-0/+137
| | | | | | | Add support for MMIO register MDIO muxes based on the Linux mdio-mux-mmioreg driver. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
* Merge branch 'next'Tom Rini2021-04-05659-4548/+22451
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| * Merge tag 'xilinx-for-v2021.07' of ↵Tom Rini2021-03-3135-434/+4637
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://source.denx.de/u-boot/custodians/u-boot-microblaze into next Xilinx changes for v2021.07 net: - Fix gem PCS support spi: - Small trivial fixes zynq: - Enable time/timer commands - Update bitmain platform - Several DT changes zynqmp: - Update clock driver - mini config alignments - Add/update psu_init for zcu208/zcu216/zc1275 - Several DT changes - Enable efi debug command (also for Versal)
| | * xilinx: Enable efi debug commandMichal Simek2021-03-302-0/+2
| | | | | | | | | | | | | | | | | | | | | Enable EFI debug command to be able to setup various efi variables to avoid software like grub. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| | * ARM: bitmain: Enable saving variables to SD cardMichal Simek2021-03-301-0/+1
| | | | | | | | | | | | | | | | | | | | | Board has NAND and SD interfaces which can be used for saving variables too. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| | * ARM: bitmain: Enable legacy u-boot formatMichal Simek2021-03-301-0/+1
| | | | | | | | | | | | | | | | | | Still legacy formats are used that's why enable them by default. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| | * ARM: bitmain: Enable nand and smcc driversMichal Simek2021-03-301-0/+8
| | | | | | | | | | | | | | | | | | Enable nand and smcc via DT. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| | * spi: xilinx_spi: Trivial fixes in axi qspi driverT Karthik Reddy2021-03-301-5/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | Use __func__ instead for function name in debug. Use Linux style u32 instead of uint32_t. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Acked-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| | * xilinx: Sync DTs with Linux kernelMichal Simek2021-03-3019-255/+498
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are several changes which happen in mainline kernel which should get also to U-Boot. Here is the list of patches from the kernel: - ARM: zynq: Fix leds subnode name for zc702/zybo-z7 - arm64: dts: zynqmp: Fix leds subnode name for zcu100/ultra96 v1 - arm64: dts: zynqmp: Fix u48 si5382 chip on zcu111 - arm64: dts: zynqmp: Wire up the DisplayPort subsystem - arm64: dts: zynqmp: Add DisplayPort subsystem - arm64: dts: zynqmp: Add DPDMA node - arm64: dts: zynqmp: Enable phy driver for Sata on zcu102/zcu104/zcu106 - arm64: dts: zynqmp: Enable si5341 driver for zcu102/106/111 - arm64: dts: zynqmp: Add DT description for si5328 for zcu102/zcu106 - arm64: dts: zynqmp-zcu100-revC: correct interrupt flags - arm64: dts: xilinx: align GPIO hog names with dtschema - arm64: zynqmp: Add Xilinx AES node - dt: bindings: dma: xilinx: dpdma: DT bindings for Xilinx DPDMA but also some other changes have been done. - Using only one compatible string for adxl345 on zturn - Remove Xilinx internal DP bindings - Remove USB3.0 serdes configurations - Remove SATA serdes configuration for zc1232 - Resort nvmem_firmware - Update nand compatible string - Aling power-domains property for sd0/1 Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| | * clk: zynqmp: Fix clk dump valuesT Karthik Reddy2021-03-301-81/+170
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With "clk dump" command, few clocks are showing up incorrect values and some clocks are displayed as "unknown". Add missing clocks to zynqmp clock driver to display proper clocks rates. Implement a simple way to get clock source, instead of calling functions. Change existing functions to this simple mechanism. Fix gem clock name "gem_rx" to "gem_tx" which was incorrect. Change dbf_fpd & dbf_lpd clk names to dbg_fpd & dbg_lpd. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
| | * arm64: zynqmp: Rename clocks as per the Arasan NAND driverAmit Kumar Mahapatra2021-03-301-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | In zynqmp.dtsi file renamed "clk_sys" clock to "controller" and "clk_flash" clock to "bus" as per upstreamed Arasan NAND driver. This fixes NAND driver probe failure. Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| | * arm64: zynqmp: Update device tree properties for nand flashAmit Kumar Mahapatra2021-03-301-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update the following device tree properties for nand flash - Set software ecc mode. - Set bch as ecc algo. - Set read block to 0. Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| | * arm64: zynqmp: Update psu_init for zcu1275Michal Simek2021-03-301-82/+148
| | | | | | | | | | | | | | | | | | Update clock/pll setup, ddr, MIOs based on 2020.2 hw design. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| | * arm64: zynqmp: Add idt 8a34001 chip to zcu208/zcu216Michal Simek2021-03-302-2/+8
| | | | | | | | | | | | | | | | | | There is Linux driver for these chips that's why add it to device tree. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| | * arm64: zynqmp: Add missing psu inits for zcu208/216Michal Simek2021-03-302-0/+3762
| | | | | | | | | | | | | | | | | | Add missing configurations file for zcu208 and zcu216. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| | * arm64: zynqmp: Add emmc specific parametersAshok Reddy Soma2021-03-302-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | EMMC will have bus-width 8 and it is non-removable in general. These are missing from dt node. Add bus-width and non-removable parameters to emmc node. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| | * arm64: zynqmp: Increase size of malloc poolAshok Reddy Soma2021-03-302-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | size of malloc() pool for use before relocation is not sufficient for ZynqMP mini u-boot with emmc configuration. Increase it to 4K. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| | * xilinx: zynq: Enable time and timer commandsAshok Reddy Soma2021-03-301-0/+2
| | | | | | | | | | | | | | | | | | | | | Enable time command to get the elapsed time and timer commands. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| | * net: gem: Fix setting PCS auto-negotiation stateRobert Hancock2021-03-301-8/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The code was trying to disable PCS auto-negotiation when a fixed-link node is present and enable it otherwise. However, the PCS registers were being written before the PCSSEL bit was set in the network configuration register, and it appears that in this state, PCS register writes are ignored. The result is that the intended change only took effect on the second network operation that was performed, since at that time PCSSEL is already enabled. Fix the order of register writes so that PCS registers are only written to after the PCS is enabled. Fixes: 26e62cc971 ("net: gem: Disable PCS autonegotiation in case of fixed-link") Signed-off-by: Robert Hancock <robert.hancock@calian.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Reviewed-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | Merge tag 'u-boot-atmel-2021.07-a' of ↵Tom Rini2021-03-304-14/+36
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://source.denx.de/u-boot/custodians/u-boot-atmel into next First set of u-boot-atmel features for 2021.07 cycle: This small feature set includes the implementation of the slew rate for the PIO4 pin controller device, and a fix for arm926ejs-based microprocessors that avoids a crash.
| | * | ARM: mach-at91: arm926ejs: fix data abort in startup returning from ↵Martin Townsend2021-03-221-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | lowlevel_init The startup code in arm/cpu/arm926ejs preserves the link register across the call to lowlevel_init by using r4: mov r4, lr /* perserve link reg across call */ bl lowlevel_init /* go setup pll,mux,memory */ mov lr, r4 /* restore link */ The lowlevel_init function for at91 machines based on the same CPU uses r4 and hence corrupts it causing a data abort when it returns to the startup code. This patch fixes this by using r6 instead of r4 in the lowlevel_init function. Discovered and the fix was tested on a AT91SAM9261 based board. Signed-off-by: Martin Townsend <martin@rufilla.com> Reviewed-by: Eugen Hristev <eugen.hristev@microchip.com>
| | * | pinctrl: at91-pio4: add support for slew-rateClaudiu Beznea2021-03-022-3/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SAMA7G5 supports slew rate configuration. Adapt the driver for this. For switching frequencies lower than 50MHz the slew rate needs to be enabled. Since most of the pins on SAMA7G5 fall into this category enabled the slew rate by default. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
| | * | dt-bindings: pinctrl: at91-pio4: add slew-rateClaudiu Beznea2021-03-021-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | Document slew-rate DT binding for SAMA7G5. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
| * | | Merge tag 'v2021.04-rc5' into nextTom Rini2021-03-2945-619/+712
| |\ \ \ | | | |/ | | |/| | | | | Prepare v2021.04-rc5
| * | | Merge tag 'dm-pull-28mar21' of git://git.denx.de/u-boot-dm into nextTom Rini2021-03-28126-812/+3133
| |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | binman support for expanding entries, connections misc fixes and improvements to sandbox, etc. x86 CBFS improvements x86 coreboot improvements
| | * | | sandbox: define __dyn_sym_start, dyn_sym_endHeinrich Schuchardt2021-03-271-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On RISC-V the symbols __dyn_sym_start, dyn_sym_end are referenced in efi_runtime_relocate(). Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
| | * | | spi: spi-uclass: Add support to manually relocate spi memory opsT Karthik Reddy2021-03-271-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add spi memory operations to relocate manually when CONFIG_NEEDS_MANUAL_RELOC is enabled. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Acked-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
| | * | | dtoc: Add new check that offsets are correctSimon Glass2021-03-272-3/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a few more internal checks to make sure offsets are correct, before updating the dtb. To make this easier, update the functions which add a property to return that property,. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * | | dtoc: Support adding subnodes alongside existing onesSimon Glass2021-03-272-9/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | So far we have only needed to add subnodes to empty notds, so have not had to deal with ordering. However this feature is needed for binman's expanded nodes, since there may be another node in the same section. While libfdt adds new properties after existing properties, it adds new subnodes before existing subnodes. This means that we must reorder the nodes in the cached version, so that the ordering remains consistent. Update the sync implementation to sync existing subnodes first, then add new ones, then tidy up the ordering in the cached version. Update the test to cover this behaviour. Also improve the comment about property syncing while we are here. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * | | dtoc: Add a subnode test for multiple nodesSimon Glass2021-03-272-12/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a new test that adds a subnode alongside an existing one, as well as adding properties to a subnode. This will expand to adding multiple subnodes in future patches. Put a node after the one we are adding to so we can check that things sync correctly. The testAddNode() test should be in the TestNode class since it is a node test, so move it. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * | | dtoc: Tweak ordering of fdt-offsets refreshingSimon Glass2021-03-271-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Once the tree has been synced, thus potentially moving things around in the fdt, we set _cached_offsets to False so that a refresh will happen next time a property is accessed. This 'lazy' refresh doesn't really save much time, since refresh is a very fast operation, just a single walk of the tree. Also, having the refresh happen in the bowels of property access it makes it harder to figure out what is going on. Simplify the code by always doing a refresh before and after a sync. Set _cached_offsets to True immediately after this, in the Refresh() function, since this makes more sense than doing it in the caller. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * | | dtoc: Tidy up property-offset handlingSimon Glass2021-03-271-3/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If a property does not yet have an offset, then that means it exists in the cache'd fdt but has not yet been synced back to the flat tree. Use the dirty flag for this so we don't need to check the offset too. Improve the comments for Prop and Node to make it clear what an offset of None means. Also clear the dirty flag after the property is synced. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * | | dtoc: Improve internal error for Refresh()Simon Glass2021-03-272-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the node name too so it is easy to see which node failed. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * | | binman: Support default alignment for sectionsSimon Glass2021-03-278-0/+58
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Sometimes it is useful to specify the default alignment for all entries in a section, such as when word-alignment is necessary, for example. It is tedious and error-prone to specify this individually for each section. Add a property to control this for a section. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * | | binman: Support obtaining section contents immediatelySimon Glass2021-03-276-19/+95
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Generally the content of sections is not built until the final assembly of the image. This is partly to avoid wasting time, since the entries within sections may change multiple times as binman works through its various stages. This works quite well since sections exist in a strict hierarchy, so they can be processed in a depth-first manner. However the 'collection' entry type does not have this luxury. If it contains a section within its 'content' list, then it must produce the section contents, if available. That section is typically a sibling node, i.e. not part oc the collection's hierarchy. Add a new 'required' argument to section.GetData() to support this. When required is True, any referenced sections are immediately built. If this is not possible (because one of the subentries does not have its data yet) then an error is produced. The test for this uses a 'collection' entry type, referencing a section as its first member. This forces a call to _BuildSectionData() with required set to False, at first, then True later, when the image is assembled. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * | | binman: Add support for a collection of entriesSimon Glass2021-03-276-14/+128
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The vblock entry type includes code to collect the data from a number of other entries (not necessarily subentries) and concatenating it. This is a useful feature for other entry types. Make it a base class, so that vblock can use it, along with other entry types. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * | | binman: Allow disabling expanding an entrySimon Glass2021-03-278-9/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present there is a command-line flag to disable substitution of expanded entries. Add an option to the entry node as well, so it can be controlled at the node level. Add a test to cover this. Fix up the comment to the checkSymbols() function it uses, while we are here. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * | | binman: Use a unique number for the symbols test fileSimon Glass2021-03-272-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Two test devicetree files currently have 192 as their unique number. Fix this by separating them out. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * | | x86: coral: Show memory config and SKU ID on startupSimon Glass2021-03-274-14/+179
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Provide the model information through sysinfo so that it shows up on boot. For memconfig 4 pins are provided, for 16 combinations. For SKU ID there are two options: - two pins provided in a ternary arrangement, for 9 combinations. - reading from the EC Add a binding doc and drop the unused #defines as well. Example: U-Boot 2021.01-rc5 CPU: Intel(R) Celeron(R) CPU N3450 @ 1.10GHz DRAM: 3.9 GiB MMC: sdmmc@1b,0: 1, emmc@1c,0: 2 Video: 1024x768x32 @ b0000000 Model: Google Coral (memconfig 5, SKU 3) This depends on the GPIO series: http://patchwork.ozlabs.org/project/uboot/list/?series=228126 Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Bin Meng <bmeng.cn@gmail.com>
| | * | | sysinfo: Allow showing model info from sysinfoSimon Glass2021-03-272-8/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some boards may want to show the SKU ID or other information obtained at runtime. Allow this to come from sysinfo. The board can then provide a sysinfo driver to provide it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| | * | | sandbox: Correct uninit conflictSimon Glass2021-03-271-5/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It is not possible to remove the state before driver model is uninited, since the devices are allocated in the memory buffer. Also it is not possible to uninit driver model afterwards, since the RAM has been freed. Drop the uninit altogether, since it is not actually necessary. Signed-off-by: Simon Glass <sjg@chromium.org>
generated by cgit (git 2.34.1) at 2024-11-19 21:48:29 +0000