| Commit message (Collapse) | Author | Age | Files | Lines |
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When there is no command line, we cannot enable this feature. Add a check
to avoid a build error.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Add an extra condition here since we cannot put x86 tables in a bloblist
when bloblists are not supported.
Signed-off-by: Simon Glass <sjg@chromium.org>
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The U_BOOT_CMDREP_COMPLETE() macro produces a build error if CONFIG_CMDLINE
is not enabled. Fix this by updating the macro to provide the 'repeatable'
arugment in this case.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Move this documentation over to reST. Move the example files into a files/
directory so they are still separate.
Do a few minor updates while we are here:
- Tidy up sandbox build instructions
- Update my github account name
- Add some talks and links
Signed-off-by: Simon Glass <sjg@chromium.org>
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Export this function always so it can be used behind IS_ENABLED() instead
of requiring an #ifdef.
Signed-off-by: Simon Glass <sjg@chromium.org>
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The _SUPPORT suffix is from an earlier time and interferes with use of
the CONFIG_IS_ENABLED() macro. Rename the option to drop the suffix.
Tidy up the TODO that prompted this.
Signed-off-by: Simon Glass <sjg@chromium.org>
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This feature was dropped from U-Boot some time ago:
f12f96cfaf5 (sf: Drop spl_flash_get_sw_write_prot")
However, we do need a way to see if a flash device is write-protected,
since if it is, it may not be possible to write to do (i.e. failing to
write is expected).
I am not sure of the correct layer to implement this, so this patch is a
stab at it. If spi-flash makes sense then I will add to the 'sf' also.
Re the points mentioned in the removal commit:
1) This kind of requirement can be achieved using existing
flash operations and flash locking API calls instead of
making a separate flash API.
Which uclass is this?
2) Technically there is no real hardware user for this API to
use in the source tree.
I do want coral (at least) to support this.
3) Having a flash operations API for simple register read bits
also make difficult to extend the flash operations.
This new patch only mentions write-protect being on or off, rather than
the actual mechanism.
4) Instead of touching generic code, it is possible to have
this functionality inside spinor operations in the form of
flash hooks or fixups for associated flash chips.
That sounds to me like what drivers are for. But we still need some sort
of API for it to be accessible.
Signed-off-by: Simon Glass <sjg@chromium.org>
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At present bootstage silently ignores new records if it runs out of
space. It is sometimes obvious by looking at the report, but the IDs are
not contiguous, so it is easy to miss.
Aad a message so that action can be taken.
Signed-off-by: Simon Glass <sjg@chromium.org>
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We have two separate places that need to figure out the bootstage ID to
use. Put this code in a function so that the logic is in one place.
Signed-off-by: Simon Glass <sjg@chromium.org>
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This change seems important enough to warrant a visible message. Change
the log_debug() to log_info().
Signed-off-by: Simon Glass <sjg@chromium.org>
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These tests current produce unwanted output on sandbox. Use the correct
functions to controller console output, to avoid this.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Sandbox is special in that it is used for testing and it does not match
any particular target architecture. Allow it to load an image from any
architecture, so that 'bootm' can be used as needed.
Signed-off-by: Simon Glass <sjg@chromium.org>
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At present when a file is bound to a host device it is always marked as
removeable. Arguably the device is removeable, since it can be unbound at
will. However while it is bound, it is not considered removable by the
user. Also it is useful to be able to model both fixed and removeable
devices for code that distinguishes them.
Add a -r flag to the 'host bind' command and plumb it through to provide
this feature.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Remove the 'bind' subcommand before processing the arguments. This will
make it easier to add an optional flag.
Signed-off-by: Simon Glass <sjg@chromium.org>
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This function has a strange mix of declarations and argument parsing
which is a bit hard to follow and harder to modify. Separate out the
declarations at the start of the function and adjust the ordering of
the code slightly.
Signed-off-by: Simon Glass <sjg@chromium.org>
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This can crash if the EC has not yet been probed. Add a check to prevent
this.
Signed-off-by: Simon Glass <sjg@chromium.org>
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At present sandbox removes its executable after failing to run it,
since there is no other way that it would get cleaned up.
However, this is actually only wanted if the image was created within
sandbox. For the case where the image was generated by the build system,
such as u-boot-spl, we don't want to delete it.
Handle the two code paths accordingly.
Signed-off-by: Simon Glass <sjg@chromium.org>
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This function only exists if CPU is enabled. Update the code to take
account of this, so that it does not have to be enabled on all sandbox
builds.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
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This currently hangs and it is not necessary in any case. Drop the code
when booting from coreboot.
Signed-off-by: Simon Glass <sjg@chromium.org>
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When booting from coreboot there is no need to notify the FSP of anything,
since coreboot has already done it. Nor it is possible, since the FSP
details are not provided by coreboot.
Skip it in this case.
Signed-off-by: Simon Glass <sjg@chromium.org>
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When booting from coreboot the FSP video information is no-longer
available. Enable the coreboot driver so that we can get some sort of
display in this case.
Signed-off-by: Simon Glass <sjg@chromium.org>
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At present the debug UART is only set up in SPL, on the assumption that
the boot flow will always pass through there. When booting from coreboot,
SPL is not used, so the debug UART is not available.
Move the code into a common place so that it can be used in U-Boot proper
also. Add the required init to start_from_spl.S as well.
Signed-off-by: Simon Glass <sjg@chromium.org>
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When CONFIG_ACPIGEN is not enabled the CPU code does not build. Fix this
by moving things around.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Allow referencing a CBFS file in the flashmap, so that it is possible to
boot from coreboot, where files are not available from binman.
Signed-off-by: Simon Glass <sjg@chromium.org>
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This driver cannot work when booted from coreboot, since the FSP
information is not available. Disable it in that case, so that the
coreboot video driver can be used instead.
Signed-off-by: Simon Glass <sjg@chromium.org>
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When booting from coreboot we need this driver for the video to work.
Update the driver to be usable on any board.
The driver disables itself if it sees that is not booted from coreboot.
Signed-off-by: Simon Glass <sjg@chromium.org>
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The copy buffer, if enabled, prevents booting from coreboot correctly,
since no memory is allocated for it. Allow it to fall back to disabled
in this situation. This ensures that a console is displayed, even if
it is slow.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Two commands are missing this check, so compilation fails when building
without CONFIG_CMDLINE. Add it.
Signed-off-by: Simon Glass <sjg@chromium.org>
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This information is interesting to look at and can be important for
debugging and inspection. Add a command to display it in a helpful
format.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Move this code into a generic location so that it can be used by other x86
boards which want to boot from coreboot. Also ensure that this is called
if booting from coreboot.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Quite a few new tag types have been added over the years. Bring these into
U-Boot so that all required tags can be parsed.
Add a proper comment to struct sysinfo_t while we are here, since many of
the meanings are not obvious.
Signed-off-by: Simon Glass <sjg@chromium.org>
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It is useful to be able to parse coreboot tables on any x86 build which is
booted from coreboot. Add a new Kconfig option to enable this feature and
move the code so it can be used on any board, if enabled.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Add new timestamp codes that are present in coreboot, so that we can decode
these in U-Boot.
At present TS_U_BOOT_START_KERNEL is used twice. It should only be used
just before jumping to Linux, so update the other call site to use
TS_START_KERNEL.
Signed-off-by: Simon Glass <sjg@chromium.org>
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This all relates to the sysinfo structure provided by coreboot. Put the
timestamp definitions into the same file as the others. Tidy up a few
comments at the same time.
Signed-off-by: Simon Glass <sjg@chromium.org>
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It is possible to boot U-Boot for chromebook_coral either 'bare metal' or
from coreboot. In the latter case we want to provide access to the coreboot
sysinfo tables. Move the definitions into a file available to any x86
board.
Signed-off-by: Simon Glass <sjg@chromium.org>
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The results of malloc() are a void * and so this cast is unnecessary. Drop
it.
Signed-off-by: Simon Glass <sjg@chromium.org>
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CBFS now supports compressed filed. Add support for reading this
information so that the correct decompression can be applied. The
decompression itself is not implemented in CBFS.
Signed-off-by: Simon Glass <sjg@chromium.org>
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In file_cbfs_next_file() there is a lot of complicated code to move to
the next file. Use the ALIGN() macros to simplify this.
Signed-off-by: Simon Glass <sjg@chromium.org>
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The file_cbfs_next_file() function is already fairly long. Before
expanding it further, move the core part into a separate function.
Signed-off-by: Simon Glass <sjg@chromium.org>
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The file traversal functions currently use a single global CBFS. In some
cases we need to access multiple CBFSs to obtain different files. Add new
functions to support this.
Signed-off-by: Simon Glass <sjg@chromium.org>
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In some cases CBFS does not start with a header but is just a collection
of files. It is possible to support this so long as the size of the CBFS
is provided.
Update the cbfs_init_mem() function to support this.
Signed-off-by: Simon Glass <sjg@chromium.org>
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When U-Boot is booted from coreboot the SMBIOS tables are written by
coreboot, not U-Boot. The existing method of updating the BIOS version
string does not work in that case, since gd->smbios_version is only set
when U-Boot writes the tables.
Add a new function which allows the version to be updated by parsing the
tables and writing the string in the correct place. Since coreboot
provides a pointer to the SMBIOS tables in its sysinfo structure, this
makes it easy to do the update.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Rename this variable since there is no need to distinguish it from an old
node.
Signed-off-by: Simon Glass <sjg@chromium.org>
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CBFS now supports attributes for things that cannot fit in the header as
originally conceived. Add the structures for these.
Also rename attributes_offset to something shorter, to ease code
readability.
Signed-off-by: Simon Glass <sjg@chromium.org>
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The driver currently reads the card-detect but does not register it with
the MMC stack. Update this so that card-detect works as expected.
Signed-off-by: Simon Glass <sjg@chromium.org>
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We should not enable debugging by default. Drop this.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Since the recent bug fix, it doesn't matter which GPIO phandle is used so
long as the GPIO number is right. Still, we may as well use the correct
one to avoid confusion.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
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At present the eMMC device does not have an alias so it appears after
the SD card which is device 1. There is no device 0 which is odd.
Make the eMMC device be the first one. Update the boot script to use the
new device.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
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The Intel GPIO binding allows GPIOs to be globally numbered, so that it
does not matter which GPIO bank is specified in the device tree. This is
convenient and avoid confusion since the banks do not have the same number
of GPIOs and the numbering is not sequential.
The GPIO uclass ensures that the device mentioned in the devicetree
binding is probed. It is fine for the driver to update gpio_desc to point
to a different driver, but this may not have been probed. If it has not
been, then it cannot be claimed since there is no uclass data.
We could handle this in the GPIO uclass but so far it is an unusual
situation so it is probably not worth the extra code. Handle this case in
the GPIO driver by probing the selected device if necessary.
Signed-off-by: Simon Glass <sjg@chromium.org>
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We should not enable debugging by default. Drop this.
Signed-off-by: Simon Glass <sjg@chromium.org>
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