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* video: backlight: fix pwm's duty cycle calculationDario Binacchi2020-10-182-7/+7
| | | | | | | | For levels equal to the maximum value, the duty cycle must be equal to the period. Signed-off-by: Dario Binacchi <dariobin@libero.it> Reviewed-by: Simon Glass <sjg@chromium.org>
* video: backlight: fix pwm data structure descriptionDario Binacchi2020-10-181-1/+1
| | | | | | | The description of the 'max_level' field was incorrectly assigned to the 'min_level' field. Signed-off-by: Dario Binacchi <dariobin@libero.it>
* video: dw-mipi-dsi: permit configuring the escape clock rateNeil Armstrong2020-10-182-4/+17
| | | | | | | | | | | | The Amlogic D-PHY in the Amlogic AXG SoC Family does support a frequency higher than 10MHz for the TX Escape Clock, thus make the target rate configurable. This is based on the Linux commit [1] and adapted to the U-Boot driver. [1] a328ca7e4af3 ("drm/bridge: dw-mipi-dsi: permit configuring the escape clock rate") Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* video: dw-mipi-dsi: driver-specific configuration of phy timingsNeil Armstrong2020-10-182-6/+27
| | | | | | | | | | | | | | | | The timing values for dw-dsi are often dependent on the used display and according to Philippe Cornu will most likely also depend on the used phy technology in the soc-specific implementation. To solve this and allow specific implementations to define them as needed add a new get_timing callback to phy_ops and call this from the dphy_timing function to retrieve the necessary values for the specific mode. This is based on the Linux commit [1] and adapted to the U-Boot driver. [1] 25ed8aeb9c39 ("drm/bridge/synopsys: dsi: driver-specific configuration of phy timings") Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* test: Fix sandbox tests failing to buildSean Anderson2020-10-172-2/+2
| | | | | | | | syslog_test.h is in test/log/, not include/ Fixes: 52d3df7fef ("log: Allow LOG_DEBUG to always enable log output") Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvellTom Rini2020-10-168-7/+93
|\ | | | | | | | | | | - Fix Octeon SPI driver for Octeon TX2 - Fix and enhance Octeon watchdog driver - Misc minor enhancements to Octeon TX/TX2
| * arm: octeontx: Add CMD_WDTStefan Roese2020-10-164-0/+4
| | | | | | | | | | | | | | | | | | Enable WDT command for Octeon TX/TX2 boards. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Aaron Williams <awilliams@marvell.com> Cc: Suneel Garapati <sgarapati@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com>
| * watchdog: octeontx_wdt: Add support for start and stopSuneel Garapati2020-10-161-5/+83
| | | | | | | | | | | | | | | | | | | | | | | | This patch enhances the Octeon TX/TX2 watchdog driver to fully enable the WDT. With this changes, the "wdt" command is now also supported on these platforms. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de> Cc: Aaron Williams <awilliams@marvell.com> Cc: Suneel Garapati <sgarapati@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com>
| * arm: octeontx: Select CLKStefan Roese2020-10-161-0/+2
| | | | | | | | | | | | | | | | | | | | Clock support is needed for all Octeon TX/TX2 boards. This patch selects CONFIG_CLK so that it is available. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Aaron Williams <awilliams@marvell.com> Cc: Suneel Garapati <sgarapati@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com>
| * mmc: octeontx_hsmmc.c: Remove test debug messageStefan Roese2020-10-161-1/+0
| | | | | | | | | | | | | | | | | | | | Remove a left-over debug test message from the Octeon TX / TX2 MMC driver. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Aaron Williams <awilliams@marvell.com> Cc: Suneel Garapati <sgarapati@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com>
| * spi: octeon_spi: Use a fixed 100MHz input clock on Octeon TX2Stefan Roese2020-10-161-1/+4
| | | | | | | | | | | | | | | | | | | | | | Octeon TX2 sets the TB100_EN bit in the config register. We need to use a fixed 100MHz clock for this as well to work properly. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Aaron Williams <awilliams@marvell.com> Cc: Suneel Garapati <sgarapati@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com> Cc: Jagan Teki <jagan@amarulasolutions.com>
* | Merge branch '2020-10-15-further-cleanup_dev_xxx'Tom Rini2020-10-1626-94/+74
|\ \ | |/ |/| | | - Bring in the next round of dev_xxx cleanup patches.
| * dm: Don't undefine dev_xxx macrosSean Anderson2020-10-161-20/+0
| | | | | | | | | | | | | | | | Now that linux/compat.h does not define these macros, we do not need to undefine them. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * linux/compat.h: Remove redefinition of dev_xxx macrosSean Anderson2020-10-161-28/+0
| | | | | | | | | | | | | | All users of these functions now include dm/device_compat.h directly. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * usb: dwc3: Include device_compat.h in dwc3-octeon-glue.cTom Rini2020-10-161-0/+1
| | | | | | | | | | | | Necessary for dev_xxx. Signed-off-by: Tom Rini <trini@konsulko.com>
| * clk: at91: Include device_compat.h in compat.cTom Rini2020-10-161-0/+1
| | | | | | | | | | | | Necessary for dev_xxx. Signed-off-by: Tom Rini <trini@konsulko.com>
| * arm: fsl-layerscape: Include device_compat.h in soc.cTom Rini2020-10-161-0/+1
| | | | | | | | | | | | Necessary for dev_xxx. Signed-off-by: Tom Rini <trini@konsulko.com>
| * usb: musb-new: mt85xx: Fix not calling dev_err with a deviceSean Anderson2020-10-161-3/+4
| | | | | | | | | | | | | | This driver doesn't use DM (in the correct places), so we use a device and not a udevice. We also need to include device_compat.h Signed-off-by: Sean Anderson <seanga2@gmail.com>
| * usb: musb-new: Include device_compat.hSean Anderson2020-10-165-1/+11
| | | | | | | | | | | | | | This was included, but was ifdef'd out. We also need dm.h for struct udevice. Signed-off-by: Sean Anderson <seanga2@gmail.com>
| * usb: xhci: Include device_compat.hSean Anderson2020-10-162-5/+7
| | | | | | | | | | | | This header is necessary for the dev_xxx macros. Signed-off-by: Sean Anderson <seanga2@gmail.com>
| * timer: Include device_compat.hSean Anderson2020-10-161-2/+3
| | | | | | | | | | | | | | Necessary for dev_xxx. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * tee: optee: Include device_compat.hSean Anderson2020-10-161-0/+1
| | | | | | | | | | | | | | Necessary for dev_xxx. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * spi: fsl_qspi: Include device_compat.hSean Anderson2020-10-161-4/+5
| | | | | | | | | | | | Necessary for dev_xxx. Signed-off-by: Sean Anderson <seanga2@gmail.com>
| * spi: nxp_fspi: Include device_compat.hSean Anderson2020-10-161-3/+4
| | | | | | | | | | | | Necessary for dev_xxx. Signed-off-by: Sean Anderson <seanga2@gmail.com>
| * ram: imxrt: Include device_compat.hSean Anderson2020-10-151-0/+1
| | | | | | | | | | | | Necessary for dev_xxx. Signed-off-by: Sean Anderson <seanga2@gmail.com>
| * phy: Include device_compat.hSean Anderson2020-10-151-1/+1
| | | | | | | | | | | | Necessary for dev_xxx. Signed-off-by: Sean Anderson <seanga2@gmail.com>
| * net: ldpaa_eth: Include device_compat.hSean Anderson2020-10-151-7/+7
| | | | | | | | | | | | Necessary for dev_xxx. Signed-off-by: Sean Anderson <seanga2@gmail.com>
| * mtd: mxs_nand: Fix not calling dev_xxx with a deviceSean Anderson2020-10-151-13/+15
| | | | | | | | | | | | This includes device_compat.h, and fixes several calls to dev_xxx. Signed-off-by: Sean Anderson <seanga2@gmail.com>
| * firmware: scmi: Include device_compat.hSean Anderson2020-10-153-0/+3
| | | | | | | | | | | | | | This header is necessary for the dev_xxx macros. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * dm: syscon: Set LOG_CATEGORYSean Anderson2020-10-151-0/+2
| | | | | | | | | | | | | | We call log_debug, but do not have a category set. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * clk: sifive: Include device_compat.hSean Anderson2020-10-151-7/+7
|/ | | | | | Necessary for dev_xxx. Signed-off-by: Sean Anderson <seanga2@gmail.com>
* Merge tag 'mmc-2020-10-14' of ↵Tom Rini2020-10-1516-237/+556
|\ | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-mmc - fsl_esdhc_imx cleanup - not send cm13 if send_status is 0. - Add reinit API - Add mmc HS400 for fsl_esdhc - Several cleanup for fsl_esdhc - Add ADMA2 for sdhci
| * mmc: fsl_esdhc: add ADMA2 supportMichael Walle2020-10-143-5/+67
| | | | | | | | | | | | | | | | | | | | | | Newer eSDHC controllers support ADMA2 descriptor tables which support 64bit DMA addresses. One notable user of addresses in the upper memory segment is the EFI loader. If support is enabled, but the controller doesn't support ADMA2, we will fall back to SDMA (and thus 32 bit DMA addresses only). Signed-off-by: Michael Walle <michael@walle.cc>
| * mmc: fsl_esdhc: replace most #ifdefs by IS_ENABLED()Michael Walle2020-10-141-73/+65
| | | | | | | | | | | | | | Make the code cleaner and drop the old-style #ifdef constructs where it is possible. Signed-off-by: Michael Walle <michael@walle.cc>
| * mmc: fsl_esdhc_imx: replace all readl/writel to esdhc_read32/esdhc_write32Haibo Chen2020-10-121-32/+32
| | | | | | | | | | | | | | Currently, readl/writel and esdhc_read32/esdhc_write32 are used. To align the usage, change to only use esdhc_read32/esdhc_write32. Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
| * mmc: do not check argument of free() beforehandHeinrich Schuchardt2020-10-121-2/+1
| | | | | | | | | | | | free() checks if its argument in NULL. No need to check it twice. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
| * mmc: sdhci: move the ADMA2 table handling into own moduleMichael Walle2020-10-125-58/+92
| | | | | | | | | | | | | | | | There are other (non-SDHCI) controllers which supports ADMA2 descriptor tables, namely the Freescale eSDHC. Instead of copying the code, move it into an own module. Signed-off-by: Michael Walle <michael@walle.cc>
| * mmc: fsl_esdhc: simplify esdhc_setup_data()Michael Walle2020-10-121-27/+42
| | | | | | | | | | | | | | | | First, we need the waterlevel setting for PIO mode only. Secondy, both DMA setup code is identical for both directions, except for the data pointer. Thus, unify them. Signed-off-by: Michael Walle <michael@walle.cc>
| * mmc: fsl_esdhc: use dma-mapping APIMichael Walle2020-10-121-35/+14
| | | | | | | | | | | | | | Use the dma_{map,unmap}_single() calls. These will take care of the flushing and invalidation of caches. Signed-off-by: Michael Walle <michael@walle.cc>
| * mmc: fsl_esdhc: simplify 64bit check for SDMA transfersMichael Walle2020-10-121-23/+6
| | | | | | | | | | | | | | | | | | | | SDMA can only do DMA with 32 bit addresses. This is true for all architectures (just doesn't apply to 32 bit ones). Simplify the code and remove unnecessary CONFIG_FSL_LAYERSCAPE. Also make the error message more concise. Signed-off-by: Michael Walle <michael@walle.cc>
| * mmc: fsl_esdhc_imx: remove the 1ms delay before sending commandHaibo Chen2020-10-121-7/+0
| | | | | | | | | | | | | | | | | | | | | | This 1ms delay before sending command already exist from the beginning of the fsl_esdhc driver added in year 2008. Now this driver has been split for two files: fsl_esdhc.c and fsl_esdhc_imx.c. fsl_esdhc_imx.c only for i.MX series. i.MX series esdhc/usdhc do not need this 1ms delay before sending any command. So remove this 1ms, this will save a lot time if handling a large mmc data. Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
| * mmc: do not send cmd13 if the parameter 'send_status' is 0 for __mmc_switchHaibo Chen2020-10-121-1/+3
| | | | | | | | | | | | | | | | According to the code logic in __mmc_switch, if the parameter 'send_status' is zero, no need to send cmd13, just wait the stated timeout time, then can return directly. Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
| * configs: lx2160ardb: enable eMMC HS400 mode supportYangbo Lu2020-10-123-0/+3
| | | | | | | | | | | | Enable eMMC HS400 mode support on LX2160ARDB. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
| * arm: dts: lx2160ardb: support eMMC HS400 modeYangbo Lu2020-10-121-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add properties related to eMMC HS400 mode. mmc-hs400-1_8v; bus-width = <8>; They had been already in kernel dts file since the first lx2160ardb dts patch. b068890 arm64: dts: add LX2160ARDB board support Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
| * mmc: fsl_esdhc: fix eMMC HS400 stability issueYangbo Lu2020-10-121-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There was a fix-up for eMMC HS400 stability issue in Linux. Patch link: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/ commit/?id=58d0bf843b49fa99588ac9f85178bd8dfd651b53 Description: Currently only LX2160A eSDHC supports eMMC HS400. According to a large number of tests, eMMC HS400 failed to work at 150MHz, and for a few boards failed to work at 175MHz. But eMMC HS400 worked fine on 200MHz. We hadn't found the root cause but setting eSDHC_DLLCFG0[DLL_FREQ_SEL] = 0 using slow delay chain seemed to resovle this issue. Let's use this as fixup for now. Introduce the fix-up in u-boot since the issue could be reproduced in u-boot too. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
| * mmc: fsl_esdhc: fix mmc->clock with actual clockYangbo Lu2020-10-121-0/+3
| | | | | | | | | | | | | | | | Fix mmc->clock with actual clock which is divided by the controller, and record it with priv->clock which was removed accidentally. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
| * mmc: fsl_esdhc: support eMMC HS400 modeYangbo Lu2020-10-122-34/+98
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The process for eMMC HS400 mode for eSDHC is, 1. Perform the Tuning Process at the HS400 target operating frequency. Latched the clock division value. 2. if read transaction, then set the SDTIMNGCTL[FLW_CTL_BG]. 3. Switch to High Speed mode and then set the card clock frequency to a value not greater than 52Mhz 4. Clear TBCTL[TB_EN],tuning block enable bit. 5. Change to 8 bit DDR Mode 6. Switch the card to HS400 mode. 7. Set TBCTL[TB_EN], tuning block enable bit. 8. Clear SYSCTL[SDCLKEN] 9. Wait for PRSSTAT[SDSTB] to be set 10. Change the clock division to latched value.Set TBCTL[HS 400 mode] and Set SDCLKCTL[CMD_CLK_CTRL] 11. Set SYSCTL[SDCLKEN] 12. Wait for PRSSTAT[SDSTB] to be set 13. Set DLLCFG0[DLL_ENABLE] and DLLCFG0[DLL_FREQ_SEL]. 14. Wait for delay chain to lock. 15. Set TBCTL[HS400_WNDW_ADJUST] 16. Again clear SYSCTL[SDCLKEN] 17. Wait for PRSSTAT[SDSTB] to be set 18. Set ESDHCCTL[FAF] 19. Wait for ESDHCCTL[FAF] to be cleared 20. Set SYSCTL[SDCLKEN] 21. Wait for PRSSTAT[SDSTB] to be set. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
| * mmc: add a mmc_hs400_prepare_ddr() interfaceYangbo Lu2020-10-123-1/+33
| | | | | | | | | | | | | | | | Add a mmc_hs400_prepare_ddr() interface for controllers which needs preparation before switching to DDR mode for HS400 mode. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
| * mmc: add a hs400_tuning flagYangbo Lu2020-10-122-0/+3
| | | | | | | | | | | | | | | | | | | | | | Some controllers may have difference between HS200 tuning and HS400 tuning, such as different registers setting, different procedure, or different errata. This patch is to add a hs400_tuning flag to identify the tuning for HS400 mode. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
| * mmc: fsl_esdhc: clean TBCTL[TB_EN] manually during initYangbo Lu2020-10-121-0/+3
| | | | | | | | | | | | | | Clean TBCTL[TB_EN] manually during init since it is not able to be reset by reset all operation. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
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