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* arm64: zynqmp: Enable cadence WDT for zcu100Michal Simek2018-05-113-1/+4
| | | | | | | | | | | | Enable watchdog on zcu100 to make sure if there is a bug in the u-boot there is proper reset. Watchdog expires and PMU fw is informed and based on setting proper action is taken. The patch is enabling reset-on-timeout feature and also fixing fixed clock rate for watchdog where 100MHz is max (and also default) clock value. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* arm64: zynqmp: Wire watchdog internalsMichal Simek2018-05-111-0/+42
| | | | | | | | | | Enable watchdog in full U-Boot. Similar changes were done by: "arm: zynq: Wire watchdog internals" (sha1: e6cc3b25d721c3001019f8b44bfaae2a57255162) Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* watchdog: cadence: Show used timeout valueMichal Simek2018-05-111-2/+2
| | | | | | | | Debug message was showing timeout value which was passed to start function but there is a checking if this value can be setup. The patch is moving this debug printf function below checking. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* arm64: zynqmp: Reset FPD Watchdog on zcu100Michal Simek2018-05-111-1/+1
| | | | | | | Low level configuration didn't reset FPD Watchdog that's why accessing it caused u-boot hang. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* nand: zynq: Send address cycles as per onfi parameter pageSiva Durga Prasad Paladugu2018-05-111-1/+15
| | | | | | | | | | Send address cycles as per value read from onfi parameter page for Read and write commands instead of using a hard coded value. This may vary for different parts and hence use it from onfi parameter page value. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* nand: zynq: Add support for 16-bit buswidthSiva Durga Prasad Paladugu2018-05-111-0/+38
| | | | | | | | This patch adds support for 16-bit buswidth by determining the bus width based on mio configuration. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* MAINTAINERS: zynqmp: Point to proper zynqmp folderMichal Simek2018-05-111-1/+1
| | | | | | Point to Zynqmp arm64 cpu folder not to Zynq arm32. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* serial: zynq: Remove header depedency on arm header structureMichal Simek2018-05-111-1/+0
| | | | | | There is no need to have arm hardware header in this driver. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* timer: Add Cadence TTC timer counter supportMichal Simek2018-05-114-0/+100
| | | | | | This driver was tested on Xilinx ZynqMP SoC. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* microblaze: Dont enable UBI support by defaultSiva Durga Prasad Paladugu2018-05-111-4/+0
| | | | | | | | This patch removes UBI support from defconfig and it can be enabled from menuconfig as per need. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* arm64: zynqmp: Add new defconfig for zc1275 revBSiva Durga Prasad Paladugu2018-05-115-0/+674
| | | | | | | | | This patch enables support zc1275 revB board. It has SD added compared to revA. The same configuration will work for RevC boards aswell. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* scsi: ceva: Convert driver to use UCLASS_AHCI instead of SCSIMichal Simek2018-05-111-16/+20
| | | | | | | | | | | In v2018 the patch "dm: ahci: Correct uclass private data" (sha1: bfc1c6b4838501d10aa48c0e92eaf70976f4b2dd) was causing an issue for ceva_sata. But this issue is not in v2018.05-rc1 but still converting to UCLASS_AHCI would make more sense. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* arm: zynq: Remove checkboard and enable DISPLAY_CPUINFOMichal Simek2018-05-1119-34/+19
| | | | | | | | | | | | | | | | | | | | | | Now that showing silicon version is part of the CPU info display, let's remove checkboard(). Note that the generic show_board_info() will still show the DT 'model' property. For instance: U-Boot 2018.05-rc2-00025-g611b3ee0159b (Apr 19 2018 - 11:23:12 +0200) CPU: Zynq 7z045 Silicon: v1.0 Model: Zynq ZC706 Development Board I2C: ready Based on patches from Ariel D'Alessandro <ariel@vanguardiasur.com.ar>, and Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> mini configuration doesn't need to show this information. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* arm: zynq: Rework FPGA initializationMichal Simek2018-05-115-119/+101
| | | | | | | | | | This commit moves the FPGA descriptor definition to mach-zynq, where it makes more sense. Based on patches from Ariel D'Alessandro <ariel@vanguardiasur.com.ar> and Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* arm: zynq: Enable debug_uart_init in spl when enabledMichal Simek2018-05-111-5/+6
| | | | | | | In past this code was commented and was used for debug purpose. But there is no reason not to enabled it based on macros. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* Merge git://git.denx.de/u-boot-ubiTom Rini2018-05-101-0/+4
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| * ubifs: avoid assert failed in ubifs.cPatrice Chotard2018-05-091-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch solves assert failed displayed in the console during a boot. The root cause is that the ubifs_inode is not already allocated when ubifs_printdir and ubifs_finddir functions are called. Trace showing the issue: feed 'boot.scr.uimg', ino 94, new f_pos 0x17b40ece dent->ch.sqnum '7132', creat_sqnum 3886945402880 UBIFS assert failed in ubifs_finddir at 436 INODE ALLOCATION: creat_sqnum '7129' Found U-Boot script /boot.scr.uimg Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
* | Merge git://git.denx.de/u-boot-sunxiTom Rini2018-05-0914-171/+748
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| * board: sunxi: sun8i-v40: Add Bananapi M2 Berry supportJagan Teki2018-05-074-1/+153
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Banana Pi BPI-M2 Berry is a quad-core mini single board computer built with Allwinner V40 SoC. It features - Quad Core ARM Cortex A7 CPU V40 - 1GB of RAM . - microSD/SATA port.. - onboard WiFi and BT - 4 USB A 2.0 ports - 1 USB OTG port - 1 HDMI port - 1 audio jack - DC power port Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
| * ARM: dts: sun8i: Sync r40 dtsi from LinuxJagan Teki2018-05-073-0/+360
| | | | | | | | | | | | | | | | | | | | | | | | Sync sun8i-r40.dtsi changes from Linux with Merge: a406778618d0 088345fc3553 Author: Stephen Rothwell <sfr@canb.auug.org.au> Date: Tue Apr 24 14:15:02 2018 +1000 Merge branch 'akpm/master' Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * sunxi: Sort dts Makefile entries for H3Chen-Yu Tsai2018-05-011-5/+5
| | | | | | | | | | | | | | | | | | The dts Makefile entries for the H3 are not ordered correctly. Move the Nano Pi entries before the Orange Pi so they are. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * sunxi: Add Libre Computer Board ALL-H3-CC H5 ver.Chen-Yu Tsai2018-05-014-0/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds a device tree file for the H5 version of the Libre Computer Board ALL-H3-CC. It is the same board first introduced in commit afe27544125e ("sunxi: Add support for Libre Computer Board ALL-H3-CC H3 ver."), with the H3 SoC replaced with the H5 SoC, and has 4Gb DDR3 chips instead of 2Gb ones. The device tree utilizes the common board design file for ALL-H3-CC, providing just the model strings and SoC specifics. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * sunxi: Add Libre Computer Board ALL-H3-CC H2+ ver.Chen-Yu Tsai2018-05-014-1/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds a device tree file for the H2+ version of the Libre Computer Board ALL-H3-CC. It is the same board first introduced in commit afe27544125e ("sunxi: Add support for Libre Computer Board ALL-H3-CC H3 ver."), with the H3 SoC replaced with the H2+ SoC, and has only two 2Gb DDR3 chips instead of four. The device tree utilizes the common board design file for ALL-H3-CC, providing just the model strings and SoC specifics. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * sunxi: Split out common board design for ALL-H3-CC device treeChen-Yu Tsai2018-05-012-164/+170
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Libre Computer Project ALL-H3-CC has three models, all using the same board design, but with different pin compatible SoCs and amount of DRAM. Currently only the H3 1GB DRAM variant is supported. To support the two other variants, first split the original device tree into a common board design part and an SoC specific part. The SoC part only defines which SoC is used and model name, and includes the SoC specific dtsi file and the common design dtsi file. Also fix up the SPDX identifier line to use the correct comment style, and place it on the first line. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * sunxi: Disable R_I2C for Libre Computer Board ALL-H3-CC H3 ver.Chen-Yu Tsai2018-05-011-2/+0
| | | | | | | | | | | | | | | | | | | | | | The Libre Computer Board ALL-H3-CC does not have an I2C controllable regulator. Having R_I2C and SPL_I2C enabled serves no purpose. Disable them. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
* | bootm.c: Correct the flush_len used in bootm_load_os()Tom Rini2018-05-081-14/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In do_bootm_states when doing BOOTM_STATE_LOADOS we use load_end uninitialized and Coverity notes this now. This however leads down another interesting path. We pass this pointer to bootm_load_os and that in turn uses this uninitialized value immediately to calculate the flush length, and is wrong. We do not know what load_end will be until after bootm_decomp_image is called, so we must only set flush_len after that. All of this also makes it clear that the only reason we pass a pointer for load_end to bootm_load_os is so that we can call lmb_reserve on success. Rather than initialize load_end to 0 in do_bootm_states we can just call lmb_reserve ourself. Reported-by: Coverity (CID: 175572) Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | image: fit: Show signatures and hashes for configurationsClément Péron2018-05-081-0/+13
| | | | | | | | | | | | | | | | | | | | | | The signature/hash information are displayed for images but nor for configurations. Add subnodes printing in fit_conf_print() like it's done in fit_image_print() Signed-off-by: Clément Péron <peron.clem@gmail.com> [trini: Add guards around fit_conf_print to avoid warnings] Signed-off-by: Tom Rini <trini@konsulko.com>
* | arm: bitops: fix find_next_zero_bit() for case size < 32Grygorii Strashko2018-05-081-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | find_next_zero_bit() incorrectly handles cases when: - total bitmap size < 32 - rest of bits to process static inline int find_next_zero_bit(void *addr, int size, int offset) { unsigned long *p = ((unsigned long *)addr) + (offset >> 5); unsigned long result = offset & ~31UL; unsigned long tmp; if (offset >= size) return size; size -= result; offset &= 31UL; if (offset) { tmp = *(p++); tmp |= ~0UL >> (32-offset); if (size < 32) [1] goto found_first; if (~tmp) goto found_middle; size -= 32; result += 32; } while (size & ~31UL) { tmp = *(p++); if (~tmp) goto found_middle; result += 32; size -= 32; } [2] if (!size) return result; tmp = *p; found_first: [3] tmp |= ~0UL >> size; ^^^ algo can reach above line from from points: [1] offset > 0 and size < 32, tmp[offset-1..0] bits set to 1 [2] size < 32 - rest of bits to process in both cases bits to search are tmp[size-1..0], but line [3] will simply set all tmp[31-size..0] bits to 1 and ffz(tmp) below will fail. example: bitmap size = 16, offset = 0, bitmap is empty. code will go through the point [2], tmp = 0x0 after line [3] => tmp = 0xFFFF and ffz(tmp) will return 16. found_middle: return result + ffz(tmp); } Fix it by correctly seting tmp[31..size] bits to 1 in the above case [3]. Fixes: 81e9fe5a2988 ("arm: implement find_next_zero_bit function") Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
* | cmd: add ADC cli commandsNeil Armstrong2018-05-083-0/+129
| | | | | | | | | | | | | | Add an 'adc' cli command to get information from adc devices and to read "single shot" data. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* | pci: Don't use pci_indirect when DM is activeMario Six2018-05-081-1/+1
| | | | | | | | | | | | | | | | | | Declaration of indirect PCI bridges is not compatible with DM: Both define PCI operations, but in different ways. Hence, don't use indirect bridges if DM is active. Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Simon Glass <sjg@chromium.org>
* | gdsys: drivers: Add gdsys_rxaui_ctrl driverMario Six2018-05-083-1/+82
| | | | | | | | | | | | | | Add a driver for RXAUI control on IHS FPGAs. Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Simon Glass <sjg@chromium.org>
* | clk: Add ICS8N3QV01 driverMario Six2018-05-083-0/+239
| | | | | | | | | | | | Add a driver for the ICS8N3QV01 Quad-Frequency Programmable VCXO. Signed-off-by: Mario Six <mario.six@gdsys.cc>
* | ihs_mdio: Make DM-compatibleMario Six2018-05-082-5/+58
| | | | | | | | | | | | | | Make the ihs_mdio driver DM-compatible, while retaining the old functionality for not-yet-converted boards. Signed-off-by: Mario Six <mario.six@gdsys.cc>
* | ihs_mdio: Encapsulate register accessMario Six2018-05-081-7/+34
| | | | | | | | | | | | | | To prepare for DM conversion, encapsulate all register accesses in function calls. Signed-off-by: Mario Six <mario.six@gdsys.cc>
* | db410c: set clk node to be probed before relocationRamon Fried2018-05-082-1/+12
| | | | | | | | | | | | | | | | | | The clock node is used by the serial driver and it's needed before relocation. This patch ensures that the msm-serial driver can actually use the clock node. Signed-off-by: Ramon Fried <ramon.fried@linaro.org>
* | ARM: dts: sti: Add stih410-b2260-u-boot.dtsiPatrice Chotard2018-05-081-0/+16
| | | | | | | | | | | | | | | | | | | | | | STiH410 has 2 PHYs wired on the DWC3 IP, USB2 and USB3 PHYs. As currently no U-boot driver is available for the USB3 PHY and to avoid issue during DWC3 drive probe, we use DWC3 IP with only USB2 PHY using stih410-b2260-u-boot.dtsi file. Fixes: 2fd4242cc50e ("ubs: xhci-dwc3: Enable USB3 PHY when available") Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
* | arm: ti: boot: Extract PARTS_DEFAULT to boot.hSam Protsenko2018-05-085-52/+29
| | | | | | | | | | | | | | | | Eliminate code duplication: the same PARTS_DEFAULT was defined in am57xx_evm.h and in dra7xx_evm.h. Extract it to environment/boot.h and use in all OMAP5-based boards. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
* | Merge git://git.denx.de/u-boot-mmcTom Rini2018-05-0812-328/+32
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| * | power: pwm regulator: support live treeAndy Yan2018-05-081-11/+4
| | | | | | | | | | | | | | | | | | | | | Use live tree compatible api for pwm regulator. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * | dm: mmc: socfpga: call dwmci_probe()Patrick Bruenn2018-05-081-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On a socfpga_cyclone5 based board the SD card, was never powered up. For other dw_mmc based SoCs dwmci_probe() is called in the platform specific probe(). It seems this call is missing for socfpga_dw_mmc. With this change DWMCI_PWREN is set by dmwci_init(). Signed-off-by: Patrick Bruenn <p.bruenn@beckhoff.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
| * | mmc: Kconfig: add the MMC_TRACE config in KconfigJaehoon Chung2018-05-081-0/+8
| | | | | | | | | | | | | | | | | | Add the MMC_TRACE config in Kconfig. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
| * | mmc: add the debug message in mmc_set_clockJaehoon Chung2018-05-081-0/+2
| | | | | | | | | | | | | | | | | | | | | Add the debug message for checking the mmc clock status. It's helpful to debug the controlling clock. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
| * | mmc: add the MMC_CLK_ENABLE/DISABLE macro in mmc.hJaehoon Chung2018-05-084-10/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | mmc_set_clock() function has the disable argument as bool type. When mmc_set_clock is called, it might be passed to "true" or "false". But it's too confusion whether clock is enabled or disabled with only "true" and "false". To prevent the confusion, replace to MMC_CLK_ENABLE/DISABLE macro from true/false. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
| * | lib: fdtdec: drop the old compatible about max77686Jaehoon Chung2018-05-082-2/+0
| | | | | | | | | | | | | | | | | | | | | Drop the old compatible about max77686. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Acked-by: Lukasz Majewski <lukma@denx.de>
| * | power: pmic_max77686: remove the old pmic_max77686 fileJaehoon Chung2018-05-082-304/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | max77686 pmic is supporting with max77686.c under pmic/ and regulator/ direnctroy. Remove pmic_max77686.c what didn't use anywhere. Instead, enable CONFIG_DM_REGULATOR_MAX77686 and CONFIG_DM_PMIC_MAX77686. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
| * | configs: trats2: enable the max77686 regulator configJaehoon Chung2018-05-081-0/+2
| | | | | | | | | | | | | | | | | | Enable the CONFIG_DM_REGULATOR_MAX77686 for using regulator driver. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
* | | Merge git://git.denx.de/u-boot-uniphierTom Rini2018-05-085-24/+190
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| * | | ARM: uniphier: enable CONFIG_PINCONFMasahiro Yamada2018-05-081-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Enable the pin configuration feature for UniPhier 64 bit SoCs. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | | pinctrl: uniphier: add ethernet TX pin data for LD20Masahiro Yamada2018-05-081-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | These are necessary to optimize the drive-strength of the pins. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | | pinctrl: uniphier: support drive-strength configurationMasahiro Yamada2018-05-082-5/+140
| | | | | | | | | | | | | | | | | | | | | | | | This allows our DT to specify drive-strength property. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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