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* efi_loader: carve out utf_to_cp()Heinrich Schuchardt2021-03-074-16/+71
| | | | | | | | Carve out a function to translate a Unicode code point to an 8bit codepage. Provide a unit test for the new function. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
* efi_loader: move codepage 437 tableHeinrich Schuchardt2021-03-073-1/+12
| | | | | | Move the Unicode to codepage 437 table to charset.c Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
* efi_loader: console size of vidconsoleHeinrich Schuchardt2021-03-071-1/+1
| | | | | | | | | | If stdout is 'vidconsole', we correctly set the console size. If stdout is 'vidconsole,serial', the video console is ignored. We should always evaluate the size of vidconsole if it is the primary console. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
* Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriqTom Rini2021-03-0664-817/+924
|\ | | | | | | | | | | | | - Convert qemu-ppce500 to driver model and enable additional driver support - bug fixes/updates in net-dsa driver, vid driver, move configs to kconfig - Update Maintainers of some powerpc, layerscape platforms
| * doc: Add a reST document for qemu-ppce500Bin Meng2021-03-052-0/+89
| | | | | | | | | | | | | | | | | | Add a reST document to describe how to build and run U-Boot for the QEMU ppce500 machine. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * ppc: qemu: Move board directory from board/freescale to board/emulationBin Meng2021-03-055-3/+5
| | | | | | | | | | | | | | | | | | | | board/emulation is the place for other QEMU targets like x86, arm, riscv. Let's move the qemu-ppce500 board codes there. List me as a co-maintainer for this board. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * ppc: qemu: Drop fixed_sdram()Bin Meng2021-03-051-5/+0
| | | | | | | | | | | | | | | | | | | | This function is not called anywhere. Only fsl_ddr_sdram_size() is necessary [1] for QEMU. Drop it. [1] arch/powerpc/cpu/mpc85xx/cpu.c::dram_init() Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * ppc: qemu: Drop a custom env variable 'fdt_addr_r'Bin Meng2021-03-052-4/+1
| | | | | | | | | | | | | | | | | | Now that we have switched to CONFIG_OF_CONTROL, and we can use the env variable 'fdtcontroladdr' directly instead of creating one that is duplicated. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * ppc: qemu: Delete the temporary FDT virtual-physical mapping after U-Boot is ↵Bin Meng2021-03-051-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | relocated After U-Boot is relocated to RAM already, the previous temporary FDT virtual-physical mapping that was used in the pre-relocation phase is no longer needed. Let's delete the mapping. get_fdt_virt() might be used before and after relocation, update it to return different virtual address of FDT. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * ppc: qemu: Enable RTC support via I2CBin Meng2021-03-052-0/+6
| | | | | | | | | | | | | | | | | | The QEMU ppce500 target integrates a Freescale I2C controller and has a Pericom pt7c4338 RTC connected to it. Enable corresponding DM drivers so that 'date' command is actually useful. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * ppc: qemu: Enable support for power off via GPIOBin Meng2021-03-051-1/+5
| | | | | | | | | | | | | | | | | | The QEMU ppce500 target provides the power off functionality via the GPIO pin#0, and we can support this using the sysreset gpio poweroff driver. Let's enable it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * dm: sysreset: Add a Kconfig option for the 'reset' commandBin Meng2021-03-052-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | sysreset uclass driver provides an implementation of 'reset' command using the sysreset_ APIs unconditionally. It also supports the 'poweroff' command using the sysreset_ APIs, but under a Kconfig option CONFIG_SYSRESET_CMD_POWEROFF. Let's do the same for the 'reset' command, by introducing a new Kconfig option CONFIG_SYSRESET_CMD_RESET, and set it to on by default, to allow a board that don't have a sysreset reset driver yet, but have a sysreset poweroff driver to compile without any issue. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * ppc: qemu: Enable GPIO supportBin Meng2021-03-051-0/+3
| | | | | | | | | | | | | | | | | | QEMU ppce500 target integrates a GPIO controller that is compatible with the QorIQ GPIO controller. Enable the DM GPIO driver for it and the 'gpio' command. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * gpio: mpc8xxx: Support controller register physical address beyond 32-bitBin Meng2021-03-052-4/+5
| | | | | | | | | | | | | | | | | | dev_read_addr_size_index() returns fdt_addr_t which might be a 64-bit physical address. This might be true for some 85xx SoCs whose CCSBAR is mapped beyond 4 GiB. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * ppc: mpc85xx: Add 'gpibe' register to 'struct ccsr_gpio'Bin Meng2021-03-051-0/+1
| | | | | | | | | | | | | | | | Without this, the DM GPIO driver for MPC8xxx does not compile for MPC85xx SoCs. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * ppc: qemu: Enable VirtIO BLK supportBin Meng2021-03-051-0/+3
| | | | | | | | | | | | | | | | Enable VirtIO BLK driver so that we can store a kernel image to a disk image and boot from there. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * virtio: Fix VirtIO BLK driver dependencyBin Meng2021-03-051-0/+1
| | | | | | | | | | | | | | | | | | The VirtIO BLK driver depends on the blk uclass driver. Add the dependency in the Kconfig. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * ppc: qemu: Enable VirtIO NET supportBin Meng2021-03-052-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | By default the QEMU ppce500 machine connects a VirtIO NET to the PCI controller, although it can be replaced to an e1000 NIC via additional command line options. Now that we have switched over to DM PCI, VirtIO support becomes possible. This commit enables the support. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * cmd: Fix virtio command dependencyBin Meng2021-03-051-0/+1
| | | | | | | | | | | | | | | | | | The 'virtio' command calls blk_common_cmd() which is only available when CONFIG_HAVE_BLOCK_DEVICE is on. Fix the Kconfig dependency. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * ppc: qemu: Drop CONFIG_OF_BOARD_SETUPBin Meng2021-03-052-8/+0
| | | | | | | | | | | | | | ft_board_setup() is now empty. Drop it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * ppc: qemu: Switch over to use DM ETH and PCIBin Meng2021-03-053-104/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present the board supports non-DM version PCI and E1000 drivers. Switch over to use DM ETH and PCI by: - Rewrite the PCI address map functions using DM APIs - Enable CONFIG_MISC_INIT_R to do the PCI initialization and address map - Drop unnecessary ad-hoc config macros - Remove board_eth_init() in the board codes Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * pci: mpc85xx: Support 64-bit bus and cpu addressBin Meng2021-03-051-8/+8
| | | | | | | | | | | | | | | | | | | | | | At present the driver only supports 32-bit bus and cpu address. The controller's outbound registers/fields for extended address are not programmed. Let's program them to support 64-bit bus and cpu address. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * pci: mpc85xx: Support controller register physical address beyond 32-bitBin Meng2021-03-051-3/+2
| | | | | | | | | | | | | | | | | | | | devfdt_get_addr_index() returns fdt_addr_t which might be a 64-bit physical address. Use map_physmem() to return the virtual address that can be used by a 32-bit machine. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * pci: mpc85xx: Wrap LAW programming with CONFIG_FSL_LAWBin Meng2021-03-051-0/+4
| | | | | | | | | | | | | | | | | | | | | | For the QEMU ppce500 machine, LAW registers are not implemented hence CONFIG_FSL_LAW is not turned on and all LAW APIs are not available. We should wrap all LAW registers programming in the mpc85xx PCI driver with CONFIG_FSL_LAW. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * ppc: qemu: Switch over to use DM serialBin Meng2021-03-053-10/+7
| | | | | | | | | | | | | | | | | | | | | | | | The QEMU ppce500 target integrates 2 NS16550 serial ports. Switch over to use the DM version of the driver by: - drop unnecessary ad-hoc config macros - add get_serial_clock() in the board codes Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * common: Move initr_addr_map() to a bit earlierBin Meng2021-03-051-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | At present initr_addr_map() is put at a late stage in the init_sequence_r[] calls. This won't work because lot of device driver initialization (e.g.: serial port) happens before it but is lack of the address translation support. This moves the call to a bit earlier, right after the DM initialization. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * ppc: io.h: Use addrmap_ translation APIs only in post-relocation phaseBin Meng2021-03-051-6/+9
| | | | | | | | | | | | | | | | | | | | | | | | In phys_to_virt() and virt_to_phys(), if CONFIG_ADDR_MAP is defined, they use addrmap_ translation APIs to do the address translation. However these APIs only work in post-relocation phase. Update the code logic to fall back to use the default one when in pre-relocation phase. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * lib: kconfig: Mention CONFIG_ADDR_MAP limitation in the helpBin Meng2021-03-051-0/+2
| | | | | | | | | | | | | | | | Mention that CONFIG_ADDR_MAP only works in the post-relocation phase. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * test: cmd: Add a basic test for 'addrmap' commandBin Meng2021-03-054-0/+47
| | | | | | | | | | | | | | | | | | This adds a basic test for the newly introduced 'addrmap' command. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> [Rebase] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
| * cmd: Add a command to display the address mapBin Meng2021-03-055-0/+85
| | | | | | | | | | | | | | | | | | This adds a new command 'addrmap' to display the address map for non-identity virtual-physical memory mappings. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * lib: addr_map: Move address_map[] type to the header fileBin Meng2021-03-052-5/+9
| | | | | | | | | | | | | | | | | | | | At present address_map[] is static and its type is unknown to external modules. In preparation to create a command to list its contents, this patch moves its type definition and declaration to the header file. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * include: Remove extern from addr_map.hBin Meng2021-03-051-4/+4
| | | | | | | | | | | | | | | | Remove the extern of the header because they are useless. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * ppc: qemu: Enable driver modelBin Meng2021-03-051-0/+2
| | | | | | | | | | | | | | | | | | At present QEMU ppce500 target has not been migrated to driver model yet. As a start, let's enable driver model and the 'dm' command. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * ppc: qemu: Enable OF_CONTROLBin Meng2021-03-052-1/+12
| | | | | | | | | | | | | | | | | | | | The QEMU ppce500 machine generates a device tree blob and passes it to U-Boot during boot. Let's enable OF_CONTROL with OF_BOARD and provide board_fdt_blob_setup() in the board codes. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * ppc: qemu: Drop board_early_init_f()Bin Meng2021-03-052-6/+0
| | | | | | | | | | | | | | This function does nothing. Drop it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * ppc: qemu: Drop init_laws() and print_laws()Bin Meng2021-03-051-10/+0
| | | | | | | | | | | | | | These are no longer needed. Drop them. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * ppc: mpc85xx: Wrap LAW related codes with CONFIG_FSL_LAWBin Meng2021-03-052-0/+4
| | | | | | | | | | | | | | LAW related codes should be wrapped with CONFIG_FSL_LAW. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * ppc: qemu: Fix CONFIG_SYS_PCI_MAP_ENDBin Meng2021-03-051-1/+1
| | | | | | | | | | | | | | | | | | | | | | CONFIG_SYS_PCI_MAP_END currently points to 0xe8000000, which means the upper end of the virtual address mapped to PCI bus address ends at 0xe8000000. But this is wrong as the CCSBAR was already mapped at 0xe0000000 with a 1 MiB size. Fixes: fa08d3951777 ("PPC 85xx: Add qemu-ppce500 machine") Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * ppc: qemu: Support non-identity PCI bus addressBin Meng2021-03-051-15/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When QEMU originally supported the ppce500 machine back in Jan 2014, it was created with a 1:1 mapping of PCI bus address. Things seemed to change rapidly that in Nov 2014 with the following QEMU commits: commit e6b4e5f4795b ("PPC: e500: Move CCSR and MMIO space to upper end of address space") and commit cb3778a0455a ("PPC: e500 pci host: Add support for ATMUs") the PCI memory and IO physical address were moved to beyond 4 GiB, but PCI bus address remained below 4 GiB, hence a non-identity mapping was created. Unfortunately corresponding U-Boot updates were missed along with the QEMU changes and the U-Boot QEMU ppce500 PCI support has been broken since then. This commit makes the PCI (non-DM version) work again. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * common: fdt_support: Support special case of PCI address in fdt_read_prop()Bin Meng2021-03-051-3/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present fdt_read_prop() can only handle 1 or 2 cells. It is called by fdt_read_range() which may be used to read PCI address from <ranges> for a PCI bus node where the number of PCI address cell is 3. The <ranges> property is an array of: { <child address> <parent address> <size in child address space> } When trying to read <child address> from a PCI bus node using fdt_read_prop(), as the codes below: /* Read <child address> */ if (child_addr) { r = fdt_read_prop(ranges, ranges_len, cell, child_addr, acells); if (r) return r; } it will fail, because the PCI child address is made up of 3 cells but fdt_read_prop() cannot handle it. We advance the cell offset by 1 so that the <child address> can be correctly read. This adds the special handling of such case. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * ppc: qemu: Update MAINTAINERS for correct email addressBin Meng2021-03-051-1/+1
| | | | | | | | | | | | | | | | Alex's previous email address is no longer reachable. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * pci: fsl_pci_init: Dynamically allocate the PCI regionsBin Meng2021-03-051-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit e002474158d1 ("pci: pci-uclass: Dynamically allocate the PCI regions") changes 'struct pci_controller'.regions from pre-allocated array of regions to dynamically allocated, which unfortunately broken lots of boards that still use the non-DM PCI driver. This patch changes the non-DM fsl_pci_init driver to dynamically allocate the regions, just like what's done in the pci uclass driver. Fixes: e002474158d1 ("pci: pci-uclass: Dynamically allocate the PCI regions") Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * net: dsa: remove master santiy checkMichael Walle2021-03-051-21/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Because we probe the master ourselves (and fail if there is no master), it is not possible that we don't have a master device. There is one catch though: device removal. We don't support that. It wasn't supported neither before this patch. Because the master device was only set in .pre_probe(), if a device was removed master_dev was a dangling pointer and transmitting a frame cause a panic. I don't see a good solution without having some sort of notify machanism when a udevice is removed. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Tested-by: Michael Walle <michael@walle.cc> [DSA unit tests] Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * net: dsa: remove NULL check for priv and platform dataMichael Walle2021-03-051-14/+7
| | | | | | | | | | | | | | | | | | | | | | Because the uclass has the "*_auto" properties set, the driver model will take care of allocating the private structures for us and they can't be NULL. Drop the checks. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * net: dsa: probe master deviceMichael Walle2021-03-051-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DSA needs to have the master device probed first for MAC inheritance. Until now, it only works by chance because the only user (LS1028A SoC) will probe the master device first. The probe order is given by the PCI device ordering, thus it works because the master device has a "smaller" BDF then the switch device. Explicitly probe the master device in dsa_port_probe(). Fixes: fc054d563bfb ("net: Introduce DSA class for Ethernet switches") Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * net: dsa: return early if there is no masterMichael Walle2021-03-051-4/+4
| | | | | | | | | | | | | | | | | | | | | | It doesn't make sense to have DSA without a master port. Error out early if there is no master port. Fixes: fc054d563bfb ("net: Introduce DSA class for Ethernet switches") Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * board: ls1012aqds: Update MAINTAINERSPriyanka Jain2021-03-051-1/+1
| | | | | | | | | | | | | | Update LS1012AQDS Board MAINTAINERS entries to current MAINTAINERS. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
| * board: lx2160a: Update MAINTAINERSPriyanka Jain2021-03-051-1/+0
| | | | | | | | | | | | | | Update LX2160AQDS BOARD MAINTAINER entry to current MAINTAINER. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
| * board: ls1046ardb: Update MAINTAINERSPriyanka Jain2021-03-051-7/+0
| | | | | | | | | | | | | | Update LS1046ARDB BOARD MAINTAINERS entries to current MAINTAINERS. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
| * board: ls1046aqds: Update MAINTAINERSPriyanka Jain2021-03-051-3/+0
| | | | | | | | | | | | | | Update LS1046AQDS BOARD MAINTAINERS entries to current MAINTAINERS. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
generated by cgit (git 2.34.1) at 2024-09-22 21:34:54 +0000