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* ARM: socfpga: Drop last use of socfpga_reset_managerMarek Vasut2020-02-031-4/+1
| | | | | | | | | | | | | | This particular chunk of code was not updated, likely due to the order in which the patches were posted and applied. Fix this missing part. Fixes: bb25aca13433 ("arm: socfpga: Convert reset manager from struct to defines") Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dalon Westergreen <dwesterg@gmail.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
* reset: socfpga: Poll for reset status after deassert resetLey Foon Tan2020-02-031-1/+5
| | | | | | | | | | | In Cyclone 5 SoC platform, the first USB probing is failed but second probing is success. DWC2 USB driver read gsnpsid register right after de-assert reset, but controller is not ready yet and it returns gsnpsid 0. Polling reset status after de-assert reset to solve the issue. Retry with this fix more than 10 times without issue. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
* Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini2020-02-023-1/+17
|\ | | | | | | - DFU and Cadence USB 3 fixes
| * dfu: Add option to skip empty pages when flashing UBI images to NANDGuillermo Rodríguez2020-02-022-1/+13
| | | | | | | | | | | | | | | | | | | | Add a new option to enable the DROP_FFS flag when flashing UBI images to NAND in order to drop trailing all-0xff pages. This is similar to the existing FASTBOOT_FLASH_NAND_TRIMFFS option. Signed-off-by: Guillermo Rodriguez <guille.rodriguez@gmail.com> Cc: Lukasz Majewski <lukma@denx.de>
| * usb: cdns3: ep0: Invalidate cache before reading Setup PacketVignesh Raghavendra2020-02-021-0/+4
| | | | | | | | | | | | | | Invalidate dcache line before accessing Setup Packet contents. Otherwise driver will see stale content on non coherent architecture. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
* | Merge tag 'u-boot-rockchip-20200130' of ↵Tom Rini2020-02-0167-841/+1465
|\ \ | |/ |/| | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip - Support redundant boot for rk3399 - Support binman for rockchip platform - Update ram driver and add ddr4 support for rk3328
| * configs: firefly-rk3399: Enable CONFIG_MISC_INIT_R and ROCKCHIP_EFUSEMark Kettenis2020-01-301-0/+3
| | | | | | | | | | | | | | | | This enables readning the cpuid from e-fuse, and deriving a static MAC address from it. Signed-off-by: Mark Kettenis <kettenis@openbsd.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * rockchip: rk3308: add alias for emmc/sdmmcKever Yang2020-01-301-0/+7
| | | | | | | | | | | | | | Add alias for mmc/sdmmc so that we can have a fix mmc number for emmc. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * rockchip: px30: remove CONFIG_OPTEE supportKever Yang2020-01-302-2/+0
| | | | | | | | | | | | | | Rockchip use CONFIG_SPL_OPTEE for OPTEE support, which is load and run before U-Boot, but not use CONFIG_OPTEE which is after U-Boot. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
| * ram: rk3328: update lpddr3 settingYouMin Chen2020-01-301-4/+4
| | | | | | | | | | | | | | update lpddr3 setting for fix init fail about "col error". Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
| * ram: rk3328: add support ddr4 initYouMin Chen2020-01-301-0/+216
| | | | | | | | | | | | | | Add rk3328-sdram-ddr4-666.dtsi for support ddr4 init. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
| * ram: rk3328: only do data traning for cs0Kever Yang2020-01-301-7/+3
| | | | | | | | | | | | | | | | | | No need to do twice data training for rk3328 ddr sdram, we re-use the setting for both channel. And adjust the sdram_init properly for correct init flow. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: YouMin Chen <cym@rock-chips.com>
| * doc: boards: Add rockchip documentationJagan Teki2020-01-302-0/+140
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rockchip has documentation file, doc/README.rockchip but which is not so readable to add or understand the existing contents. Even the format that support is legacy readme in U-Boot. Add rockchip specific documentation file using new rst format, which describes the information about Rockchip supported boards and it's usage steps. Added minimal information about rk3288, rk3328, rk3368 and rk3399 boards and usage. This would indeed updated further based on the requirements and updates. Cc: Kever Yang <kever.yang@rock-chips.com> Cc: Matwey V. Kornilov <matwey.kornilov@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * rockchip: Add Single boot image (with binman, pad_cat)Jagan Teki2020-01-308-4/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All rockchip platforms support TPL or SPL-based bootloader in mainline with U-Boot proper as final stage. For each stage we need to burn the image on to flash with respective offsets. This patch creates a single boot image component using - binman, for arm32 rockchip platforms - pad_cat, for arm64 rockchip platforms. This would help users to get rid of burning different boot stage images. The new image called 'u-boot-rockchip.bin' which can burn into flash like: ₹ sudo dd if=u-boot-rockchip.bin of=/dev/sda seek=64 This would support all rockchip platforms, except rk3128 since it doesn't support for SPL yet. Cc: Matwey V. Kornilov <matwey.kornilov@gmail.com> Cc: Wadim Egorov <w.egorov@phytec.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * arm: dts: rk3188: Add rk3188-u-boot.dtsiJagan Teki2020-01-302-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | Add U-Boot specific dtsi file for rk3188 SoC. This would help to add U-Boot specific dts nodes, properties which are common across rk3188. Right now, the file is empty, will add required changes in future patches. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * arm: dts: rk3036: Add rk3036-u-boot.dtsiJagan Teki2020-01-302-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | Add U-Boot specific dtsi file for rk3036 SoC. This would help to add U-Boot specific dts nodes, properties which are common across rk3036. Right now, the file is empty, will add required changes in future patches. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * Makefile: rockchip: Support SPL-alone mkimageJagan Teki2020-01-301-1/+9
| | | | | | | | | | | | | | | | | | | | | | Add SPL-alone mkimage tooling support via Makefile for few platforms or boards used in rockchip family. With this users would get rid of explicitly creating mkimage tool for rockchip rksd or rkspi boot modes. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * Makefile: rockchip: Suffix platform type with tpl nameJagan Teki2020-01-301-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Most of the platforms uses the platform type on their boot stage image naming conventions in makefile like, u-boot-x86-start16-tpl.bin - x86 start16 TPL bin u-boot-spl-mtk.bin - Mediatek SPL bin This would help to understand the users to what that particular image belongs to? and less confused. On that note, suffix platform type rockchip for existing u-boot-tpl.img so now it become u-boot-tpl-rockchip.bin Also, bin is more conventional way to include it on tools like binman, pad_cat etc in future patches. Note: usage of platform type doesn't follow consistent order as of now. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * Makefile: Add rockchip image typeJagan Teki2020-01-301-1/+9
| | | | | | | | | | | | | | | | | | | | Add rockchip image type support. right now the image type marked with rksd, So create image type variable with required image type like rksd or rkspi. Cc: Matwey V. Kornilov <matwey.kornilov@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * rockchip: rk3399: Add bootcount supportJagan Teki2020-01-303-1/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add bootcount support for Rockchip rk3399. The bootcount value is preserved in PMU_SYS_REG0 register, this would help to support redundent boot. Once the redundant boot triggers, the altboot command will look for extlinux-rollback.conf on particular bootable partition which supposed to be a recovery partition where redundant boot required. Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * rockchip: Add common reset causeJagan Teki2020-01-304-52/+62
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add cpu reset cause in common cpu-info file. This would help to print the reset cause for various resets. Right now it support rk3288, rk3399. rest of rockchip platforms doesn't have reset cause support ye but this code is more feasible to extend the same. Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * arm: rockchip: Add common cru.hJagan Teki2020-01-3015-68/+85
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Few of the rockchip family SoC atleast rk3288, rk3399 are sharing some cru register bits so adding common code between these SoC families would require to include both cru include files that indeed resulting function declarations error. So, create a common cru include as cru.h then include the rk3399 arch cru include file and move the common cru register bit definitions into it. The rest of rockchip cru files will add it in future. Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * rockchip: rk3399: Enable DISPLAY_CPUINFOJagan Teki2020-01-3024-24/+0
| | | | | | | | | | | | | | | | RK3288, RK3399 are now support cpu-info, so enable DISPLAY_CPUINFO by default. Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * rockchip: Add cpu-infoJagan Teki2020-01-302-0/+17
| | | | | | | | | | | | | | | | | | | | Add cpu information for rockchip soc. This would help to print the SoC family number, with associated temparature, clock and reason for reset etc. Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * rockpro-rk3399: Enable SPI FlashJagan Teki2020-01-302-0/+6
| | | | | | | | | | | | | | Enable winbond SPI flash for ROC-PC-RK3399 board. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * roc-pc-rk3399: Enable SPI FlashJagan Teki2020-01-302-0/+6
| | | | | | | | | | | | | | Enable winbond SPI flash for ROC-PC-RK3399 board. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * rockchip: dts: Sync ROC-RK3399-PC changes from LinuxJagan Teki2020-01-302-670/+816
| | | | | | | | | | | | | | | | | | | | | | Sync the ROC-RK3399-PC device tree changes from Linux with below commit details: commit <c36308abe4110e4db362d5e2ae3797834a7b1192> ("arm64: dts: rockchip: Enable MTD Flash on rk3399-roc-pc") Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * env: Enable SPI flash env for rockchipJagan Teki2020-01-301-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | Most of the SPI flash devices in rockchip are 16MiB size. So, keeping U-Boot proper offset start from 128MiB with 1MiB size and then start env of 8KiB would be a compatible location between all variants of flash sizes. This patch add env start from 0x14000 with a size of 8KiB. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * env: kconfig: Restrict rockchip env for MMCJagan Teki2020-01-301-2/+3
| | | | | | | | | | | | | | | | | | | | | | Rockchip do support SPI flash as well, so there is a possibility of using flash environment for those use cases. So, restrict the current env offset, size for MMC. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * rk3399: Check MMC env while defining itJagan Teki2020-01-301-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | rk3399 do support SPI flash as well, so there is a possibility of using flash environment for those usecases. So define env device for MMC only when it is used by specific configuration. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * ram: rk3399: don't assume phy_io_config() uses real regsThomas Hebb2020-01-301-4/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the RK3399 DRAM driver, the function set_ds_odt() supports operating in two different modes, selected by the ctl_phy_reg argument: when true, the function reads and writes directly from the DRAM registers, accessed through "chan->pctl->denali_*"; when false, the function reads and writes from an array, accessed through "params->pctl_regs.denali_*", which is written to DRAM registers at a later time. However, phy_config_io(), which is called by set_ds_odt() to do a subset of its register operations, operates directly on DRAM registers at all times. This means that it reads incorrect values (and writes new values prematurely) when ctl_phy_reg in set_ds_odt() is false. Fix this by passing in the address of the registers to work with. This prevents an "Invalid DRV value" error in the SPL debug log and (presumably) results in a more correct end state. See the following logs from a RK3399 NanoPi M4 board (4GB LPDDR3): Before: sdram_init() Starting SDRAM initialization... phy_io_config() Invalid DRV value. phy_io_config() Invalid DRV value. sdram_init() sdram_init: data trained for rank 2, ch 0 phy_io_config() Invalid DRV value. phy_io_config() Invalid DRV value. sdram_init() sdram_init: data trained for rank 2, ch 1 Channel 0: LPDDR3, 933MHz BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB Channel 1: LPDDR3, 933MHz BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB 256B stride 256B stride sdram_init() Finish SDRAM initialization... After: sdram_init() Starting SDRAM initialization... sdram_init() sdram_init: data trained for rank 2, ch 0 sdram_init() sdram_init: data trained for rank 2, ch 1 Channel 0: LPDDR3, 933MHz BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB Channel 1: LPDDR3, 933MHz BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB 256B stride 256B stride sdram_init() Finish SDRAM initialization... Signed-off-by: Thomas Hebb <tommyhebb@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* | Merge tag 'uniphier-v2020.04-2' of ↵Tom Rini2020-01-3115-113/+65
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-uniphier UniPhier SoC updates for v2020.04 (2nd) Denali NAND driver changes: - Set up more registers in denali-spl for SOCFPGA - Make clocks optional - Do not assert reset signals in the remove hook - associate SPARE_AREA_SKIP_BYTES with DT compatible - switch to UCLASS_MTD UniPhier platform changes: - fix a bug in dram_init() - specify loadaddr for "source" command
| * | ARM: uniphier: use $loadaddr for source commandMasahiro Yamada2020-02-011-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If the "source" command is not given the address, it uses CONFIG_SYS_LOAD_ADDR, which is compile-time determined. Using the "loadaddr" environment variable is handier because it is relocated according to the memory base when CONFIG_POSITION_INDEPENDENT is enabled. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: uniphier: set gd->ram_base correctlyMasahiro Yamada2020-02-011-6/+1
| | | | | | | | | | | | | | | | | | | | | gd->ram_base is not set at all if the end address of the DRAM ch0 exceeds the 4GB limit. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | mtd: rawnand: denali_dt: use UCLASS_MTD instead of UCLASS_MISCMasahiro Yamada2020-02-013-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | UCLASS_MTD is a better fit for NAND drivers. Make NAND_DENALI_DT depend on DM_MTD, which is needed to compile drivers/mtd/mtd-uclass.c Also, make ARCH_UNIPHIER select DM_MTD because all the defconfig of this platform enables NAND_DENALI_DT. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
| * | ARM: uniphier: remove adhoc reset deassertion for the NAND controllerMasahiro Yamada2020-02-017-73/+8
| | | | | | | | | | | | | | | | | | | | | Now that the reset controlling of the Denali NAND driver (denali_dt.c) works for this platform, remove the adhoc reset deassert code. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | mtd: rawnand: denali: set SPARE_AREA_SKIP_BYTES based on DT compatibleMasahiro Yamada2020-02-012-9/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, the denali NAND driver in U-Boot configures the SPARE_AREA_SKIP_BYTES based on the CONFIG option. Recently, Linux kernel merged a patch that associates the proper value for this register with the DT compatible string. Do likewise in U-Boot too. The denali_spl.c still uses CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | mtd: rawnand: denali_dt: insert udelay() after reset deassertMasahiro Yamada2020-02-011-2/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When the reset signal is de-asserted, the HW-controlled bootstrap starts running unless it is disabled in the SoC integration. It issues some commands to detect a NAND chip, and sets up registers automatically. Until this process finishes, software should avoid any register access. Without this delay function, some of UniPhier boards hangs up while executing nand_scan_ident(). (denali_read_byte() is blocked) Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | mtd: rawnand: denali: Do not reset the block before booting the kernelMarek Vasut2020-02-012-13/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Denali NAND driver in mainline Linux currently cannot deassert the reset. The upcoming Linux 5.6 will support the reset controlling, and also set up SPARE_AREA_SKIP_BYTES correctly. So, the Denali driver in the future kernel will work without relying on any bootloader or firmware. However, we still need to take care of stable kernel versions for a while. U-boot should not assert the reset of this controller. Fixes: ed784ac3822b ("mtd: rawnand: denali: add reset handling") Signed-off-by: Marek Vasut <marex@denx.de> [yamada.masahiro: reword the commit description] Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | mtd: rawnand: denali_dt: make the core clock optionalMasahiro Yamada2020-02-011-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | The "nand_x" and "ecc" clocks are currently optional. Make the core clock optional in the same way. This will allow platforms with no clock driver support to use this driver. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Tested-by: Marek Vasut <marex@denx.de> # On SoCFPGA Arria V
| * | mtd: rawnand: denali-spl: Add missing hardware init on SoCFPGAMarek Vasut2020-02-011-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On Altera SoCFPGA, upon either cold-boot or power-on reset, the Denali NAND IP is initialized by the BootROM ; upon warm-reset, the Denali NAND IP is NOT initialized by BootROM. In fact, upon warm-reset, the SoCFPGA BootROM checks whether the SPL image in on-chip RAM is valid and if so, completely skips re-loading the SPL from the boot media. This does sometimes lead to problems where the software left the boot media in inconsistent state before warm-reset, and because the BootROM does not reset the boot media, the boot media is left in this inconsistent state, often until another component attempts to access the boot media and fails with an difficult to debug failure. To mitigate this problem, the SPL on Altera SoCFPGA always resets all the IPs on the SoC early on boot. This results in a couple of register values, pre-programmed by the BootROM, to be lost during this reset. To restore correct operation of the IP on SoCFPGA, these values must be programmed back into the controller by the driver. Note that on other SoCs which do not use the HW-controlled bootstrap, more registers may have to be programmed. This also aligns the SPL behavior with the full Denali NAND driver, which sets these values in denali_hw_init(). Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | | Merge branch '2020-01-30-master-imports'Tom Rini2020-01-3016-108/+56
|\ \ \ | |_|/ |/| | | | | | | | | | | - Assorted minor fixes - Revert 6dcb8ba4 from upstream libfdt to restore boot-time speed on many platforms.
| * | Remove redundant YYLOC global declarationPeter Robinson2020-01-301-1/+0
| | | | | | | | | | | | | | | | | | Same as the upstream fix for building dtc with gcc 10. Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
| * | Makefile: Fix the location of the migration fileFabio Estevam2020-01-301-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since commit e1910d93b890 ("doc: driver-model: Convert MIGRATION.txt to reST") MIGRATION.txt has been converted to migration.rst, so update the Makefile references accordingly. Fixes: e1910d93b890 ("doc: driver-model: Convert MIGRATION.txt to reST") Signed-off-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * | tools: buildman: fix typoFlavio Suligoi2020-01-301-1/+1
| | | | | | | | | | | | | | | Signed-off-by: Flavio Suligoi <f.suligoi@asem.it> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | net: fix typoFlavio Suligoi2020-01-301-1/+1
| | | | | | | | | | | | Signed-off-by: Flavio Suligoi <f.suligoi@asem.it>
| * | MAINTAINERS: board: hisi: poplar: update emailJorge Ramirez-Ortiz2020-01-301-1/+1
| | | | | | | | | | | | Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
| * | MAINTAINERS: board: qcom: db820c: update emailJorge Ramirez-Ortiz2020-01-301-1/+1
| | | | | | | | | | | | Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
| * | libfdt: Revert 6dcb8ba4 from upstream libfdtTom Rini2020-01-303-52/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In upstream libfdt, 6dcb8ba4 "libfdt: Add helpers for accessing unaligned words" introduced changes to support unaligned reads for ARM platforms and 11738cf01f15 "libfdt: Don't use memcpy to handle unaligned reads on ARM" improved the performance of these helpers. In practice however, this only occurs when the user has forced the device tree to be placed in memory in a non-aligned way, which in turn violates both our rules and the Linux Kernel rules for how things must reside in memory to function. This "in practice" part is important as handling these other cases adds visible (1 second or more) delay to boot in what would be considered the fast path of the code. Cc: Patrice CHOTARD <patrice.chotard@st.com> Cc: Patrick DELAUNAY <patrick.delaunay@st.com> Link: https://www.spinics.net/lists/devicetree-compiler/msg02972.html Signed-off-by: Tom Rini <trini@konsulko.com> Tested-by: Patrice Chotard <patrice.chotard@st.com>
| * | Consistently use nproc for counting the CPUsHeinrich Schuchardt2020-01-303-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | Coreutils command nproc can be used on Linux and BSD to count the number of available CPU cores. Use this instead of relying on the parsing of the Linux specific proc file system. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
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