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* Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini2017-09-2310-18/+49
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| * armv8: ls1046ardb: disable PPA loading during SPL stage for SD bootYangbo Lu2017-09-221-1/+0
| | | | | | | | | | | | | | | | PPA loading during SPL stage is not required for nornal SD boot scenario. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: ls1043ardb: disable PPA loading during SPL stage for SD bootYangbo Lu2017-09-221-1/+0
| | | | | | | | | | | | | | | | PPA loading during SPL stage is not required for nornal SD boot scenario. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: ls1043a: disable IFC in SPL only when QSPI is usedYangbo Lu2017-09-221-1/+1
| | | | | | | | | | | | | | | | | | | | Current u-boot disables IFC support for SD boot on all ls1043a boards. Actually IFC only conflicts with QSPI on ls1043a hardware. Only when QSPI is used, IFC should be disabled. Otherwise, the u-boot with ls1043aqds_sdcard_ifc_defconfig would not work. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * board/ls2080ardb: Update board env based on SoCPriyanka Jain2017-09-221-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | As per current implementation, default value of board env is based on board filename i.e ls2080ardb. With distro support changes, this env is used to decide upon kernel dtb which is different for other SoCs (ls2088a, ls2081a) combination supported with this board. Add support to modify board env at runtime based on SoC type Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * board/ls2080ardb: Add mcmemsize variable in default envPriyanka Jain2017-09-221-0/+1
| | | | | | | | | | | | | | | | | | For most of ls2080ardb use-cases, mc private DRAM block is required to be of 1.75GB. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> [YS: this reservation needs to be reduced if memory is not enough] Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: fsl: i2c: Put I2C related code under CONFIG_SYS_I2CSriram Dash2017-09-221-1/+1
| | | | | | | | | | | | | | I2C code is put under CONFIG_SYS_I2C. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: fsl: ifc: Put IFC related code under CONFIG_FSL_IFCSriram Dash2017-09-222-0/+12
| | | | | | | | | | | | | | IFC code is put under CONFIG_FSL_IFC Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * pci: layerscape: Fixup iommu-map for LS208xABharat Bhushan2017-09-221-5/+14
| | | | | | | | | | | | | | | | | | | | | | Commit 0aaa1a9 added support for LS208xA devices but fixing iommu-map property is missing. This patch adds support for fixing iommu-map. Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com> Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> [YS: revised commit message] Reviewed-by: York Sun <york.sun@nxp.com>
| * board/ls2081ardb: Update QSPI flash type from n25q512a to s25fs512sSantan Kumar2017-09-222-7/+3
| | | | | | | | | | | | | | | | | | | | | | | | As per updated board design, different QSPI flash is connected on boards, hence change QSPI flash type from Micron n25q512a device to spansion s25fs512s device in dts and config. Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * board/ls2080ardb: Remove CONFIG_DISPLAY_BOARDINFO_LATESantan Kumar2017-09-221-1/+0
| | | | | | | | | | | | | | | | | | | | CONFIG_DISPLAY_BOARDINFO_LATE config is used to delay the prints of boardinfo late in cycle during uboot boot. This feature is not required in case of QSPI_BOOT. Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: fsl-layerscape: Put SATA code under SATA configsAshish Kumar2017-09-221-0/+4
| | | | | | | | | | | | | | | | | | It is not necessary for every SoC to have 2 SATA controller. So put SATA1, SATA2 code under respective defines. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv7: ls1021a: Fix marco CONFIG_LS102XAYork Sun2017-09-221-1/+1
|/ | | | | | | Commit a8ecb39e accidentally reverted config macro CONFIG_ARCH_LS1021A to CONFIG_LS102XA. Signed-off-by: York Sun <york.sun@nxp.com>
* Travis-CI: Checkout only v1.4.3 of dtcTom Rini2017-09-221-1/+1
| | | | | | Our minimum DTC version is 1.4.3, so check that out. Signed-off-by: Tom Rini <trini@konsulko.com>
* net/tftp: fix build if CMD_BOOTEFI is not setJörg Krause2017-09-221-0/+2
| | | | | | | | Fixes: net/tftp.c:811: undefined reference to `efi_set_bootdev' Signed-off-by: Jörg Krause <joerg.krause@embedded.rocks> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* Makefile: Update minimum dtc version to 1.4.3Tom Rini2017-09-222-5/+6
| | | | | | | | | With support for overlays and calling the -@ flag to dtc we need to have at least 1.4.3 available now. Cc: Simon Glass <sjg@chromium.org> Reported-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Tom Rini <trini@konsulko.com>
* spl: Fix compiling warning on gunzip argumentYork Sun2017-09-221-1/+4
| | | | | | | | | | common/spl/spl_fit.c:201:12: warning: passing argument 4 of ‘gunzip’ from incompatible pointer type [-Wincompatible-pointer-types] src, &length)) Signed-off-by: York Sun <york.sun@nxp.com> Reported-by: Heinrich Schuchardt <xypron.glpk@gmx.de> CC: Jean-Jacques Hiblot <jjhiblot@ti.com>
* arm: am33xx: Make pin multiplexing functions optionalFelix Brack2017-09-221-0/+14
| | | | | | | | | This patch provides default implementations of the two functions set_uart_mux_conf and set_mux_conf_regs. Hence boards not using them do not need to provide their distinct empty definitions. Signed-off-by: Felix Brack <fb@ltec.ch> Reviewed-by: Tom Rini <trini@konsulko.com>
* board: Add stm32h7 SoC, discovery and evaluation boards supportPatrice Chotard2017-09-2219-0/+585
| | | | | | | | | | | This patch adds support for stm32h7 soc family, stm32h743 discovery and evaluation boards. For more information about STM32H7 series, please visit: http://www.st.com/en/microcontrollers/stm32h7-series.html Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* ARM: DTS: stm32: adapt stm32h7 dts files for U-bootPatrice Chotard2017-09-226-28/+294
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adapts stm32h743 disco and eval dts files to match with U-boot requirements or add features wich are not yet upstreamed on kernel side : _ Add RCC clock driver node and update all clocks phandle accordingly. By default, on kernel side, all clocks was temporarly configured as a phandle to timer_clk waiting for a RCC clock driver to be available. On U-boot side, we now have a dedicated RCC clock driver, we can configured all clocks as phandle to this driver. All this binding update will be available soon in a kernel tag, as all the bindings have been acked by Rob Herring [1]. [1] http://lkml.iu.edu/hypermail/linux/kernel/1704.0/00935.html _ Align STM32H7 serial compatible string with the one which will be available in next kernel tag. The bindings has been acked by Rob Herring [2]. This compatible string will be usefull to add stm32h7 specific feature for this serial driver. [2] https://lkml.org/lkml/2017/7/17/739 _ Add gpio compatible and aliases for stm32h743 _ Add FMC sdram node with associated new bindings value to manage second bank (ie bank 1). _ Add missing HSI and CSI oscillators nodes needed by STM32H7 RCC clock driver. Clock sources could be: _ HSE (High Speed External) _ HSI (High Speed Internal) _ CSI (Low Power Internal) These clocks can be used as clocksource in some configuration. By default, HSE is selected as clock source. _ Set HSE to 25Mhz for stm32h743i-disco and eval board By default, the external oscillator frequency is defined at 25 Mhz in SoC stm32h743.dtsi file. It has been set at 125 Mhz in kernel DT temporarly waiting for RCC clock driver becomes available. As in U-boot we got a RCC clock driver, the real value of HSE clock can be used. _ Add "u-boot,dm-pre-reloc" for rcc, fmc, fixed-clock, pinctrl, pwrcfg and gpio nodes. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* ARM: DTS: stm32: add stm32h743i-eval filesPatrice Chotard2017-09-222-1/+76
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This file is imported from linux kernel v4.13 Add device tree support for STM32H743 evaluation board. This board offers : _ STM32H743XIH6 microcontroller with 2 Mbytes of Flash memory and 1 Mbyte of RAM in TFBGA240+25 package _ 5.7” 640x480 TFT color LCD with touch screen _ Ethernet compliant with IEEE-802.3-2002 _ USB OTG HS and FS _ I2 C compatible serial interface _ RTC with rechargeable backup battery _ SAI Audio DAC _ ST-MEMS digital microphones _ 8-Gbyte (or more) SDIO3.0 interface microSD™ card _ 8Mx32bit SDRAM, 1Mx16bit SRAM and 8Mx16bit NOR Flash _ 1-Gbit Twin Quad-SPI NOR Flash _ Potentiometer _ 4 colored user LEDs _ Reset, wakeup, tamper or key buttons _ Joystick with 4-direction control and selector _ Board connectors : Power jack 3 USB with Micro-AB RS-232 communications Ethernet RJ45 FD-CAN compliant connection Stereo headset jack including analog microphone input 2 audio jacks for external speakers microSD™ card JTAG/SWD and ETM trace _ Expansion connectors: Extension connectors and memory connectors for daughterboard or wire-wrap board _ Flexible power-supply options: ST-LINK USB VBUS or external sources _ On-board ST-LINK/V2-1 debugger/programmer with USB re-enumeration capability: mass storage, virtual COM port and debug port Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* ARM: DTS: stm32: add stm32h743i-disco filesPatrice Chotard2017-09-225-0/+1946
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All these files are imported from linux kernel v4.13 Add device tree support for STM32H743 SoC and discovery board. This board offers : _ STM32H743XIH6 microcontroller with 2 Mbytes of Flash memory and 1 Mbyte of RAM in TFBGA240+25 package _ 5.7” 640x480 TFT color LCD with touch screen _ Ethernet compliant with IEEE-802.3-2002 _ USB OTG HS _ I2 C compatible serial interface _ ST-MEMS digital microphones _ 8-Gbyte (or more) SDIO3.0 interface microSD™ card _ 8Mx32bit SDRAM _ 1-Gbit Twin Quad-SPI NOR Flash _ Reset, wakeup, or key buttons _ Joystick with 4-direction control and selector _ Board connectors : 1 USB with Micro-AB Ethernet RJ45 Stereo headset jack including analog microphone input microSD™ card RCA connector JTAG/SWD and ETM trace _ Expansion connectors: Arduino Uno compatible Connectors 2 x PIO connectors (PMOD and PMOD+) _ On-board ST-LINK/V2-1 debugger/programmer with USB re-enumeration capability: mass storage, virtual COM port and debug port Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* dm: misc: add stm32 rcc driverChristophe Kerello2017-09-223-0/+55
| | | | | | | | | | | | | | | This patch adds the support of reset and clock control block (rcc) found on STM32 SoCs. This driver is similar to a MFD linux driver. This driver supports currently STM32H7 only. STM32F4 and STM32F7 will be migrated to this rcc MFD driver in the future to uniformize all STM32 SoCs already upstreamed. Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* dm: reset: add stm32 reset driverPatrice Chotard2017-09-225-0/+232
| | | | | | | | | | | | | | | | | This driver is adapted from linux drivers/reset/reset-stm32.c It's compatible with STM32 F4/F7/H7 SoCs. This driver doesn't implement .of_match as it's binded by MFD RCC driver. To add support for each SoC family, a SoC's specific include/dt-binfings/mfd/stm32xx-rcc.h file must be added. This patch only includes stm32h7-rcc.h dedicated for STM32H7 SoCs. Other SoCs support will be added in the future. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* dm: clk: add clk driver support for stm32h7 SoCsPatrice Chotard2017-09-224-0/+1122
| | | | | | | | | | | | | | | | | | This driver implements basic clock setup, only clock gating is implemented. This driver doesn't implement .of_match as it's binded by MFD RCC driver. Files include/dt-bindings/clock/stm32h7-clks.h and doc/device-tree-bindings/clock/st,stm32h7-rcc.txt will be available soon in a kernel tag, as all the bindings have been acked by Rob Herring [1]. [1] http://lkml.iu.edu/hypermail/linux/kernel/1704.0/00935.html Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* serial: stm32x7: add STM32H7 supportPatrice Chotard2017-09-222-3/+6
| | | | | | | | STM32F7 and STM32H7 shares the same UART block, add STM32H7 compatible string. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* pinctrl: stm32: add stm32h743-pinctrl compatiblePatrice Chotard2017-09-221-0/+1
| | | | | | | | | STM32H7 SoCs uses the same pinctrl block as found into STM32F7 SoCs Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
* spl: stash bootstage info before jump to next stageKever Yang2017-09-221-7/+7
| | | | | | | | Since we may jump to next stage like ATF/OP-TEE instead of U-Boot, we need to stash the bootstage info before it. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* board: STiH410-B2260: add fastboot supportPatrice Chotard2017-09-221-0/+42
| | | | | | | | | Add usb_gadget_handle_interrupts(), board_usb_init(), board_usb_cleanup() and g_dnl_board_usb_cable_connected() callbacks needed for FASTBOOT support Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* ARM: dts: STiH410: update ehci and ohci compatiblePatrice Chotard2017-09-221-4/+7
| | | | | | | | Update ehci and ohci node's compatible string in order to use ehci-generic and ohci-generic drivers. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* ARM: dts: STiH410: set DWC3 dual role mode to peripheralPatrice Chotard2017-09-221-1/+1
| | | | | | | | | On STi 96boards, configure by default the micro USB connector (managed by DWC3 hardware block) in peripheral mode. This will allow to use fastboot feature. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* usb: dwc3: Add dwc3 glue driver support for STiPatrice Chotard2017-09-226-0/+379
| | | | | | | | | | | | This patch adds the ST glue logic to manage the DWC3 HC on STiH407 SoC family. It configures the internal glue logic and syscfg registers. Part of this code been extracted from kernel.org driver (drivers/usb/dwc3/dwc3-st.c) Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* STiH410-B2260: enable USB, fastboot, reset, PHY related flagsPatrice Chotard2017-09-221-4/+35
| | | | | Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* STiH410-B2260: enable USB Host NetworkingPatrice Chotard2017-09-221-0/+15
| | | | | | | | Enable USB Host Networking support by enabling Ethernet/USB adaptors support and by enabling some BOOTP flags Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* usb: phy: Add STi USB2 PHYPatrice Chotard2017-09-224-0/+214
| | | | | | | | | This is the generic phy driver for the picoPHY ports used by USB2/1.1 controllers. It is found on STiH407 SoC family from STMicroelectronics. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* mmc: sti_sdhci: Use reset frameworkPatrice Chotard2017-09-221-15/+20
| | | | | | Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* ARM: dts: stih410-family: Add missing reset_names for mmc1 nodePatrice Chotard2017-09-221-0/+1
| | | | | | | | | reset-names property is needed to use the reset API for STi sdhci driver. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* mmc: sti_sdhci: Rework sti_mmc_core_config()Patrice Chotard2017-09-221-15/+18
| | | | | | | | | | | Use struct udevice* as input parameter. Previous parameters are retrieved through plat and priv data. This to prepare to use the reset framework. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* pci: Remove unnecessary 'default n' from KconfigTuomas Tynkkynen2017-09-221-1/+0
| | | | | | | | | 'default n' is the default anyway so it doesn't need to be specified explicitly, and the rest of the file doesn't specify it either anywhere. Drop it. Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* pci: layerscape: Remove unused field 'hose' from struct ls_pcieTuomas Tynkkynen2017-09-221-1/+0
| | | | | | | This field is no longer used since the DM conversion. Drop it. Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* pci: tegra: Remove unused field 'hose' from struct tegra_pcieTuomas Tynkkynen2017-09-221-2/+0
| | | | | | | This field is no longer used since the DM conversion. Drop it. Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* pci: xilinx: Remove unused field 'hose' from struct xilinx_pcieTuomas Tynkkynen2017-09-221-2/+0
| | | | | | | | This field has never been used as the driver has been DM-based since the beginning. Drop it. Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* pci: xilinx: Fix doc comments on config space accessorsTuomas Tynkkynen2017-09-221-2/+2
| | | | | | | | | These take the 'struct udevice *' as an argument, not the 'struct xilinx_pcie *` which is a local variable. Fix the comments to match the code. Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* fs/fat: Reduce stack usageTom Rini2017-09-221-4/+10
| | | | | | | | | | | We have limited stack in SPL builds. Drop itrblock and move to malloc/free of itr to move this off of the stack. As part of this fix a double-free issue in fat_size(). Signed-off-by: Tom Rini <trini@konsulko.com> --- Rework to use malloc/free as moving this to a global overflows some SH targets.
* Merge branch 'next' of git://git.denx.de/u-boot-videoTom Rini2017-09-219-6/+657
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| * video: add config option to skip framebuffer clearRob Clark2017-09-123-2/+13
| | | | | | | | | | | | | | | | The use-case is that the thing that loaded u-boot already put a splash image on screen. And we want to preserve that until grub boot menu takes over. Signed-off-by: Rob Clark <robdclark@gmail.com>
| * video: simplefbRob Clark2017-09-123-1/+84
| | | | | | | | | | | | | | | | | | Not really qcom specific, but for now qcom/lk is the one firmware that is (afaiu) setting up the appropriate dt node for pre-configured display. Uses the generic simple-framebuffer DT bindings so this should be useful on other platforms. Signed-off-by: Rob Clark <robdclark@gmail.com>
| * video: add STM32 LTDC display controllerPhilippe CORNU2017-09-125-0/+463
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The STM32 LTDC display controller provides a parallel digital RGB and signals for horizontal, vertical synchronization, Pixel Clock and Data Enable as output to interface directly to a variety of LCD and TFT panels. The LTDC main features are: - 24-bit RGB Parallel Pixel Output, Programmable timings & polarity for HSync, VSync and Data Enable. - 2 layers with Blending, Color Keying, Window position & size, Dithering, Background color, Color Look-Up Table (CLUT). - Supported layer color formats: ARGB8888, RGB888, RGB565, ARGB1555, ARGB4444, L8 CLUT, AL44 & AL88 This LTDC driver: - supports: RGB parallel output with timings & polarity, 1 layer in RGB565. - supports but with hard-coded configurations: blending, window position & size (crop), background color. - does not support yet: rgb888, argb8888, 8-bit clut, dithering. This LTDC driver is compatible with all stm32 platforms with the LTDC IP and has been tested on stm32 f746-disco board. Signed-off-by: Philippe CORNU <philippe.cornu@st.com>
| * dm: backlight: Add a driver for GPIO backlightPatrick Delaunay2017-09-123-0/+85
| | | | | | | | | | | | | | | | Add a driver for GPIO backlights. It understands the standard device tree binding. It can be used with simple-panel when PWM is not necessary. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
| * dm: backlight: Add CONFIG_BACKLIGHT_PWMPatrick Delaunay2017-09-122-3/+12
| | | | | | | | | | | | | | Add a config to select individually the driver for PWM backlights. Manage "depends on" to be backyard compatible. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
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